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comparison packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl @ 2809:a0730cb32880

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* cdl/spi_lpc2xxx.cdl: Ensure the SPI interrupts are using different priorities: CYGNUM_IO_SPI_ARM_LPC2XXX_SPI{0,1}_INTPRIO entered. * include/spi_lpc2xxx.h: cyg_spi_lpc2xxx_bus_t: spi_prio field added. * src/spi_lpc2xxx.cxx: spi_lpc2xxx_set_config(): fixed copy & paste typo, spi_lpc2xxx_init_bus(): added 'prio' argument to initializer.
author jlarmour
date Tue, 17 Feb 2009 00:51:30 +0000
parents 74dbf4c3f2e1
children 782f0399f068
comparison
equal deleted inserted replaced
2808:ef21b86ad6b9 2809:a0730cb32880
55 active_if CYGPKG_IO_SPI 55 active_if CYGPKG_IO_SPI
56 56
57 include_dir cyg/io 57 include_dir cyg/io
58 compile spi_lpc2xxx.cxx 58 compile spi_lpc2xxx.cxx
59 59
60 cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 { 60 cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
61 display "Enable SPI interface 0" 61 display "Enable SPI interface 0"
62 flavor bool 62 flavor bool
63 default_value 1 63 default_value 1
64 description "The LPC2xxx controllers contain two SPI interfaces. 64 description "The LPC2xxx controllers contain two SPI interfaces.
65 Enable this option to get support for SPI interface 0." 65 Enable this component to get support for SPI
66 interface 0."
67
68 cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_BUS0_INTPRIO {
69 display "Interrupt priority of the SPI bus 0 ISR"
70 flavor data
71 legal_values 0 to 15
72 default_value 12
73 requires { is_active(CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
74 implies (CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO !=
75 CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
76 }
77 description "
78 This option specifies the interrupt priority of the ISR of
79 the SPI bus 0 interrupt in the VIC. Slot 0 has the highest
80 priority and slot 15 the lowest."
81 }
66 } 82 }
67 83
68 cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 { 84 cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
69 display "Enable SPI interface 1" 85 display "Enable SPI interface 1"
70 flavor bool 86 flavor bool
71 default_value 1 87 default_value 1
72 description "The LPC2xxx controllers contain two SPI interfaces. 88 description "The LPC2xxx controllers contain two SPI interfaces.
73 Enable this option to get support for SPI interface 1." 89 Enable this component to get support for SPI
90 interface 1."
91
92 cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO {
93 display "Interrupt priority of the SPI bus 1 ISR"
94 flavor data
95 legal_values 0 to 15
96 default_value 13
97 description "
98 This option specifies the interrupt priority of the ISR of
99 the SPI bus 1 interrupt in the VIC. Slot 0 has the highest
100 priority and slot 15 the lowest."
101 }
74 } 102 }
75 } 103 }