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diff packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl @ 2809:a0730cb32880

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* cdl/spi_lpc2xxx.cdl: Ensure the SPI interrupts are using different priorities: CYGNUM_IO_SPI_ARM_LPC2XXX_SPI{0,1}_INTPRIO entered. * include/spi_lpc2xxx.h: cyg_spi_lpc2xxx_bus_t: spi_prio field added. * src/spi_lpc2xxx.cxx: spi_lpc2xxx_set_config(): fixed copy & paste typo, spi_lpc2xxx_init_bus(): added 'prio' argument to initializer.
author jlarmour
date Tue, 17 Feb 2009 00:51:30 +0000
parents 74dbf4c3f2e1
children 782f0399f068
line wrap: on
line diff
--- a/packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl
+++ b/packages/devs/spi/arm/lpc2xxx/current/cdl/spi_lpc2xxx.cdl
@@ -57,19 +57,47 @@ cdl_package CYGPKG_DEVS_SPI_ARM_LPC2XXX 
     include_dir cyg/io
     compile     spi_lpc2xxx.cxx
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS0 {
         display       "Enable SPI interface 0"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
-                       Enable this option to get support for SPI interface 0."
+                       Enable this component to get support for SPI
+                       interface 0."
+
+        cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_BUS0_INTPRIO {
+            display       "Interrupt priority of the SPI bus 0 ISR"
+            flavor        data
+            legal_values  0 to 15
+            default_value 12
+            requires      { is_active(CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
+                             implies (CYGNUM_IO_SPI_ARM_LPC2XXX_SPI0_INTPRIO !=
+                             CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO)
+            }
+            description "
+                This option specifies the interrupt priority of the ISR of
+                the SPI bus 0 interrupt in the VIC. Slot 0 has the highest
+                priority and slot 15 the lowest."
+        }
     }
 
-    cdl_option CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
+    cdl_component CYGPKG_DEVS_SPI_ARM_LPC2XXX_BUS1 {
         display       "Enable SPI interface 1"
         flavor        bool
         default_value 1
         description   "The LPC2xxx controllers contain two SPI interfaces.
-                       Enable this option to get support for SPI interface 1."
+                       Enable this component to get support for SPI
+                       interface 1."
+
+        cdl_option CYGNUM_IO_SPI_ARM_LPC2XXX_SPI1_INTPRIO {
+            display       "Interrupt priority of the SPI bus 1 ISR"
+            flavor        data
+            legal_values  0 to 15
+            default_value 13
+            description "
+                This option specifies the interrupt priority of the ISR of
+                the SPI bus 1 interrupt in the VIC. Slot 0 has the highest
+                priority and slot 15 the lowest."
+        }
     }
 }