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comparison packages/hal/powerpc/ppc40x/current/src/var_intr.c @ 136:a9ac27ec7abc ecos-sw-2000-11-17

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Merge from eCos master repository on 2000-11-17-18:24:25-GMT
author jlarmour
date Fri, 17 Nov 2000 23:16:43 +0000
parents d2f49caf9e38
children 52c99470ec11
comparison
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135:3bc2abeae9ff 136:a9ac27ec7abc
41 //####DESCRIPTIONEND#### 41 //####DESCRIPTIONEND####
42 // 42 //
43 //========================================================================== 43 //==========================================================================
44 44
45 #include <pkgconf/hal.h> 45 #include <pkgconf/hal.h>
46 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
47 #include <cyg/hal/ppc_regs.h>
48 #include <cyg/hal/hal_intr.h>
46 #include <cyg/infra/cyg_type.h> 49 #include <cyg/infra/cyg_type.h>
50
51 static cyg_uint32 exier_mask[] = {
52 0x00000000, // Unused
53 0x00000000, // Unused
54 0x80000000, // CYGNUM_HAL_INTERRUPT_CRITICAL 2
55 0x08000000, // CYGNUM_HAL_INTERRUPT_SERIAL_RCV 3
56 0x04000000, // CYGNUM_HAL_INTERRUPT_SERIAL_XMT 4
57 0x02000000, // CYGNUM_HAL_INTERRUPT_JTAG_RCV 5
58 0x01000000, // CYGNUM_HAL_INTERRUPT_JTAG_XMT 6
59 0x00800000, // CYGNUM_HAL_INTERRUPT_DMA0 7
60 0x00400000, // CYGNUM_HAL_INTERRUPT_DMA1 8
61 0x00200000, // CYGNUM_HAL_INTERRUPT_DMA2 9
62 0x00100000, // CYGNUM_HAL_INTERRUPT_DMA3 10
63 0x00000010, // CYGNUM_HAL_INTERRUPT_EXT0 11
64 0x00000008, // CYGNUM_HAL_INTERRUPT_EXT1 12
65 0x00000004, // CYGNUM_HAL_INTERRUPT_EXT2 13
66 0x00000002, // CYGNUM_HAL_INTERRUPT_EXT3 14
67 0x00000001, // CYGNUM_HAL_INTERRUPT_EXT4 15
68 };
69
70 // This table inverts bit number to signal number
71 cyg_uint32 EXISR_TAB[] = {
72 CYGNUM_HAL_INTERRUPT_CRITICAL, // 0x80000000
73 0x00000000, // 0x40000000
74 0x00000000, // 0x20000000
75 0x00000000, // 0x10000000
76 CYGNUM_HAL_INTERRUPT_SERIAL_RCV, // 0x08000000
77 CYGNUM_HAL_INTERRUPT_SERIAL_XMT, // 0x04000000
78 CYGNUM_HAL_INTERRUPT_JTAG_RCV, // 0x02000000
79 CYGNUM_HAL_INTERRUPT_JTAG_XMT, // 0x01000000
80 CYGNUM_HAL_INTERRUPT_DMA0, // 0x00800000
81 CYGNUM_HAL_INTERRUPT_DMA1, // 0x00400000
82 CYGNUM_HAL_INTERRUPT_DMA2, // 0x00200000
83 CYGNUM_HAL_INTERRUPT_DMA3, // 0x00100000
84 0x00000000, // 0x00080000
85 0x00000000, // 0x00040000
86 0x00000000, // 0x00020000
87 0x00000000, // 0x00010000
88 0x00000000, // 0x00008000
89 0x00000000, // 0x00004000
90 0x00000000, // 0x00002000
91 0x00000000, // 0x00001000
92 0x00000000, // 0x00000800
93 0x00000000, // 0x00000400
94 0x00000000, // 0x00000200
95 0x00000000, // 0x00000100
96 0x00000000, // 0x00000080
97 0x00000000, // 0x00000040
98 0x00000000, // 0x00000020
99 CYGNUM_HAL_INTERRUPT_EXT0, // 0x00000010
100 CYGNUM_HAL_INTERRUPT_EXT1, // 0x00000008
101 CYGNUM_HAL_INTERRUPT_EXT2, // 0x00000004
102 CYGNUM_HAL_INTERRUPT_EXT3, // 0x00000002
103 CYGNUM_HAL_INTERRUPT_EXT4 // 0x00000001
104 };
105
106 cyg_uint32 _hold_tcr = 0; // Shadow of hardware register
47 107
48 externC void 108 externC void
49 hal_variant_IRQ_init(void) 109 hal_variant_IRQ_init(void)
50 { 110 {
51 // No special init required for 40x series. 111 cyg_uint32 iocr;
112
113 // Ensure all interrupts masked (disabled) & cleared
114 CYGARC_MTDCR(DCR_EXIER, 0);
115 CYGARC_MTDCR(DCR_EXISR, 0xFFFFFFFF);
116
117 // Configure all external interrupts to be level/low
118 CYGARC_MFDCR(DCR_IOCR, iocr);
119 iocr &= ~0xFFC00000;
120 CYGARC_MTDCR(DCR_IOCR, iocr);
121
122 // Disable timers
123 CYGARC_MTSPR(SPR_TCR, 0);
124 }
125
126 externC void
127 hal_ppc40x_interrupt_mask(int vector)
128 {
129 cyg_uint32 exier, tcr;
130
131 switch (vector) {
132 case CYGNUM_HAL_INTERRUPT_CRITICAL:
133 case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
134 case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
135 case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
136 case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
137 case CYGNUM_HAL_INTERRUPT_DMA0:
138 case CYGNUM_HAL_INTERRUPT_DMA1:
139 case CYGNUM_HAL_INTERRUPT_DMA2:
140 case CYGNUM_HAL_INTERRUPT_DMA3:
141 case CYGNUM_HAL_INTERRUPT_EXT0:
142 case CYGNUM_HAL_INTERRUPT_EXT1:
143 case CYGNUM_HAL_INTERRUPT_EXT2:
144 case CYGNUM_HAL_INTERRUPT_EXT3:
145 case CYGNUM_HAL_INTERRUPT_EXT4:
146 CYGARC_MFDCR(DCR_EXIER, exier);
147 exier &= ~exier_mask[vector];
148 CYGARC_MTDCR(DCR_EXIER, exier);
149 break;
150 case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
151 CYGARC_MFSPR(SPR_TCR, tcr);
152 tcr = _hold_tcr;
153 tcr &= ~TCR_PIE;
154 CYGARC_MTSPR(SPR_TCR, tcr);
155 _hold_tcr = tcr;
156 break;
157 case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
158 CYGARC_MFSPR(SPR_TCR, tcr);
159 tcr = _hold_tcr;
160 tcr &= ~TCR_FIE;
161 CYGARC_MTSPR(SPR_TCR, tcr);
162 _hold_tcr = tcr;
163 break;
164 case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
165 CYGARC_MFSPR(SPR_TCR, tcr);
166 tcr = _hold_tcr;
167 tcr &= ~TCR_WIE;
168 CYGARC_MTSPR(SPR_TCR, tcr);
169 _hold_tcr = tcr;
170 break;
171 default:
172 }
173 }
174
175 externC void
176 hal_ppc40x_interrupt_unmask(int vector)
177 {
178 cyg_uint32 exier, tcr;
179
180 switch (vector) {
181 case CYGNUM_HAL_INTERRUPT_CRITICAL:
182 case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
183 case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
184 case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
185 case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
186 case CYGNUM_HAL_INTERRUPT_DMA0:
187 case CYGNUM_HAL_INTERRUPT_DMA1:
188 case CYGNUM_HAL_INTERRUPT_DMA2:
189 case CYGNUM_HAL_INTERRUPT_DMA3:
190 case CYGNUM_HAL_INTERRUPT_EXT0:
191 case CYGNUM_HAL_INTERRUPT_EXT1:
192 case CYGNUM_HAL_INTERRUPT_EXT2:
193 case CYGNUM_HAL_INTERRUPT_EXT3:
194 case CYGNUM_HAL_INTERRUPT_EXT4:
195 CYGARC_MFDCR(DCR_EXIER, exier);
196 exier |= exier_mask[vector];
197 CYGARC_MTDCR(DCR_EXIER, exier);
198 break;
199 case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
200 CYGARC_MFSPR(SPR_TCR, tcr);
201 tcr = _hold_tcr;
202 tcr |= TCR_PIE;
203 CYGARC_MTSPR(SPR_TCR, tcr);
204 _hold_tcr = tcr;
205 break;
206 case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
207 CYGARC_MFSPR(SPR_TCR, tcr);
208 tcr = _hold_tcr;
209 tcr |= TCR_FIE;
210 CYGARC_MTSPR(SPR_TCR, tcr);
211 _hold_tcr = tcr;
212 break;
213 case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
214 CYGARC_MFSPR(SPR_TCR, tcr);
215 tcr = _hold_tcr;
216 tcr |= TCR_WIE;
217 CYGARC_MTSPR(SPR_TCR, tcr);
218 _hold_tcr = tcr;
219 break;
220 default:
221 }
222 }
223
224 externC void
225 hal_ppc40x_interrupt_acknowledge(int vector)
226 {
227 switch (vector) {
228 case CYGNUM_HAL_INTERRUPT_EXT0:
229 case CYGNUM_HAL_INTERRUPT_EXT1:
230 case CYGNUM_HAL_INTERRUPT_EXT2:
231 case CYGNUM_HAL_INTERRUPT_EXT3:
232 case CYGNUM_HAL_INTERRUPT_EXT4:
233 CYGARC_MTDCR(DCR_EXISR, exier_mask[vector]);
234 break;
235 case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
236 CYGARC_MTSPR(SPR_TSR, TSR_PIS); // clear & acknowledge interrupt
237 break;
238 case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
239 CYGARC_MTSPR(SPR_TSR, TSR_FIS); // clear & acknowledge interrupt
240 break;
241 case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
242 CYGARC_MTSPR(SPR_TSR, TSR_WIS); // clear & acknowledge interrupt
243 break;
244 case CYGNUM_HAL_INTERRUPT_CRITICAL:
245 case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
246 case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
247 case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
248 case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
249 case CYGNUM_HAL_INTERRUPT_DMA0:
250 case CYGNUM_HAL_INTERRUPT_DMA1:
251 case CYGNUM_HAL_INTERRUPT_DMA2:
252 case CYGNUM_HAL_INTERRUPT_DMA3:
253 default:
254 }
255 }
256
257 // Note: These functions are only [well] defined for "external" interrupts
258 // which can be controlled via the EXIER register.
259 externC void
260 hal_ppc40x_interrupt_configure(int vector, int level, int dir)
261 {
262 cyg_uint32 mask, new_state, iocr;
263
264 if ((vector >= CYGNUM_HAL_INTERRUPT_EXT0) &&
265 (vector <= CYGNUM_HAL_INTERRUPT_EXT4)) {
266 mask = 0x03 << (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
267 new_state = 0x00;
268 if (level == 0) {
269 // Edge triggered
270 new_state = 0x02 | (dir & 0x01); // Up/Down
271 }
272 new_state <<= (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
273 CYGARC_MFDCR(DCR_IOCR, iocr);
274 iocr = (iocr & ~mask) | new_state;
275 CYGARC_MTDCR(DCR_IOCR, iocr);
276 }
277 }
278
279 externC void
280 hal_ppc40x_interrupt_set_level(int vector, int level)
281 {
52 } 282 }
53 283
54 // ------------------------------------------------------------------------- 284 // -------------------------------------------------------------------------
55 // EOF var_intr.c 285 // EOF var_intr.c