changeset 2546:28ecf71a7103

* cdl/hal_arm_at91sam7s.cdl: Set MOR OSCCOUNT and PLL Count to values suggests by Atmel. This should make the startup stable for all devices
author asl
date Thu, 04 Sep 2008 06:10:22 +0000
parents 3e357a0a0869
children 3cff44606584
files packages/hal/arm/at91/at91sam7s/current/ChangeLog packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
diffstat 2 files changed, 11 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/packages/hal/arm/at91/at91sam7s/current/ChangeLog
+++ b/packages/hal/arm/at91/at91sam7s/current/ChangeLog
@@ -1,3 +1,9 @@
+2008-09-04  John Eigelaar  <jeigelaar@mweb.co.za>
+
+	* cdl/hal_arm_at91sam7s.cdl: Set MOR OSCCOUNT and PLL Count to
+	values suggests by Atmel. This should make the startup stable for
+	all devices.
+  	
 2008-09-02  John Eigelaar  <jeigelaar@mweb.co.za>
 
 	* include/plf_io.h: Added definitions for devices
--- a/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
+++ b/packages/hal/arm/at91/at91sam7s/current/cdl/hal_arm_at91sam7s.cdl
@@ -240,10 +240,11 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
         display       "Startup time for the main oscillator"
         flavor        data
         legal_values  { 0 to 255 }
-        default_value 6
+        default_value 64
         description   "
             Specifies the number of Slow Clock cycles multiplied by 8 
-	    for the Main Oscillator start-up time."
+	    for the Main Oscillator start-up time. 64 is the number suggested
+	    by the kind folk at Atmel"
     }       
 
     cdl_option CYGNUM_HAL_ARM_AT91_PLL_DIVIDER {
@@ -273,7 +274,8 @@ cdl_package CYGPKG_HAL_ARM_AT91SAM7 {
         default_value 16
         description   "
             Specifies the number of slow clock cycles before the LOCK bit 
-	    is set in PMC_SR after PLL Register is written."
+	    is set in PMC_SR after PLL Register is written. The Atmel people
+	    suggest that 16 should be fine"
     }       
     
     cdl_option CYGNUM_HAL_ARM_AT91_SLOW_CLOCK {