Mercurial > ecos-v3_0-branch
changeset 2553:514095c1a69f
The PATI HAL package provides the support needed to run
eCos on an PATI PC/104+ board from MPL elektronik.
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new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/ChangeLog @@ -0,0 +1,35 @@ +2008-05-08 Steven Clugston <steven.clugston@ncl.ac.uk> + + * New package. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/cdl/hal_powerpc_pati.cdl @@ -0,0 +1,279 @@ +# ==================================================================== +# +# hal_powerpc_pati.cdl +# +# PowerPC/pati board HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): Steven Clugston +# Original: Bob Koninckx, bartv +# Date: 2008-05-08 +# +#####DESCRIPTIONEND#### +# +# ==================================================================== + +cdl_package CYGPKG_HAL_POWERPC_PATI { + display "PATI MPC555 development board" + parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_POWERPC_MPC5xx + define_header hal_powerpc_pati.h + include_dir cyg/hal + description " + The PATI HAL package provides the support needed to run + eCos on an PATI PCI target board from MPL elektronik." + + compile hal_diag.c plf_misc.c pati.S plf_stub.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_powerpc_mpc5xx.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_powerpc_pati.h>" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + legal_values {"RAM" "ROM"} + default_value {"RAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the PATI board it is possible to build + the system for either RAM bootstrap or ROM bootstrap. RAM + bootstrap generally requires that the board + is equipped with ROMs containing a suitable ROM monitor or + equivalent software that allows GDB to download the eCos + application on to the board. The ROM bootstrap requires that + the eCos application be blown into the MPC555 internal flash + array. Both types of startup require the internal flash array to + be enabled." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + description " + The PATI has two serial ports." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + flavor data + legal_values 0 to 1 + default_value 0 + description " + The PATI has two serial ports. This option + chooses which port will be used to connect to a host running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 1 + description " + The PATI has two serial ports. This option + chooses which port will be used for diagnostic output." + } + + cdl_option CYGHWR_HAL_POWERPC_BOARD_SPEED { + display "Development board clock speed (MHz)" + flavor data + default_value 40 + description " + The board is fitted with a 4MHz crystal. This frequency + is internally boosted to maximum 40MHz. The value is fixed to the + maximum." + } + + cdl_option CYGHWR_HAL_POWERPC_FORCE_VECTOR_BASE_LOW { + display "Force vector base at address 0x0000 0000" + flavor bool + calculated 1 + description " + The PowerPC architecture allows the vectorbase to live at either + 0x0000 0000 or 0xfff0 0000. Since there is no memory at the + high addresses, vectors may never be located at 0xfff0 0000 for this + board. They can be still be copied though if the internal flash is + disabled and relocated to somewhere else" + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Baud rate for serial ports" + flavor data + legal_values 300 600 1200 2400 4800 9600 14400 19200 28800 38400 57600 115200 + default_value 57600 + description " + This option determines the baud rate that will be used on both the console + cannel and the debug channel." + } + + # Real-time clock/counter specifics + cdl_component CYGNUM_HAL_RTC_CONSTANTS { + display "Real-time clock constants." + description " + Period is busclock/16/100." + flavor none + + cdl_option CYGNUM_HAL_RTC_NUMERATOR { + display "Real-time clock numerator" + flavor data + default_value 1000000000 + } + cdl_option CYGNUM_HAL_RTC_DENOMINATOR { + display "Real-time clock denominator" + flavor data + default_value 100 + } + cdl_option CYGNUM_HAL_RTC_PERIOD { + display "Real-time clock period" + flavor data + default_value { (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/CYGNUM_HAL_RTC_DENOMINATOR) } + } + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + parent CYGPKG_NONE + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "powerpc-eabi" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=505 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -mmultiple -fno-rtti -fno-exceptions -finit-priority" } + description " + This option controls the global compiler flags which + are used to compile all packages by + default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-mcpu=505 -g -nostdlib -Wl,--gc-sections -Wl,-static" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) -O binary $< $@ + } + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "powerpc_pati_ram" : \ + "powerpc_pati_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_pati_ram.ldi>" : \ + "<pkgconf/mlt_powerpc_pati_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_powerpc_pati_ram.h>" : \ + "<pkgconf/mlt_powerpc_pati_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/hal_diag.h @@ -0,0 +1,89 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) + +#include <cyg/hal/hal_if.h> + +#define HAL_DIAG_INIT() hal_if_diag_init() +#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) +#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) + +#else // everything by steam + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/pkgconf/mlt_powerpc_pati_ram.h @@ -0,0 +1,54 @@ +// eCos memory layout - Fri Oct 20 10:25:48 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + +#define CYGMEM_REGION_rom (0x000000) +#define CYGMEM_REGION_rom_SIZE (0x06ffff) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_RO) + +#define CYGMEM_REGION_ram (0x400000) +#define CYGMEM_REGION_ram_SIZE (0xffffff) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_iram (0x3f9800) +#define CYGMEM_REGION_iram_SIZE (0x006800) +#define CYGMEM_REGION_iram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_eflash (0xFFC00000) +#define CYGMEM_REGION_eflash_SIZE (0x3fffff) +#define CYGMEM_REGION_eflash_ATTR (CYGMEM_REGION_ATTR_RO) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x2000) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_for_rom) []; +#endif +#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom)) +#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x10000) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((size_t)CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1) - (size_t)(0x88c0))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/pkgconf/mlt_powerpc_pati_ram.ldi @@ -0,0 +1,40 @@ + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + rom : ORIGIN = 0x00000000, LENGTH = 0x0006ffff /* internal flash */ + ram(WA) : ORIGIN = 0x00400000, LENGTH = 0x00ffffff /* external RAM */ + iram(WA) : ORIGIN = 0x003f9800, LENGTH = 0x00006800 /* internal RAM */ + eflash(RXIW) : ORIGIN = 0xFFC00000, LENGTH = 0x003fffff /* external FLASH */ +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_vectors) = 0x00000000; + + . = 0x3f9800; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); + . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); + . = 0x00400000; + + CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); + . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x10000; + + SECTION_vectors (ram, 0x00410000, LMA_EQ_VMA) + + SECTION_vectors (ram, 0x00410000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/pkgconf/mlt_powerpc_pati_rom.h @@ -0,0 +1,48 @@ +// eCos memory layout - Fri Oct 20 10:25:48 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> +#endif + +#define CYGMEM_REGION_rom (0x000000) +#define CYGMEM_REGION_rom_SIZE (0x06ffff) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_RO) + +#define CYGMEM_REGION_ram (0x400000) +#define CYGMEM_REGION_ram_SIZE (0xffffff) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_iram (0x3f9800) +#define CYGMEM_REGION_iram_SIZE (0x006800) +#define CYGMEM_REGION_iram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_eflash (0xFFC00000) +#define CYGMEM_REGION_eflash_SIZE (0x3fffff) +#define CYGMEM_REGION_eflash_ATTR (CYGMEM_REGION_ATTR_RO) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vectors) []; +#endif +#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors)) +#define CYGMEM_SECTION_reserved_vectors_SIZE (0x2000) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_vsr_table) []; +#endif +#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table)) +#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x200) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__reserved_virtual_table) []; +#endif +#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table)) +#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100) + +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE ((size_t)CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/pkgconf/mlt_powerpc_pati_rom.ldi @@ -0,0 +1,41 @@ + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + rom : ORIGIN = 0x00000000, LENGTH = 0x0006ffff /* internal flash */ + ram(WA) : ORIGIN = 0x00400000, LENGTH = 0x00ffffff /* external RAM */ + iram(WA) : ORIGIN = 0x003f9800, LENGTH = 0x00006800 /* internal RAM */ + eflash(RXIW) : ORIGIN = 0xFFC00000, LENGTH = 0x003fffff /* external FLASH */ +} + +SECTIONS +{ + SECTIONS_BEGIN + CYG_LABEL_DEFN(__reserved_vectors) = 0x00000000; + + SECTION_vectors (rom, 0x00000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + + . = 0x3f9800; + CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); + . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x200; + CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); + . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100; + + SECTION_data (iram, ALIGN (0x10), FOLLOWING (.gcc_except_table)) + SECTION_sbss (iram, ALIGN (0x4), LMA_EQ_VMA) + + . = 0x400000; + + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + + CYG_LABEL_DEFN(__heap1) = ALIGN(0x8); + + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/plf_cache.h @@ -0,0 +1,64 @@ +#ifndef CYGONCE_PLF_CACHE_H +#define CYGONCE_PLF_CACHE_H + +//============================================================================= +// +// plf_cache.h +// +// Platform HAL cache details +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: Platform cache control API +// Description: The macros defined here provide the platform specific +// cache control operations / behavior. +// Usage: Is included via the architecture cache header: +// #include <cyg/hal/hal_cache.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//--------------------------------------------------------------------------- +// Initial cache enabling +// MPC555 does not have any cache, disable caches completely +#undef CYGPRI_INIT_CACHES +#undef CYGPRI_ENABLE_CACHES + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_PLF_CACHE_H +// End of plf_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/plf_intr.h @@ -0,0 +1,68 @@ +#ifndef CYGONCE_HAL_PLF_INTR_H +#define CYGONCE_HAL_PLF_INTR_H + +//========================================================================== +// +// plf_intr.h +// +// pati platform specific interrupt definitions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: Define platform specific interrupt support +// +// Usage: +// #include <cyg/hal/plf_intr.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== +#include <cyg/hal/plf_stub.h> + +//---------------------------------------------------------------------------- +// Reset. + +#ifndef CYGHWR_HAL_RESET_DEFINED +#define CYGHWR_HAL_RESET_DEFINED +#define HAL_PLATFORM_RESET() cyg_hal_plf_reset() +#define HAL_PLATFORM_RESET_ENTRY 0x00000100 +#endif // CYGHWR_HAL_RESET_DEFINED +//-------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_PLF_INTR_H +// End of plf_intr.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/plf_misc.h @@ -0,0 +1,69 @@ +#ifndef CYGONCE_PLF_MISC_H +#define CYGONCE_PLF_MISC_H + +//========================================================================== +// +// plf_misc.h +// +// HAL platform miscellaneous functions +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Contributors: Steven Clugston +// Date: 2008-05-08 +// Purpose: HAL miscellaneous functions +// Description: This file contains miscellaneous defines provided by the +// HAL. +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ +#define CYGHWR_CFG_SDRAM_BASE (0x00400000) // (CS2) +#define CYGHWR_PCI_EPLD_BASE_ADDRESS (0x02800000) // (CS3) +#define CYGPLF_REG_PLD_REGISTER_BASE (CYGHWR_PCI_EPLD_BASE_ADDRESS + 0x1000) + +#define CYGPLF_REG_PLD_PART_ID (CYGPLF_REG_PLD_REGISTER_BASE + 0x00) +#define CYGPLF_REG_PLD_BOARD_TIMING (CYGPLF_REG_PLD_REGISTER_BASE + 0x04) +#define CYGPLF_REG_PLD_HW_CONFIG (CYGPLF_REG_PLD_REGISTER_BASE + 0x08) +#define CYGPLF_REG_PLD_MISC_CONFIG (CYGPLF_REG_PLD_REGISTER_BASE + 0x0C) +#define CYGPLF_REG_PLD_RESET (CYGPLF_REG_PLD_REGISTER_BASE + 0x10) + +#define CYGPLF_REG_PLD_MISC_CPU_VPP (0x00000008) +#define CYGPLF_REG_PLD_MISC_EXT_VPP (0x00000004) +#define CYGPLF_REG_PLD_MISC_EXT_WP (0x00000002) + +/*------------------------------------------------------------------------*/ +/* End of plf_misc.h */ +#endif //CYGONCE_PLF_MISC_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/include/plf_stub.h @@ -0,0 +1,90 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: Platform HAL stub support for PowerPC/PATI boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_powerpc_pati.h> + +#ifdef CYGPKG_IO_SERIAL +#include <pkgconf/io_serial.h> +#endif + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC + +#include <cyg/hal/ppc_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define some platform specific communication details. This is mostly +// handled by hal_if now, but we need to make sure the comms tables are +// properly initialized. + +externC void cyg_hal_plf_comms_init(void); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +//---------------------------------------------------------------------------- +// Stub initializer. +//---------------------------------------------------------------------------- +// Stub initializer. +extern void hal_plf_stub_init( void ); +#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init(); + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +externC void cyg_hal_plf_reset( void ); +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/misc/redboot_RAM.ecm @@ -0,0 +1,325 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware pati ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC5xx current ; + package -hardware CYGPKG_HAL_POWERPC_PATI current ; + package -hardware CYGPKG_DEVS_FLASH_PATI current ; + package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_REDBOOT current ; + package CYGPKG_LIBC current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_ERROR current ; + package CYGPKG_IO_FILEIO current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_LINUX_COMPAT current ; + package CYGPKG_IO current ; + package CYGPKG_FS_JFFS2 current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGBLD_GLOBAL_CFLAGS { + user_value "-mcpu=505 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -mmultiple -fno-rtti -fno-exceptions -finit-priority" +}; + +cdl_option CYGBLD_GLOBAL_LDFLAGS { + user_value "-mcpu=505 -g -nostdlib -Wl,--gc-sections -Wl,-static" +}; + +cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT { + user_value 0 +}; + +cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN { + user_value 0 +}; + +cdl_option CYGSEM_HAL_DIAG_MANGLER { + user_value GDB +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 16384 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + user_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + user_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + user_value 0 +}; + +cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CLAIM_COMMS { + user_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 0 +}; + +cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_POWERPC_FRAME_WALLS { + user_value 0 +}; + +cdl_component CYGPKG_HAL_POWERPC_MPC555 { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_POWERPC_FPU { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT { + user_value 0 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE { + user_value 0 +}; + +cdl_option CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP { + user_value 0 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER { + user_value 0 +}; + +cdl_option CYGBLD_BUILD_VERSION_TOOL { + user_value 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + user_value 1 +}; + +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + user_value 57600 +}; + +cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY { + user_value 1 +}; + +cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET { + user_value 1 +}; + +cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS { + user_value 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "MPL - PATI" +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE { + user_value 1 +}; + + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { + user_value 0 +}; + +cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE { + inferred_value 1 +}; + +cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 { + user_value 0 +}; + +cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 { + user_value 1 +}; + +cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 { + user_value "\"filesystem\"" +}; + +cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO { + inferred_value 0 +}; + +cdl_component CYGPKG_IO_FILEIO_INODE { + inferred_value 1 +}; + +cdl_option CYGOPT_FS_JFFS2_WRITE { + user_value 0 +}; + +cdl_option CYGIMP_LIBC_STRING_INLINES { + user_value 1 +}; + +cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { + user_value 1 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGBLD_ISO_CTYPE_HEADER { + user_value 0 0 +}; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + user_value 1 <cyg/error/codes.h> +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + user_value 1 <cyg/error/errno.h> +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + user_value 1 <cyg/libc/stdlib/atox.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER { + user_value 0 0 +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + user_value 1 <cyg/libc/stdlib/abs.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + user_value 1 <cyg/libc/stdlib/div.inl> +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + user_value 1 <cyg/error/strerror.h> +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_INTEL_28F320C3 { + user_value 1 +}; +cdl_component CYGPKG_REDBOOT_NETWORKING { + inferred_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM { + inferred_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + inferred_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + inferred_value 0 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/misc/redboot_ROM.ecm @@ -0,0 +1,315 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware pati ; + template redboot ; + package -hardware CYGPKG_HAL_POWERPC current ; + package -hardware CYGPKG_HAL_POWERPC_MPC5xx current ; + package -hardware CYGPKG_HAL_POWERPC_PATI current ; + package -hardware CYGPKG_DEVS_FLASH_PATI current ; + package -hardware CYGPKG_DEVS_FLASH_INTEL_28FXXX current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_REDBOOT current ; + package CYGPKG_LIBC current ; + package CYGPKG_LIBC_STRING current ; + package CYGPKG_ISOINFRA current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_ERROR current ; + package CYGPKG_IO_FILEIO current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_LINUX_COMPAT current ; + package CYGPKG_IO current ; + package CYGPKG_FS_JFFS2 current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_option CYGBLD_GLOBAL_CFLAGS { + user_value "-mcpu=505 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -mmultiple -fno-rtti -fno-exceptions -finit-priority" +}; + +cdl_option CYGBLD_GLOBAL_LDFLAGS { + user_value "-mcpu=505 -g -nostdlib -Wl,--gc-sections -Wl,-static" +}; + +cdl_option CYGBLD_BUILD_COMMON_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_HAL_COMMON_KERNEL_SUPPORT { + user_value 0 +}; + +cdl_component CYGDBG_HAL_DIAG_TO_DEBUG_CHAN { + user_value 0 +}; + +cdl_option CYGSEM_HAL_DIAG_MANGLER { + user_value GDB +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP { + user_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + user_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { + user_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_COPY_VECTORS { + user_value 0 +}; + +cdl_option CYGDBG_HAL_POWERPC_FRAME_WALLS { + user_value 0 +}; + +cdl_component CYGPKG_HAL_POWERPC_MPC555 { + inferred_value 1 +}; + +cdl_option CYGHWR_HAL_POWERPC_FPU { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT { + user_value 0 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE { + user_value 0 +}; + +cdl_option CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE { + user_value 1 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP { + user_value 0 +}; + +cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER { + user_value 0 +}; + +cdl_option CYGBLD_BUILD_VERSION_TOOL { + user_value 0 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + user_value 1 +}; + +cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + user_value 57600 +}; + +cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMCPY { + user_value 1 +}; + +cdl_option CYGIMP_INFRA_PREFER_SMALL_TO_FAST_MEMSET { + user_value 1 +}; + +cdl_option CYGFUN_INFRA_EMPTY_DELETE_FUNCTIONS { + user_value 0 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "MPL - PATI" +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_THREADS { + user_value 0 +}; + +cdl_option CYGSEM_REDBOOT_VARIABLE_BAUD_RATE { + user_value 1 +}; + + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + user_value 0 +}; + +cdl_option CYGOPT_REDBOOT_FIS_REDBOOT { + user_value 0 +}; + +cdl_component CYGOPT_REDBOOT_FIS_REDBOOT_POST { + user_value 0 +}; + +cdl_option CYGNUM_REDBOOT_FLASH_CONFIG_BLOCK { + user_value 1 +}; + +cdl_option CYGOPT_REDBOOT_FIS { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_component CYGPKG_IO_FLASH_BLOCK_DEVICE { + inferred_value 1 +}; + +cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_STATIC_1 { + user_value 0 +}; + +cdl_component CYGNUM_IO_FLASH_BLOCK_CFG_FIS_1 { + user_value 1 +}; + +cdl_component CYGDAT_IO_FLASH_BLOCK_FIS_NAME_1 { + user_value "\"filesystem\"" +}; + +cdl_option CYGSEM_ERROR_PER_THREAD_ERRNO { + inferred_value 0 +}; + +cdl_component CYGPKG_IO_FILEIO_INODE { + inferred_value 1 +}; + +cdl_option CYGOPT_FS_JFFS2_WRITE { + user_value 0 +}; + +cdl_option CYGIMP_LIBC_STRING_INLINES { + user_value 1 +}; + +cdl_option CYGIMP_LIBC_STRING_PREFER_SMALL_TO_FAST { + user_value 1 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGBLD_ISO_CTYPE_HEADER { + user_value 0 0 +}; + +cdl_option CYGBLD_ISO_ERRNO_CODES_HEADER { + user_value 1 <cyg/error/codes.h> +}; + +cdl_option CYGBLD_ISO_ERRNO_HEADER { + user_value 1 <cyg/error/errno.h> +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + user_value 1 <cyg/libc/stdlib/atox.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_FLOAT_HEADER { + user_value 0 0 +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + user_value 1 <cyg/libc/stdlib/abs.inl> +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + user_value 1 <cyg/libc/stdlib/div.inl> +}; + +cdl_option CYGBLD_ISO_STRERROR_HEADER { + user_value 1 <cyg/error/strerror.h> +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + user_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_INTEL_28F320C3 { + user_value 1 +}; +cdl_component CYGPKG_REDBOOT_NETWORKING { + inferred_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_XYZMODEM { + inferred_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + inferred_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_CACHES { + inferred_value 0 +}; + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/src/hal_diag.c @@ -0,0 +1,614 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_diag.h> // our header. + +#include <cyg/infra/cyg_type.h> // base types, externC +#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_intr.h> // Interrupt macros + +#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP +#include <cyg/hal/hal_if.h> // Calling-if API + + +static void cyg_hal_plf_serial_init(void); + +void +cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) + return; + + initialized = 1; + + cyg_hal_plf_serial_init(); +} + +//============================================================================= +// Serial driver +//============================================================================= + +//----------------------------------------------------------------------------- +// There are two serial ports. +#define CYG_DEV_SERIAL_BASE_A 0x305008 // SCI1 +#define CYG_DEV_SERIAL_BASE_B 0x305020 // SCI2 + +//----------------------------------------------------------------------------- +// Define CYG_DEVICE_SERIAL_RS232_SCIBR +// These values are calculated for a 40Mhz clock frequency +#define CYG_DEV_SERIAL_RS232_SCxBR_300 4167 +#define CYG_DEV_SERIAL_RS232_SCxBR_600 2083 +#define CYG_DEV_SERIAL_RS232_SCxBR_1200 1042 +#define CYG_DEV_SERIAL_RS232_SCxBR_2400 521 +#define CYG_DEV_SERIAL_RS232_SCxBR_4800 260 +#define CYG_DEV_SERIAL_RS232_SCxBR_9600 130 +#define CYG_DEV_SERIAL_RS232_SCxBR_14400 87 +#define CYG_DEV_SERIAL_RS232_SCxBR_19200 65 +#define CYG_DEV_SERIAL_RS232_SCxBR_28800 43 +#define CYG_DEV_SERIAL_RS232_SCxBR_38400 33 +#define CYG_DEV_SERIAL_RS232_SCxBR_57600 22 +#define CYG_DEV_SERIAL_RS232_SCxBR_115200 11 + +//----------------------------------------------------------------------------- +// Define the serial registers. +#define CYG_DEV_SERIAL_RS232_SCCR0 0x00 +#define CYG_DEV_SERIAL_RS232_SCCR1 0x01 +#define CYG_DEV_SERIAL_RS232_SCSR 0x02 +#define CYG_DEV_SERIAL_RS232_SCDR 0x03 + +#define SCCR0_OTHR 0x8000 // Select baud rate other than system clock +#define SCCR0_LINKBD 0x4000 // Link baud +#define SCCR0_SCxBR 0x1fff // SCI baud rate + +#define SCCR1_LOOPS 0x4000 // Loop mode +#define SCCR1_WOMS 0x2000 // Wired or for SCI pins +#define SCCR1_ILT 0x1000 // Idle line detect type +#define SCCR1_PT 0x0800 // Parity type (0 = Odd, 1 = Even) +#define SCCR1_PE 0x0400 // Parity enable +#define SCCR1_M 0x0200 // Mode select (0 = 10 bit frame, 1 = 11 bit frame) +#define SCCR1_WAKE 0x0100 // Wakeup by address mark +#define SCCR1_TIE 0x0080 // Transmit interrupt enable +#define SCCR1_TCIE 0x0040 // Transmit complete interrupt enable +#define SCCR1_RIE 0x0020 // Receiver interrupt enable +#define SCCR1_ILIE 0x0010 // Idle line interrupt enable +#define SCCR1_TE 0x0008 // Transmiter enable +#define SCCR1_RE 0x0004 // Receiver enable +#define SCCR1_RWU 0x0002 // Receiver wakeup +#define SCCR1_SBK 0x0001 // Send break + +#define SCSR_TDRE 0x0100 // Transmit data register empty +#define SCSR_TC 0x0080 // Transmit complete +#define SCSR_RDRF 0x0040 // Receive data register full +#define SCSR_RAF 0x0020 // Receive active flag +#define SCSR_IDLE 0x0010 // Idle line detected +#define SCSR_OR 0x0008 // Overrun error +#define SCSR_NF 0x0004 // Noise error flag +#define SCSR_FE 0x0002 // Framing error +#define SCSR_PF 0x0001 // Parity error + +//----------------------------------------------------------------------------- +typedef struct { + cyg_uint16* base; + cyg_int32 msec_timeout; + int siu_vector; + int imb3_vector; + unsigned int level; + int baud_rate; +} channel_data_t; + +//----------------------------------------------------------------------------- +static void +init_serial_channel(const channel_data_t* __ch_data) +{ + cyg_uint16 * base = __ch_data->base; + cyg_uint16 br; + + switch(__ch_data->baud_rate) + { + case 300: + br = CYG_DEV_SERIAL_RS232_SCxBR_300; + break; + case 600: + br = CYG_DEV_SERIAL_RS232_SCxBR_600; + break; + case 1200: + br = CYG_DEV_SERIAL_RS232_SCxBR_1200; + break; + case 2400: + br = CYG_DEV_SERIAL_RS232_SCxBR_2400; + break; + case 4800: + br = CYG_DEV_SERIAL_RS232_SCxBR_4800; + break; + case 9600: + br = CYG_DEV_SERIAL_RS232_SCxBR_9600; + break; + case 14400: + br = CYG_DEV_SERIAL_RS232_SCxBR_14400; + break; + case 19200: + br = CYG_DEV_SERIAL_RS232_SCxBR_19200; + break; + case 28800: + br = CYG_DEV_SERIAL_RS232_SCxBR_28800; + break; + case 38400: + br = CYG_DEV_SERIAL_RS232_SCxBR_38400; + break; + case 57600: + br = CYG_DEV_SERIAL_RS232_SCxBR_57600; + break; + case 115200: + br = CYG_DEV_SERIAL_RS232_SCxBR_115200; + break; + default: + // Use the default if something unknown is requested + br = CYG_DEV_SERIAL_RS232_SCxBR_38400; + break; + } + + // 8-1-No parity + HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, (SCCR1_TE | SCCR1_RE)); + + // Set baud rate + HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR0, br); +} + +static cyg_bool +cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) +{ + cyg_uint16 status; + cyg_uint16 result; + cyg_uint16 * base = ((channel_data_t *)__ch_data)->base; + + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status); + if((status & SCSR_RDRF) == 0) + return false; + + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, result); + *ch = (cyg_uint8)(result & 0x00ff); + + return true; +} + + +cyg_uint8 +cyg_hal_plf_serial_getc(void* __ch_data) +{ + cyg_uint8 ch; + CYGARC_HAL_SAVE_GP(); + + while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); + + CYGARC_HAL_RESTORE_GP(); + return ch; +} + +void +cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c) +{ + cyg_uint16 status; + cyg_uint16 * base = ((channel_data_t *)__ch_data)->base; + + CYGARC_HAL_SAVE_GP(); + + do { + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status); + } while((status & SCSR_TDRE) == 0); + + HAL_WRITE_UINT16(base+CYG_DEV_SERIAL_RS232_SCDR, (short)c); + + // Hang around until the character is safely sent + do { + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status); + } while((status & SCSR_TDRE) == 0); + + CYGARC_HAL_RESTORE_GP(); +} + +// Channel data +// Do NOT make them const, will cause problems when trying +// to change the timeout parameter ... (Is this a bug in other) +// PowerPC platform hals ?? You only see it when you really start from +// flash .... +static channel_data_t channels[2] = { + { (cyg_uint16*)CYG_DEV_SERIAL_BASE_A, + 1000, + CYGNUM_HAL_INTERRUPT_SIU_LVL0, + CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX, + 0, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD }, + { (cyg_uint16*)CYG_DEV_SERIAL_BASE_B, + 1000, + CYGNUM_HAL_INTERRUPT_SIU_LVL0, + CYGNUM_HAL_INTERRUPT_IMB3_SCI2_RX, + 0, + CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD } +}; + +static void +cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, + cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + cyg_hal_plf_serial_putc(__ch_data, *__buf++); + + CYGARC_HAL_RESTORE_GP(); +} + +static void +cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) +{ + CYGARC_HAL_SAVE_GP(); + + while(__len-- > 0) + *__buf++ = cyg_hal_plf_serial_getc(__ch_data); + + CYGARC_HAL_RESTORE_GP(); +} + +cyg_bool +cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) +{ + int delay_count; + channel_data_t* chan = (channel_data_t*)__ch_data; + cyg_bool res; + CYGARC_HAL_SAVE_GP(); + + delay_count = chan->msec_timeout * 10; // delay in .1 ms steps + for(;;) { + res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); + if (res || 0 == delay_count--) + break; + + CYGACC_CALL_IF_DELAY_US(100); + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static int +cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) +{ + static int irq_state = 0; + channel_data_t* chan = (channel_data_t*)__ch_data; + + int ret = 0; + CYGARC_HAL_SAVE_GP(); + + switch (__func) { + case __COMMCTL_GETBAUD: + ret = chan->baud_rate; + break; + case __COMMCTL_SETBAUD: + { + va_list ap; + va_start(ap, __func); + + ret = chan->baud_rate; + chan->baud_rate = va_arg(ap, cyg_int32); + init_serial_channel(chan); + + va_end(ap); + } + break; + case __COMMCTL_IRQ_ENABLE: + HAL_INTERRUPT_SET_LEVEL(chan->imb3_vector, chan->level); + HAL_INTERRUPT_UNMASK(chan->imb3_vector); + HAL_INTERRUPT_UNMASK(chan->siu_vector); + irq_state = 1; + break; + case __COMMCTL_IRQ_DISABLE: + ret = irq_state; + irq_state = 0; + HAL_INTERRUPT_MASK(chan->imb3_vector); + HAL_INTERRUPT_MASK(chan->siu_vector); + break; + case __COMMCTL_DBG_ISR_VECTOR: + ret = chan->siu_vector; + break; + case __COMMCTL_SET_TIMEOUT: + { + va_list ap; + va_start(ap, __func); + + ret = chan->msec_timeout; + chan->msec_timeout = va_arg(ap, cyg_uint32); + + va_end(ap); + } + break; + default: + break; + } + CYGARC_HAL_RESTORE_GP(); + return ret; +} + +static int +cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, + CYG_ADDRWORD __vector, CYG_ADDRWORD __data) +{ + int res = 0; + + cyg_uint16 status; + cyg_uint16 control; + + cyg_uint16 * base = ((channel_data_t *)__ch_data)->base; + + CYGARC_HAL_SAVE_GP(); + + *__ctrlc = 0; + + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCSR, status); + HAL_READ_UINT16(base+CYG_DEV_SERIAL_RS232_SCCR1, control); + + if((status & SCSR_RDRF) && (control & SCCR1_RIE)) + { // Only if the interrupt was caused by the channel + cyg_uint8 c; + c = cyg_hal_plf_serial_getc(__ch_data); + + if(cyg_hal_is_break(&c, 1)) + *__ctrlc = 1; + + HAL_INTERRUPT_ACKNOWLEDGE(((channel_data_t *)__ch_data)->imb3_vector); + res = CYG_ISR_HANDLED; + } + + CYGARC_HAL_RESTORE_GP(); + return res; +} + +static void +cyg_hal_plf_serial_init(void) +{ + hal_virtual_comm_table_t* comm; + int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + + // Disable interrupts. + HAL_INTERRUPT_MASK(channels[0].imb3_vector); + HAL_INTERRUPT_MASK(channels[1].imb3_vector); + + // Init channels + init_serial_channel(&channels[0]); + init_serial_channel(&channels[1]); + + // Setup procs in the vector table + + // Set channel 0 + CYGACC_CALL_IF_SET_CONSOLE_COMM(0); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Set channel 1 + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); + comm = CYGACC_CALL_IF_CONSOLE_PROCS(); + CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]); + CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); + CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); + CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); + CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); + CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); + CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); + CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); + + // Restore original console + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); +} + +//============================================================================= +// Compatibility with older stubs +//============================================================================= +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION +#endif + +//----------------------------------------------------------------------------- +// Assumption: all diagnostic output must be GDB packetized unless +// this is a configuration for a stand-alone ROM system. +#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGSEM_HAL_ROM_MONITOR) +# define HAL_DIAG_USES_HARDWARE +#endif + +#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0) +# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_A) +#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1) +# define __BASE ((cyg_uint16*)CYG_DEV_SERIAL_BASE_B) +#else +# error "Invalid console channel selection" +#endif + +static channel_data_t channel = { __BASE, 0, 0 }; + +#ifdef HAL_DIAG_USES_HARDWARE + +void hal_diag_init(void) +{ + init_serial_channel(&channel); +} + +void hal_diag_write_char(char __c) +{ + cyg_hal_plf_serial_putc(&channel, __c); +} + +void hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(&channel); +} + +#else // ifdef HAL_DIAG_USES_HARDWARE + +// Initialize diag port +void +hal_diag_init(void) +{ + // Init devices + init_serial_channel(&channel); +} + +void +hal_diag_write_char_serial( char c ) +{ + unsigned long __state; + HAL_DISABLE_INTERRUPTS(__state); + cyg_hal_plf_serial_putc(&channel, c); + HAL_RESTORE_INTERRUPTS(__state); +} + +void +hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_serial_getc(&channel); +} + +void +hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while(1) + { + char c1; + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. + hal_diag_read_char(&c1); + + if( c1 == '+' ) + break; // a good acknowledge + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + if( 3 == c1 ) { + // Ctrl-C: breakpoint. + cyg_hal_gdb_interrupt( + (target_register_t)__builtin_return_address(0)); + break; + } +#endif + // otherwise, loop round again + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + + } +} + +#endif // ifdef HAL_DIAG_USES_HARDWARE + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +//----------------------------------------------------------------------------- +// End of hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/src/pati.S @@ -0,0 +1,254 @@ +##============================================================================= +## +## pati.S +## +## PATI board hardware setup +## +##============================================================================= +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 2008 Free Software Foundation, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): Steven Clugston +## Original: Bob Koninckx +## Date: 2008-05-08 +## Purpose: pati board hardware setup +## Description: This file contains any code needed to initialize the +## hardware on a PATI MPC555 board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/arch.inc> +#include <cyg/hal/plf_misc.h> + +#define PATI_CS0_FLASH_BASE_ADDRESS (0xFFC00000) +#define PATI_CS1_SDRAM_BASE_ADDRESS (0x00400000) +#define PATI_CS2_PCI_MASTER_BASE_ADDRESS (0x01800000) +#define PATI_CS3_EPLD_CONFIG_BASE_ADDRESS (0x02800000) + +#define PATI_REG_PLD_BOARD_TIMING (0x04) + +#------------------------------------------------------------------------------ + + .globl hal_hardware_init +hal_hardware_init: +#if defined(CYGPKG_HAL_POWERPC_PATI) && defined(CYGPKG_HAL_POWERPC_MPC5xx) + lwi r3, CYGARC_REG_IMM_BASE + + // Disable the Watchdog (for now) + lwi r4, 0xffffff88 + stw r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3) + // Configure SIUMCR for LEDs + lwi r4, 0x80020C00 + stw r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3) + + // Unlock locked registers + lwi r4, 0x55ccaa33 + stw r4, (CYGARC_REG_IMM_TBSCRK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_TBREF0K-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_TBREF1K-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_TBK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_RTCK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_RTSECK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_RTCALK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_PISCRK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_PITCK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_SCCRK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_PLPRCRK-CYGARC_REG_IMM_BASE)(r3) + stw r4, (CYGARC_REG_IMM_RSRK-CYGARC_REG_IMM_BASE)(r3) + + // Boost the clock to 40MHz + lwi r4, 0x03000000 + stw r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3) + lwi r4, 0x00910000 + stw r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3) + lwi r4, 0x0080 + sth r4, (CYGARC_REG_IMM_COLIR-CYGARC_REG_IMM_BASE)(r3) + + // Set up the memory map + // Do NOT write protect the flash memory, flash drivers won't work + // if we do + + // CS0, External flash, 4MByte, 16-bit port, Burst inhibit + lwi r4, (PATI_CS0_FLASH_BASE_ADDRESS | 0x00000807) + stw r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3) + // 2 wait state, asynchronous operation 40 Mhz clock, 70 ns + lwi r4, 0xFFC00000 + stw r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3) + + // CS1, SDRAM, 32-bit port, 16MByte, Burst inhibit + lwi r4, (PATI_CS1_SDRAM_BASE_ADDRESS | 0x00000007) + stw r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3) + // 1 wait state, asynchronous operation + lwi r4, 0xFF000000 + stw r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3) + + // CS2, PCI Master area, 32-bit port, 16Mbyte, Burst inhibit + lwi r4, (PATI_CS2_PCI_MASTER_BASE_ADDRESS | 0x00000007) + stw r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3) + // 1 wait state, cycle length, asynchronous operation + lwi r4, 0xFF000000 + stw r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3) + + // CS3, PCI Bridge Configuration Area / EPLD Config Address, + // 32-bit port, 4KByte / 32 Kbyte, Burst Inhibit + lwi r4, (PATI_CS3_EPLD_CONFIG_BASE_ADDRESS | 0x00000007) + stw r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3) + // 1 wait state, cycle length, asynchronous operation + lwi r4, 0xFFFF0000 + stw r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3) + +#if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP) + lwi r4, 1 +#else + lwi r4, 0 +#endif + stw r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3) + lwi r4, 0 + stw r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3) + + // Enable the time base and set the freeze flag + lwi r4, 0xc3 + sth r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3) + + // RTC is clocked by 4MHz crystal, set the freeze flag + lwi r4, 0xd2 + sth r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3) + + // Set the freeze flag for the Periodic interrupt timer + lwi r4, 0x82 + sth r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3) + + // USIU rest. + // Set outputs in data direction register + lwi r4, 0x27000000 + lwi r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE) + stwx r4, r3, r5 + lwi r4, 0x00000000 + lwi r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE) + stwx r4, r3, r5 + // Set GPIOs, set IRQ and USERi to 1, LEDs off + lwi r4, 0x28000000 + lwi r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE) + stwx r4, r3, r5 + lwi r4, 0x00000ac6 + lwi r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE) + stwx r4, r3, r5 + + // Dual ported TPU RAM + lwi r4, 0x0000 + lwi r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + + lwi r4, 0xffa0 + lwi r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + + lwi r4, 0x00 + lwi r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + + lwi r4, 0x00 + lwi r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + lwi r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + lwi r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + lwi r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE) + sthx r4, r3, r5 + + // Enable 32 interrupt priorities on the IMB3 unit + lwi r4, 0x60000000 + lwi r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE) + stwx r4, r3, r5 +// section BSS may not fit into iram so the SDRAM has to be setup here +// so it can be safely used instead by early startup code +#ifdef CYG_HAL_STARTUP_ROM + // Setup SDRAM + // Load SDRAM Controller register contents + // Mask SDRAM_CAL, SDRAM_RCD, SDRAM_WREQ, SDRAM_PR, SDRAM_RC, + // SDRAM_LMR, and SDRAM_IIP bits + lwi r3,CYGPLF_REG_PLD_REGISTER_BASE + lwz r6,(PATI_REG_PLD_BOARD_TIMING)(r3) + lwi r4,0xff81efff + and r4,r4,r6 + // Set CAL bit + lwi r6,0x00400000 + or r4,r4,r6 + stw r4, (PATI_REG_PLD_BOARD_TIMING)(r3) +// Set IIP Precharge bit + lwi r6,0x00001000 + or r4,r4,r6 + stw r4, (PATI_REG_PLD_BOARD_TIMING)(r3) +// wait for IIP bit to clear + li r5, 0x7fff +precharge_loop: + eieio + lwz r6,(PATI_REG_PLD_BOARD_TIMING)(r3) + lwi r4,0x00001000 + or r6,r6,r4 + cmpwi r6, 0 + beq wait_refresh + subi r5, r5, 1 + cmpwi r5, 0 + bgt precharge_loop +wait_refresh: +// wait for about 200us + li r5, 0x0a8c +wait_refresh_loop: + subi r5, r5, 1 + cmpwi r5, 0 + bgt wait_refresh_loop +// Set LMR load mode register bit + lwi r4,0x00020000 + or r6,r6,r4 + stw r6,(PATI_REG_PLD_BOARD_TIMING)(r3) + eieio +// Calc LMR address for CAS = 3 so LMR = 0x00000032 << 2, 0x000000c8 + lwi r3,PATI_CS1_SDRAM_BASE_ADDRESS + addi r3,r3,0x00c8 +// Do a dummy read from Mode Register address, to load the value into SDRAM + lwz r6,0(r3) +// The SDRAM should now be accessible +#endif + +#endif + sync + blr +#------------------------------------------------------------------------------ +# end of pati.S
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/src/plf_misc.c @@ -0,0 +1,75 @@ +//============================================================================= +// +// plf_misc.c +// +// Platform miscellaneous code/data. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: Bob Koninckx +// Date: 2008-05-08 +// Purpose: Platform specific code and data +// Description: Tables for per-platform initialization +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <cyg/hal/hal_mem.h> // HAL memory definitions +#include <cyg/hal/hal_if.h> // hal_if_init + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_intr.h> // interrupt vectors +#include <cyg/hal/hal_misc.h> // Helper functions +#include <cyg/hal/drv_api.h> // HANDLED +#include <cyg/hal/hal_diag.h> + +// The memory map is weakly defined, allowing the application to redefine +// it if necessary. Leave the table empty, the mpc555 has no cache ... +CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = { + CYGARC_MEMDESC_TABLE_END +}; + +void +hal_platform_init(void){ + hal_if_init(); + +#if defined CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + HAL_DIAG_INIT(); +#endif +} + +// EOF plf_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/pati/current/src/plf_stub.c @@ -0,0 +1,77 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2008 Free Software Foundation, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Steven Clugston +// Original: jskov +// Date: 2008-05-08 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/hal/hal_stub.h> +#include <cyg/hal/hal_if.h> +#include <cyg/hal/plf_misc.h> +#include <cyg/hal/hal_io.h> // IO macros + +void +hal_plf_stub_init(void) +{ + +} + +/*------------------------------------------------------------------------*/ +/* Reset support */ +#define CHIPRST CYGPLF_REG_PLD_RESET +void cyg_hal_plf_reset(void) +{ + // Write to EPLD Reset Register asserts HRESET# + // which resets the processor, + // the EPLD register is not reset, only a power on reset + // will do this. + HAL_WRITE_UINT32(CHIPRST, 0xFF); + // Just in case. + while (1) ; +} + +//----------------------------------------------------------------------------- +// End of plf_stub.c