Mercurial > ecos-v3_0-branch
changeset 32:5af43b635655 ecos-sw-1999-08-18
Merge from eCos master repository on 1999-08-18-15:20:01-BST
line wrap: on
line diff
--- a/packages/ChangeLog +++ b/packages/ChangeLog @@ -4,6 +4,11 @@ 1999-08-16 Jonathan Larmour <jlarmour@ * targets: Rename all mentions of am32 to am31 +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * packages, targets: Add support for the PowerPC target MBX860 + platform and QUICC companion components. + 1999-06-09 Gary Thomas <gthomas@cygnus.co.uk> * pkgconf.tcl (pkgconf::produce_misc_files): MLT files need @@ -22,6 +27,8 @@ 1999-06-04 Gary Thomas <gthomas@cygnus 1999-06-03 Gary Thomas <gthomas@cygnus.co.uk> + * targets: Add 'base_platform' for CL7111, based on CL7211. + * pkgconf.tcl: Support 'base_platform' in target specification. This performs the inverse of what the "platform" entry in CDL options does. @@ -29,6 +36,15 @@ 1999-05-26 Jesper Skov <jskov@cygnus.c * NEWS: Added Kernel/Debugging entry. +1999-05-18 Gary Thomas <gthomas@cygnus.co.uk> + + * packages: Remove errant CL7111 package. + +1999-05-17 Gary Thomas <gthomas@cygnus.co.uk> + + * packages: + * targets: Add new platform CL7111 - substantially the same as + the CL7211 but different processor core. 1999-05-13 Nick Garnett <nickg@cygnus.co.uk> The following changes were made in a branch and imported to the @@ -78,6 +94,10 @@ 1999-04-27 Bart Veer <bartv@cygnus.co. * pkgconf.tcl: Add $(ARCHFLAGS) and $(LDARCHFLAGS) to the command line when generating extras.o from libextras.a +1999-04-19 Gary Thomas <gthomas@cygnus.co.uk> + + * targets: Add Cirrus Logic CL7211 support. + 1999-04-16 Bart Veer <bartv@cygnus.co.uk>
--- a/packages/NEWS +++ b/packages/NEWS @@ -33,6 +33,12 @@ *** The following are the new target platforms... +**** ARM: + ARM720 - Cirrus Logic CL7211 board + ARM710C - Cirrus Logic CL7111 board + +**** PowerPC + Motorola MBX PowerPC Evaluation Board ** Host side platforms
--- a/packages/devs/watchdog/current/ChangeLog +++ b/packages/devs/watchdog/current/ChangeLog @@ -1,3 +1,17 @@ +1999-08-18 Nick Garnett <nickg@cygnus.co.uk> + + * include/pkgconf/watchdog.h: Made test for use of a non-emulated + watchdog more generic for MN10300 targets. + + * src/emulate.cxx: + * include/watchdog.hxx (class Cyg_Watchdog): + Added get_resolution() to return maximum time, in nanoseconds, + between calls to reset(). + + * tests/watchdog.cxx: + Modified to use the value returned from get_resolution() to + control the timing of reset() calls. + 1999-07-14 Jesper Skov <jskov@cygnus.co.uk> * src/mn10300.cxx:
--- a/packages/devs/watchdog/current/include/pkgconf/watchdog.h +++ b/packages/devs/watchdog/current/include/pkgconf/watchdog.h @@ -73,7 +73,7 @@ #define CYGIMP_WATCHDOG_EMULATE -#if defined(CYG_HAL_MN10300_MN103002) && !defined(CYGPKG_HAL_MN10300_SIM) +#if defined(CYGPKG_HAL_MN10300) && !defined(CYGPKG_HAL_MN10300_SIM) #undef CYGIMP_WATCHDOG_EMULATE #endif
--- a/packages/devs/watchdog/current/include/watchdog.hxx +++ b/packages/devs/watchdog/current/include/watchdog.hxx @@ -48,7 +48,6 @@ #include <cyg/kernel/ktypes.h> #include <cyg/infra/cyg_ass.h> // assertion macros - class Cyg_Watchdog_Action; // ------------------------------------------------------------------------- @@ -59,10 +58,16 @@ class Cyg_Watchdog Cyg_Watchdog_Action *action_list; + cyg_uint64 resolution; + public: Cyg_Watchdog(); + // Return time interval allowed between resets before watchdog + // triggers, in nanoseconds. + cyg_uint64 get_resolution(); + // Start the watchdog running. void start();
--- a/packages/devs/watchdog/current/src/emulate.cxx +++ b/packages/devs/watchdog/current/src/emulate.cxx @@ -87,11 +87,21 @@ Cyg_Watchdog::Cyg_Watchdog() Cyg_Clock::cyg_resolution res = Cyg_Clock::real_time_clock->get_resolution(); one_sec = ( res.divisor * 1000000000LL ) / res.dividend ; + + resolution = 1000000000LL; CYG_REPORT_RETURN(); } // ------------------------------------------------------------------------- +// Return reset resolution + +cyg_uint64 Cyg_Watchdog::get_resolution() +{ + return resolution; +} + +// ------------------------------------------------------------------------- // Start the watchdog running. void Cyg_Watchdog::start()
--- a/packages/devs/watchdog/current/src/mn10300.cxx +++ b/packages/devs/watchdog/current/src/mn10300.cxx @@ -43,7 +43,7 @@ #include <pkgconf/system.h> // system configuration file #include <pkgconf/watchdog.h> // configuration for this package -#if defined(CYG_HAL_MN10300_MN103002) && !defined(CYGIMP_WATCHDOG_EMULATE) +#if defined(CYGPKG_HAL_MN10300) && !defined(CYGIMP_WATCHDOG_EMULATE) #include <pkgconf/kernel.h> // Kernel config @@ -64,6 +64,8 @@ // ------------------------------------------------------------------------- // MN10300 watchdog timer registers +#if defined(CYGPKG_HAL_MN10300_AM31) + #define WATCHDOG_BASE 0x34004000 #define WATCHDOG_COUNTER (WATCHDOG_BASE) #define WATCHDOG_CONTROL (WATCHDOG_BASE+2) @@ -74,6 +76,14 @@ #define WATCHDOG_WDRST 0x40 #define WATCHDOG_WDCNE 0x80 +#define WATCHDOG_RESOLUTION 1016801000 // cycle time in nanoseconds + +#else + +#error Unsupported MN10300 variant + +#endif + // ------------------------------------------------------------------------- // Forward definitions @@ -98,16 +108,28 @@ static Cyg_Interrupt interrupt( // ------------------------------------------------------------------------- // Constructor + Cyg_Watchdog::Cyg_Watchdog() { CYG_REPORT_FUNCTION(); action_list = 0; + resolution = WATCHDOG_RESOLUTION; + CYG_REPORT_RETURN(); } // ------------------------------------------------------------------------- +// Return reset resolution + +cyg_uint64 Cyg_Watchdog::get_resolution() +{ + return resolution; +} + + +// ------------------------------------------------------------------------- // Start the watchdog running. void @@ -243,7 +265,7 @@ watchdog_dsr(cyg_vector vector, cyg_ucou { } -#endif // defined(CYG_HAL_MN10300_MN103002) && +#endif // defined(CYGPKG_HAL_MN10300) && // !defined(CYGIMP_WATCHDOG_EMULATE) // ------------------------------------------------------------------------- // EOF watchdog/mn10300.cxx
--- a/packages/devs/watchdog/current/tests/watchdog.cxx +++ b/packages/devs/watchdog/current/tests/watchdog.cxx @@ -77,15 +77,16 @@ char thread[sizeof(Cyg_Thread)]; Cyg_Thread *th; -cyg_tick_count one_sec; +//cyg_tick_count one_sec; +cyg_tick_count watchdog_delay; volatile bool watchdog_fired; volatile cyg_tick_count watchdog_time; -#define WATCHDOG_LOOPS_HW 5 -#define WATCHDOG_LOOPS_SIM 1 -#define WATCHDOG_SECS_PER_LOOP_HW 10 -#define WATCHDOG_SECS_PER_LOOP_SIM 2 -#define WATCHDOG_SECS_TILL_TIMEOUT 10 +#define WATCHDOG_LOOPS_HW 5 +#define WATCHDOG_LOOPS_SIM 1 +#define WATCHDOG_CYCLES_PER_LOOP_HW 10 +#define WATCHDOG_CYCLES_PER_LOOP_SIM 2 +#define WATCHDOG_TICKS_TILL_TIMEOUT 10 // ------------------------------------------------------------------------- // Action functions: @@ -109,14 +110,14 @@ void watchdog_thread( CYG_ADDRWORD id ) { cyg_tick_count watchdog_start_time; cyg_tick_count thread_start_time, thread_end_time; - cyg_ucount8 watchdog_loops, watchdog_secs_per_loop; + cyg_ucount8 watchdog_loops, watchdog_cycles_per_loop; if (cyg_test_is_simulator) { watchdog_loops = WATCHDOG_LOOPS_SIM; - watchdog_secs_per_loop = WATCHDOG_SECS_PER_LOOP_SIM; + watchdog_cycles_per_loop = WATCHDOG_CYCLES_PER_LOOP_SIM; } else { watchdog_loops = WATCHDOG_LOOPS_HW; - watchdog_secs_per_loop = WATCHDOG_SECS_PER_LOOP_HW; + watchdog_cycles_per_loop = WATCHDOG_CYCLES_PER_LOOP_HW; } watchdog_fired = false; @@ -125,8 +126,8 @@ void watchdog_thread( CYG_ADDRWORD id ) CYG_TEST_INFO("Testing that watchdog does not fire early"); for (cyg_ucount8 tries = 0; tries < watchdog_loops; tries++) { - diag_printf("Iteration #%d (testing over %d seconds)\n", - tries, watchdog_secs_per_loop); + diag_printf("Iteration #%d (testing over %d cycles)\n", + tries, watchdog_cycles_per_loop); // First test that the watchdog does not trigger when being reset. Cyg_Watchdog_Action wdaction( watchdog_action1, 0 ); @@ -137,9 +138,9 @@ void watchdog_thread( CYG_ADDRWORD id ) watchdog_start_time = Cyg_Clock::real_time_clock->current_value(); watchdog_fired = false; - for( cyg_ucount8 i = 0; i < watchdog_secs_per_loop; i++ ) { + for( cyg_ucount8 i = 0; i < watchdog_cycles_per_loop; i++ ) { thread_start_time = Cyg_Clock::real_time_clock->current_value(); - th->delay( one_sec-2 ); + th->delay( watchdog_delay-2 ); Cyg_Watchdog::watchdog.reset(); if (watchdog_fired) { thread_end_time = Cyg_Clock::real_time_clock->current_value(); @@ -167,7 +168,7 @@ void watchdog_thread( CYG_ADDRWORD id ) Cyg_Watchdog::watchdog.reset(); - th->delay( one_sec*WATCHDOG_SECS_TILL_TIMEOUT ); + th->delay( watchdog_delay*WATCHDOG_TICKS_TILL_TIMEOUT ); } CYG_TEST_FAIL_FINISH("Watchdog failed to trigger"); @@ -180,17 +181,23 @@ externC void cyg_start( void ) { CYG_TEST_INIT(); - - Cyg_Clock::cyg_resolution res = Cyg_Clock::real_time_clock->get_resolution(); - + #if !defined(CYGIMP_WATCHDOG_EMULATE) && defined(CYGPKG_HAL_MN10300_STDEVAL1) // Workaround for PR 17974 if( cyg_test_is_simulator ) CYG_TEST_NA("Watchdog device not implemented in MN10300 simulator."); #endif - one_sec = ( res.divisor * 1000000000LL ) / res.dividend ; + + Cyg_Clock::cyg_resolution res = Cyg_Clock::real_time_clock->get_resolution(); + + cyg_uint64 wres = Cyg_Watchdog::watchdog.get_resolution(); + // Calculate how many clock ticks there are in a watchdog cycle. + + watchdog_delay = ((cyg_tick_count)wres * (cyg_tick_count)res.divisor ); + watchdog_delay /= res.dividend; + th = new((void *)&thread) Cyg_Thread(CYG_SCHED_DEFAULT_INFO, watchdog_thread, 0,
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/ChangeLog @@ -0,0 +1,111 @@ +1999-08-16 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/hal_arm_cl7211.h: + + Proper case various display strings. + +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/STUBS_config: Update for latest hal.h. Also add way to + specify platform (second parameter). + +1999-07-14 Hugo Tyson <hmt@cygnus.co.uk> + + * include/hal_cache.h (HAL_UCACHE_LINE_SIZE): Correct the comment + and the value: this is supposed to be in bytes. + +1999-06-22 Gary Thomas <gthomas@cygnus.co.uk> + + * src/cl7211_misc.c (hal_IRQ_handler): Remove some debug code. + Add simple handler for battery low to test FIQ support. + +1999-06-18 Gary Thomas <gthomas@cygnus.co.uk> + + * src/plf_stub.c: + * src/hal_diag.c: Use pkgconf derived platform include file. + + * src/cl7211_misc.c (hal_hardware_init): + * include/pkgconf/hal_arm_cl7211.h: Add configuration control for + CPU processor speed. Default to 73.728 MHz. + +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * include/hal_platform_setup.h (MAP_DRAM): 16M layout was wrong. + +1999-06-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/hal_diag.c: Clean up. + + * include/hal_platform_setup.h (PLATFORM_SETUP1): + Better MMU initialization for IO segments. + (PLATFORM_SETUP1): Add mappings for expansion I/O. + + * src/cl7211_misc.c (hal_hardware_init): Turn on DIAG LED. + + * include/hal_cl7211.h: Add LED flasher definitions. + +1999-06-15 Gary Thomas <gthomas@cygnus.co.uk> + + * misc/prog_flash.c: Massive rewrite/upgrade to handle Intel + parts that are on the 7211, as well as the ATMEL parts on 7111. + This program should work for either and gives a good example + of how to access/program/erase the FLASH. + + * include/hal_platform_setup.h (CYGHWR_HAL_ARM_HAS_MMU): Define. + + * misc/PKGconf.mak (gdb_module.img): + * include/pkgconf/mlt_arm_cl7211_stubs.mlt: + * include/pkgconf/mlt_arm_cl7211_stubs.ldi: Support to allow + stubs to be the startup application (GDB on board). + +1999-06-14 Gary Thomas <gthomas@cygnus.co.uk> + + * include/hal_cache.h: Turn on FLUSH macros. + +1999-06-11 Gary Thomas <gthomas@cygnus.co.uk> + + * include/hal_cache.h: Update with new unified cache support. + +1999-06-09 Gary Thomas <gthomas@cygnus.co.uk> + + * include/hal_platform_setup.h (PLATFORM_SETUP1): Remove debug code. + + * include/pkgconf/hal_arm_cl7211.h: Add new configuration options. + DRAM size (currently 2M and 16M supported). + LCD installed? + + * include/hal_platform_setup.h: Reorganize to support configuration + of DRAM size and LCD installed. + +1999-05-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_arm_cl7211.h: New configury to support + multiple versions of CLxx11. + +1999-05-20 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/hal_arm_cl7211.h: Move RTC setup here. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 index 0000000000000000000000000000000000000000..e1d220c575d4ebe724a5b6e4ed650c17d3abb911 GIT binary patch literal 15184 zc%02!3v?XSdA>8dtH*k6jUEPBR^yQ^g90*)Yym<Quvj*AFiF<7OdaAw*F_MLQcyr} zXzQG;9yY0CQ~AN8j);ap8$wCyhP376G_4#1Cs5iWKS&(vw6imsuCXamQnzsv#oO<@ zb4OaO1#vm2J>7Gz?(4tz{`dd?`#<g-)lQ7~wM9wb7nWC{Y)6Ds9~I74q_aq}zeG5_ zG2whmN83ds{@F_~&g}EgpnOJ^Cs6J)ZBLj7{Ya(ljkDddJ?Ewo-???f*VA^kvd8vH z)7!Jrbl<qP)AruDYs4=R8?#uV?q$Hl05kf~h))>p_iZnl?jJ9;2AtB=HYX}JWFtbv zwagk<h)v$V=ks-M=kurbT|MGQ%zkG`=DJgPwe9IEfk(>rw1+T9s!z_r@xQ<reYx$G zpkH5adugmsm=duq8x?@VIw9<T0k#CNl}W%R2eZ*+-*_YT5={=E+&|ug^_ozZ>k!ve z|IBr6d~Y0_s{)))T%~X>SVM2Iy<@9^7v>z>i1j#c0bW1H_`g~G-s?u*XWa<qo`=0h z*4f_HJKulr^RRc34Cd<k6|g;q?HP--cgc5Sk^b(*i^|?L7L~qh&L8oOMUi*wmyY<K zRWSO54Svr^UZw{7G<PFq{6^%B$jgwIA!mOY{Y|Jhp<au;7I_=;Hstll>ydXL??9eF zo<QD=ycxNH+(2$2w~$Y+81W}Nkv2fyL{~NjnTlGSZZx^djfxljsCZVklU^?!9r2G~ zeKGOj>;aSytMaob|C1^|iSkiZ789S&4x+xZ8fnRh#9bHbvO3oQ-B_N)yf4PZ>F<__ z(=WutX-yNS&q0po9QgV_r!Y3^e9YB0Eqhytk7qTp?CrUuq)|n7kr?%=MMkbO_kf+P z1?*h$NuG%vWf89RNuHzqbH?oKEn^>b^A)>JE)v5hJH#$u7`s4=U4GKq<+mkw`K`__ z{}!>+wGQm^b@2Fig*f%b5w&*eSFDXT8?c+z8Wja=B(X-DRWLu=Bba|9=I=dn;d|>i zGQGEE{e$l<inXuC+Gh`6_}Zg~r`JB9eektoSo>n``|yR+b<N=mr)wGJ&qHojVcoen zNAn<0oTJql_N}p}{BZs%HGcy5w>eMw9pWiJIf{PBYQEyBlk+AHWRHzqIDIaJ2HgML zAv;?Rye@{ULytgj*x4Zi>s0Q}4VuWe?8%jzcDBN?vn9|89~Ad_69JygB^{7ws)fja z_?b(=IhL8Ka2jt2(pVepnh~@$As<9?3|hLN{m#z&9xxwjxnlVhE$ybb`N4b5mTSzG zYp=Z)02xhWGPdX+MJ~kTIiVv@icyTy#1QhK43aoFFCj!8LL_kDt58ON8h_Hl5}BV? zaIBH}5Zdbqhu=QfR!Q^Y%ifM2xWzqIDo+0r{1wkFd^>DUSR;Og5U_tobA(~v<Tcad zOq24u$CrH~<!M5^{-@9}gcFwI39H{{xvNr$a7-TaZLyMWOl<Ik0X|{uZ;Ip|!2Pjh zCf&THyXEN9g}s|?H-@kR^F6ol53dn7x*?7R=A+H8fsAmT8f&dzFXs4-$+hmA`TS|F z6~!9Rho?2*N84eju{{{8K~9X+F@^s|uMFgA1Y8qx4f7h-%YGs?2-`R4>(trSpx=Nq zrU4f0u3G}w669rK(2a<plf*@{Msqs+62pAizX-4iW1p|jS?7T@bwbU_z4S;L?Ss!U z;0VlHX72Mf@!gze^|=YuOEFf*I>_s|k8fZ<LZ@60`jM%5Y&lN^a7z^2vw({R^Ja;! zFpv2Wv0mDQWq`jH{5b(WUykzCD05xiI^ws3#s+Z|NBl&3pMNF$EaG(3Z$>!=SuYW( zEb!T(8;-|5VIIvztc;_XhjI{4m;Gn+`Td&0t9ZYp`@|0ec@sT$_U_Dx-w4<m$_(s& zEct^ReKOj^Qfb3*#%QzB+d=znP6_(+sR(%0<^2r2T!OJN^e@$q=OV}}tQh!kJSR}z z2s(To^tc>6@&P;XwQ1QU@4Ll_<a-pdvw4(0<*@W0g_ZGj$c$#LbcMN-eh+l>y6g%e z-fByZfHu$@7UB0|U+cX&z>|E8aEvwJl9vm_T33S%EG!YH$;VBQe*=fP2C1Hhn!L7- zj4yz^3KKlC9>ZK4JP^Nb6Y$yud=^-rgsvO%mn=S!)69e8IKESG<P-ZVtcV*i&+jjj zvi3N9J>t{}oVH6`aXwGgVtvx#AM*LvdkW41X>m8{VC?j}4W8>hKP|Y=jK7)ZoM#zx zbN_Md`Icnh6Y^|u|IblA&3&?r^D5<yGQ%~VmVJ*a`hFMlJnpl-R?);zblIfz#Ke!5 zz5TLW8$KoYLmXZrPS$S8Gy3+FAI&CjZq2p}aoI5O31rfbW~igrd#%9X3#p(Tay(An zoH!Spqoo40x1NxDx=hk*8s;cqmXiKBLwO_OE;XiM7Xh}dfd2`}|HlgWzs+B&`2V%o z`TVa9WdLI|<Ip(a!?^>#?e{6~+*cI)g5AxA`{H_kPg(x@Ouk9^6+3;(4&|WB2x6pE z0pEn;Te666UwI$CeTjXFS0V1jybA4y9i=XT-!6F^==}}_Lp-s*r{OG#^tM3XCaF)v zDJip9Ke9ZNB`vsj&FpvOxsZ4rk@zzfivX{C$UmIviG2R~5`||WEp&%#FqT*c|60^p zfldaUM}1xCrBdrrmvbVf_~xPPfh^2*JOw$?jE}i}EjZtY4rC#F5%92D6SreO$Spe( zG4~MXcz!hDHZOlO$9XHvgsWR`=5*rCb)0qXJB;NNZiV(Tw4t-riT@WQze0OT8%WvO z<I`t}z|Z&($kUHwfqydqdrdk(lHy-P`45mzf?szbUzMgjbkR1&JEZ(S=2Mr3^9W@N zKf^hoC%6`HEoV7|A?_*g?-rzFcrO2C+1t+|&Y0ktlrn^~Eafw>p*no98=!Am$*-S` zJaLyUP8~OdV=oX+a}{FzTH)M%aZnG_zG~qdSTM7VDLsECj9D3!IldTv^ZfJ2&z2fz z8Q)x4G*@kqKU*`iy#{c-3je*}!7ii?Qr2ISdMaYR=I^W;@srCzXQ`JDLodG;_)pg1 zoDR54bovg1ZcZ1cm#A`kM4UEJE{8s2{QE|Ft-EG%AP3NI9(fZ}wy?w~;Gr%3np13V z#T;+I?<o^ExrVjMEyWnfUmx=b&YYGRbSoIQF>VCTYv3QzFQR>jm<MxGZv`>?x95nA z(<G9viNy7y*xPQL?Wl~MZ=*jFFGYJPe2#=^??wLr=alCXdw>o*RSMXL5q}e=7BFRi z`Bs#=5I$DVBmK2KkL;mdTL2k7l+VBAXrKjTh<k;Os#^s5tf?do4*T@k+5WO7;+pl{ zan1UPgk!w?cXHgIJ7&%CkEPbSW84?kjsZVM>4~Mlcg$QU?d_O3$IpW|%}S3G_P7CG zQNh-|2W$;sj~NTG?mB7jkBf!=Jm4sdluNxdhWas#BORW^T*u6{ZbIxi*$>~2xQ)ra zBR=QStbQGBv19pse9T%nrPs@`hSb{ydwyh=J@;eJRuSCiW`TPca7IgD>zl8K-bM^k zgG73r08aD^=|9$GY%hiN;j7l2fZcLHkKKwM<n;+fj}wX>*I|A~ER1QHj1HXRcURBE z<+fRH*$7<dN0o_<*;*l<hn#rhkn{1LIsOUIuFQbkCRamlp|cFiZP%1+m0EVT6ZnjS z{<KSdI_0R#J7F!{R%Q+KBY&*c8rZ`<X{l{4*MJ`U_OYs&c(u-g*Of|sPGamyB|Gn6 z|LfHL7h-=W)&5Tw$isXkI}?DtNx{M=i@$@tOaQ)I`U1B1)n5jEO`51%Q-qH(3qEsz zPh$~W$t-Xh@#dWya6bdw&nVo_0-wbSpU(iFGYa=J1-N%B+$RBhv4Z_A!V1EUjh_(# zEaQPs$ar9*cOCjCDXVBhoDu&X&YG-4Uq#@nWAB&o%!TVkt%JF6&Cf}hKN2;qfk@PP zr4;QkEjj3Z9z2Bp+QE4^$B*;*_Opt|;CuGA2z8E(H|i$UdD6{pXA<*9ajwo%h9S3z zW$HrQc!o|CosGW|=hN>mprc+Yf_q^WxUcdq2RKd2ec9gAil3DG-lFltvy6WN<5NX& zduD;#CC)$7Uzi1Mfc`tqFwb(mI?pEW7U(B8K>i^Qq6Kt;F4Z=#bvIyKr`S+U8j`Lz zE?VpE=N=jYee~-}A7M<4{VUPGN9_@@LcB~{=)=K24Zq9#h92a9ggmN|-YNR4@h2Ms zTSXkBMg9t5qS~BT2v1#Ejycfg??z1CE&ab^KJk12c*4%ry@>VKV9qryf$v()_)o^% zw)cX>&GCK{_2!nq2j^P6<7NLkv@ZsJw}{|eCqRqNinVU#ht|5A)xMyA;)#YpP7@8& z=b}o+{6Sl1;Cs~>!24o7SfAwzl#Au&L$mN{0pRx)!PU$HSE2B%0iLUY=S`sha)sxd zS?ob%mN~+higVS&|6e+pKV1u4Kcb1#u%)Ngz<29LvS0&NRZiQ1MkMM1>Z-L@+TLF5 zjrV8sC%L}uP5k-v9ZOA8#may^t_8lp9Ki7|g*GOH3*(}|e_c=C^!a~-Puj@w7_<8q zc{%oX)E?o30!8~p@a`Ey-4hufo*7pZ`^#CZ`xJ2C{RMR6>B9aF&});V$3f+j9hA5< zjTZW4GG11G*$Mb%2NCz#*&hHmq4rbgv$si~Jh;n}XH>p9_4!S5uLFJ~+8SB5`h4Dp zalOJAs28zP50Z&=7U^N6&B~v)F#o<nn!zWMF;YOgx*vgdRnU_-zpwWIuEz*qBN(fj zTb!8L?_`3wem{9;(Pwvv%a^52WxTfvGO<d^(U5G@%)zffW}eYo`o4;|`cFjiQS=S_ z(U!iP5W{}V$~eN>>2ogP8RA^Hk1$5h*w`;(fvrxkZ!!91pK&JlpffHIo4smvmnN)7 z{Y^dKPiDkVz@|s)=?{QMS-_7DxP6fEQfsk89}9lzU&uQck#f)SZOHsWj$`tWdBlDD z1DW69Coo@`im%g1fBkC*qm#gov3q035+~B|L{8ovty=78snxC~9+WW=<MR@E$76fn zqzobE7Qx)o&n}Fw6Y6e}_lmVGA^#5{AM@#3cY^-c$UTnv>*;5ptf$AILvHmTN_7#m z)0SRAyK80Kdf2UcWv@-x;HxKtvw%6`^~!$M7uf3-Wv?3nd%1#b2CNBt-AJF*biDnL zlMLl3x!32NDq}zTsXbD5kN7d8P=6eR{`hH;{y6AgEOqQQ*TnuV<2vbAeBSAa<SRLY zx<&b_jKOcgp2?rMj7!Apq(MXk{w8@r{gMJ7<z0f(FP{aSdkW5~09{De9^OqL_AG;p z67C*#rbE3F-a}8F5p7S7{oR%C(O=nrUO(G^7@4Un*yhaAR#@*TxN{N;Ptu=vKATjm z9^9{~JC^4bz9z!6Z|<gE@k0B=c^jw349GEBFlGVQn6jC?Gl0W&cjdHR<=G|<$HC{V zIL}+5Pq&7;i1!_%yM4W7IH$K{a=bf<gC9RfTqTU%ezV1t@ssL3(n7rz^;Y$s*@k+D z6})E(tXB^ig$#M!=t~*{KHn-6L2UTEa0Y$qY1$If_sQ#L(l`x0n>K=XNR4=z&<DUv zwDimS;dr3)6<)(geZXlLxb*?2Vc^yWoQ8p0A8;B5Zhd|?>K&+)mQUsb9nJL%*AD4Z z$U6(PwyeO1Xa-KrN=G-Ly-Br)x?7G#AIH;PrcL3{Rz@2j$GrboBplv@j4ztD3-v{J zHRNNc_bnw?_f)>OEt?JJ;x_7^GNpeQKg}gwp;y~L2NU`z3SHYJ@3&qZU#;8Oq5sOm zS9w|b(7RaXos@WWob&#n?0a>*0_E+h+|C#x6|^nEoYZk)%uhM4hn{@s=hOvu_SchK zJDBSsHJ<o9pvs&l9A_&1`YAP5j+3-`)i2ZmQMEU1lyOAL6F(Vw0)E)3!NtN^gVcr8 zjr2M7mJgkFDty<6tkN!?npb6edNb$V?Hh~%&GoKf^tt?Qf!_oqL~y2x*9_MKi%v~o zjhB#KMj9(vFJ7?Tg{(yxEqt5eI=ssd<YK41k4-7ryG7aQz)o(Eu{Pr`>Svyt;QirI z3B&%MP3h{L>K;8fi`2J0NSl@*4!C~Wub|JR)0dF<ywX3;M$~)T_vO7V?|ah@?R??5 z+JbR}{rmTTy-*o`uQqvK$TIaF`~;mojMay7HSd7pwD;QRwBFUM!=TMSjwj5peZ9QH zly8lgqXKix!yHj-H{#DnA&baO<VAG@V+ngEpWh+x&%*vu%EV^s%^m-fwZr{H&=&YW zq_x-|5r&KtbxXY^g>xBij2E{3Jlq4u<qgf%T0w)h0qjTK31L4w#|x8zaqNR%v_q5l zqaAHr{}&2(=|9S~4vkYrCkt>Tk6TkCerq!H*=(<wvIrh0Du;532G}cO8~oxg=MuCh zqdVPF(B(g&x5@t~_}>e8GsUznY?SW~0gvm|TbkA~l+&p9aXw1n3rM|RFh0bkyU70) zfiDqX6}(4yZRTJM>y{_gJ$CrUB5fypqt_sxQlBRW{ATJK3DYTINMDRya11cSo#&*n zz;?)Ug0YQ?77_W@*OdkAwY104iJEcsZO&yJzZJ@fY1)U8KBPQT3DAJ&>lx~Pr3aeY zX5Rgu`{#VFP-bGYoC`zIW0iVWH=}|6nqlvF53I(1=a>1@#X3jGyH&*O?1N5j{21Z8 zyeRbDt&o}HmkMVb=^doANTNwNWk@whCX$7;3aJaJ7ik~TDAGx!3Bp{-ed}%~=3;p+ za{G#)?Rr(FUv8tXoiV=YWWR#)HH24ityAU2F6$QRC5wftX^>sMyO?(5^02L8J>S!+ zFGan4u?S*I^(IrUuV=haN%%#oU(=`ib#1zzK5qGPA<td8zM(qU$6_~xWjk=G;@eL` z!D{*jPuBw2A~>BmQHL;&5OSaV{tA33IBTKpt`ITzX7U5PF~ofD`s-r)p@^-~N3KZ3 zB%fEJKW)X_L(3_L!5d07<C_l)CyjJBQV&v1GN5@Ya@xeMB)@&Z`s#ZG^8QN9^(@+T z-SG65K`)ZDD~V%oGWa&e3g6>H97lt=EwUo!F1c=c{cloUu;!Y}g)@mX)GVB6&rY|Z zJ?2)#H}G4lx{Bqmc-mEmyd`ZIhtzo~?0HkatHW>nDEC)}{gokJ_+{V^=+XJSE2@jd z5d$H;m=EZ}7$Tp<yd5$3nH6@nx6{sk=xUVPNxuLegm<T&ybKy2={ckWNG~CcBAq}I zz%f~r8j+fjT9G;~C;lZ4WhvToiL;b4*3<1Qk@dTr2AOYnC`+W{j}Qyl^Q2C9qt<pu z^b9z)s_**+eI-`6Bk#C+AZtCHdWC}dhZ*DVngLT1ti^X;<mx@A=T(0Hh1|*V9c6;C z5bV9)I^agkn8R;5G#L}_blIns%%|Ruhx}l?T(KtRHiF*Yz}jW-=PSy(`2JfNN!ywR z+Rvw5LeBSQJvQHqwcC|T+S$L|m`A>V-l%6w(swxYfe6F9y^vqOL4KvTJLFf`wi0b6 z>9oW5V&bLu&Ug7e1Mxcw{Pgnq-eKaYaC?NfnbWxGz%AcldwJ;hh!b;4dB+ipxwm(a zcGaHN^GFqK(LC59X-oJ%v1PmAV!zS!O|FyApUStsBJUH3?+uYhvA;}JnRpar-RTgg zkY?f840UMtWFUVcwNLuaf2QumOVqm?W7rkgpZxAa49M>)$ScNkQQo=A_-~J2D`T=D z`S#w>;dt#UXsa^vF6CjIzNP{lE@MF>j33qov89S15-PR`W0K;r@Ar-@3ifpc_Qlv3 zzAnFet=9OpHRb8jX}c7{E&*)R06$P~n#|9Li#7PXdPBb}W7m!WiDUJzp{=q{`qDAr zUD`G<6+=zgw`IY&Aimn;>#=H&zDU(|Xm8=0<G}mEYv;l5_4$oc@!sisPx<U>4*Da) z==X09$0C;Ppf4_YXJ>a5v@>>={+Sq<&-nSGz`uLziwb6Ic;|z4j~9H?@Iv^uu3|vG zH4e+S_s9J*wp*F;#OPzey^J%A_U+*LUdHX&sL>BUf4d(Y&G=CPeA&l)IM9}S5XN@D z3%r|`j5_@OXseafg|$6aE*?7>3Eo9sZ!<=uEQ*%hxrnIYoBaaD**f}(zhV8Q^nu=@ z|EIovXodgMi!^ite3^nf2KlX=@*U#v6{uqv-~G9|@BKP*qrlH7eD{~{S@Le=n12fA zM6=HLp>JzES9s^6zUQ%a`3CrNxvBggF?|oiZw%yofEylCJ}Td^sUL0Vnv5N>GIsTc zt+j4j8gV9l@=WJAZOtU_C=jPc#m1}!JKbij<y(^;SKqYo-THZX-}l2@)Ot0?I@>>w zHoi%TRLVU=ePVsdm*4*<?WdQC+oYb<tX0sz-_Mmn|Ds)s+OOuQ|F+6|^zY|h;J%Zq z<hN<q_w(WXc@Y1kyfDs{=bZO()?rDbO2&Qf@V?|x#CwO~yQZCaSR3~EnYoa|xL8jg zBW_wN-P<XnqxJxOY7xXt@o=6W1Mk9Emvjv84w{WQKHuiw;x~~=!~IX}=efv;|3%bk zV;)C7jQS(;UcvT$4|%h-(2r_+bAKfFH7MU^5re+<FyKCiwv+TXl0Wd5(ytVD<x$co z`7_@CdY5CL7TU!Sbj}d?1=^L%ZxY0gl9uhxfHmk4)=GD}mdQRD&+K0cxDCqAe-HC_ zT!r}m|2QR(PON~Rv*Lr#F*(cFZ(ZPg|C{Seo{GKW&GPM(-wvg}xop&aQKWbIamH`t zDawU#Jg1C%%Mt5bL|N#0#J!8}Z}QFcsQ>OcB`dJoglGTlsy~`iYw=8Gp!00{o*T1m z>qcS;btbQp-{~5`x3}7e|F4*j?LR?YyKcmf4<VMZZgLlhTRr$M2cy=TIj%8vpAFe$ z+thtF;7UYSWl7RLD8whcl1#TzVt0!&#%l6^dEmRJZ+2rsyhU06+jI1hru(2bUl-P! zzApXgH~qglM}77me)v5W&$uRf<$X*X<4Ww{{-#0A_dMX)uGu$F%~v-?uUkDWc~jM* zB<yf%ufMT1@NKSuU2cJW{?fTXhu|!nT8g=zI2X{HKG+cS%yURDARRz@3F!?a!tGLU z)YCiYyI4Pv_+G?s1(hDE5YR*XW*a)820Eb(I*z<am|yanOz;`?M$~IiH&L%eUA|SI zUW>YkdJXE0s2hBP7Z`7>b-i=>^X|~+ikbK7v@O5d7dSM-7f2S}l}r5@-m|`sKT_<A zJX|$x<3jtEPe$GGeDD^@@5E`N=z}eicW|`z(8sW$3xsIbbogdsU5i#_w?vlPEzs@l zx)!wc8FtHn6|@mv6G<~-_BT9@^3y0kgK~qG$~I_8b4df*QGOcbXHe$(TeAE>WkZ!+ zN!?AKg#Swrb(Z;82z7^$`OZn=b&0}@YXGL@LU9WBLA*koyaJr=D8R`>neU2)c)iQF zx5ZU1*3{n7ssNWU?m^yw{2hV1$QU8cS^>^%vs#v~Xuay{Yuc{e^4oWG-+34R+2P}B zg;;I1h!oOlYX#DBu@dDCJrCah>H8jh!2HO)y?5S!|ARff4Gj(EGV`H3@94en{&sU| zceB~OrFRQT592I|rB>Ufc9Z$?O`O*><$aVex1#M1_%#5UUjN3GovT*gM7WNXTe{7= z?z{hYxAdA1^xpsJdq2flFs@yQ>oKO|-Usiw2Yz<P$L{Mjw@iUp4+G|UapAw?mk8&7 zEBz19_<#31xj;B=bu;(C|3xXRTSbI63(Al&0Ua!0rv&T;|8++8Cy_E208rQ+_GyKS zm559RDTy>%8cZ4fM$snFmMjfm!uCuNT=7p+OTl~3WRQ3XGoSS;)R8VinJKv#^~LAU MW!w<t@4$xtH;eg_5C8xG
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/hal_cache.h @@ -0,0 +1,307 @@ +#ifndef CYGONCE_HAL_CACHE_H +#define CYGONCE_HAL_CACHE_H + +//============================================================================= +// +// hal_cache.h +// +// HAL cache control API +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-28 +// Purpose: Cache control API +// Description: The macros defined here provide the HAL APIs for handling +// cache control operations. +// Usage: +// #include <cyg/hal/hal_cache.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_mmu.h> + +//----------------------------------------------------------------------------- +// Cache dimensions + +#define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes +#define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line +#define HAL_UCACHE_WAYS 4 // Associativity of the cache +#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) + +#define HAL_CACHE_UNIFIED // Let programs know the caches are combined + +//----------------------------------------------------------------------------- +// Global control of caches + +// Note: the 'mrc' doesn't seem to work. +#if 0 +// Enable the data cache +// mrc MMU_CP,0,r1,MMU_Control,c0 +// orr r1,r1,#MMU_Control_C|MMU_Control_B +// mcr MMU_CP,0,r1,MMU_Control,c0 + +#define HAL_UCACHE_ENABLE() \ +{ \ + asm volatile ("mrc p15,0,r1,c1,c0;" \ + "orr r1,r1,#0x000C;" \ + "mcr p15,0,r1,c1,c0;" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ + \ +} + +// Disable the data cache +#define HAL_UCACHE_DISABLE() \ +{ \ + asm volatile ("mrc p15,0,r1,c1,c0;" \ + "bic r1,r1,#0x000C;" \ + "mcr p15,0,r1,c1,c0;" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ + \ +} +#else +#define HAL_UCACHE_ENABLE() \ +{ \ + asm volatile ("mov r1,#0x7D;" \ + "mcr p15,0,r1,c1,c0;" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ + \ +} + +// Disable the data cache +#define HAL_UCACHE_DISABLE() \ +{ \ + asm volatile ("mov r1,#0x71;" \ + "mcr p15,0,r1,c1,c0;" \ + : \ + : \ + : "r1" /* Clobber list */ \ + ); \ + \ +} +#endif + +// Is the cache turned on? +#define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1; + +// Invalidate the entire cache +// mcr MMU_CP,0,r1,MMU_InvalidateCache,c0 +#define HAL_UCACHE_INVALIDATE_ALL() \ +{ \ + asm volatile ("mcr p15,0,r1,c7,c0,0;" ); \ + \ +} + +// Synchronize the contents of the cache with memory. +#define HAL_UCACHE_SYNC() \ +{ \ + cyg_uint32 *ROM = (cyg_uint32 *)0xE0000000; \ + int i; \ + volatile cyg_uint32 val; \ + for (i = 0; i < HAL_UCACHE_SETS; i++) { \ + val = *ROM; \ + ROM += HAL_UCACHE_LINE_SIZE; \ + } \ +} + +// Purge contents of data cache +#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Set the data cache refill burst size +//#define HAL_UCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_UCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_UCACHE_WRITETHRU_MODE 0 +//#define HAL_UCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_UCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_UCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_UCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC() + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +#define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC() + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_UCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of data cache + +#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE +#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS +#define HAL_DCACHE_SETS HAL_UCACHE_SETS + +// Enable the data cache +#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the data cache +#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() + +// Query the state of the data cache +#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) + +// Set the data cache refill burst size +//#define HAL_DCACHE_BURST_SIZE(_size_) + +// Set the data cache write mode +//#define HAL_DCACHE_WRITE_MODE( _mode_ ) + +//#define HAL_DCACHE_WRITETHRU_MODE 0 +//#define HAL_DCACHE_WRITEBACK_MODE 1 + +// Load the contents of the given address range into the data cache +// and then lock the cache so that it stays there. +//#define HAL_DCACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_DCACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_DCACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Data cache line control + +// Allocate cache lines for the given address range without reading its +// contents from memory. +//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) + +// Write dirty cache lines to memory and invalidate the cache entries +// for the given address range. +#define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ ) + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) + +// Write dirty cache lines to memory for the given address range. +#define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of reading +// from it later. +//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) + +// Preread the given range into the cache with the intention of writing +// to it later. +//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) + +// Allocate and zero the cache lines associated with the given range. +//#define HAL_DCACHE_ZERO( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +// Global control of Instruction cache - use Data cache controls since they +// are not separatable. + +#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE +#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE +#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS +#define HAL_ICACHE_SETS HAL_UCACHE_SETS + +// Enable the instruction cache +#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() + +// Disable the instruction cache +#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() + +// Invalidate the entire cache +#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() + +// Synchronize the contents of the cache with memory. +#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() + +// Set the instruction cache refill burst size +//#define HAL_ICACHE_BURST_SIZE(_size_) + +// Load the contents of the given address range into the instruction cache +// and then lock the cache so that it stays there. +//#define HAL_ICACHE_LOCK(_base_, _size_) + +// Undo a previous lock operation +//#define HAL_ICACHE_UNLOCK(_base_, _size_) + +// Unlock entire cache +//#define HAL_ICACHE_UNLOCK_ALL() + +//----------------------------------------------------------------------------- +// Instruction cache line control + +// Invalidate cache lines in the given range without writing to memory. +//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) + +//----------------------------------------------------------------------------- +#endif // ifndef CYGONCE_HAL_CACHE_H +// End of hal_cache.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/hal_cl7211.h @@ -0,0 +1,243 @@ +#ifndef CYGONCE_HAL_CL7211_H +#define CYGONCE_HAL_CL7211_H + +/*============================================================================= +// +// hal_cl7211.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-19 +// Purpose: Cirrus Logic CL7211 hardware description +// Description: +// Usage: #include <cyg/hal/hal_cl7211.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +// Note: these defintions match the documentation, thus no attempt is made +// to sanitize (mangle) the names. Also, care should be taken to keep this +// clean for use in assembly code (no "C" constructs). + +#define PADR 0x80000000 // Port A data register +#define PBDR 0x80000001 // Port B data register +#define PDDR 0x80000003 // Port D data register +#define PADDR 0x80000040 // Port A data direction register +#define PBDDR 0x80000041 // Port B data direction register +#define PDDDR 0x80000043 // Port D data direction register +#define PEDR 0x80000080 // Port E data register +#define PEDDR 0x800000C0 // Port E data direction register + +#define SYSCON1 0x80000100 // System control register #1 +#define SYSCON1_TC1M (1<<4) // Timer/counter #1 - prescale mode +#define SYSCON1_TC1S (1<<5) // Timer/counter #1 - source (1=512KHz,0=2KHz) +#define SYSCON1_TC2M (1<<6) // Timer/counter #2 - prescale mode +#define SYSCON1_TC2S (1<<7) // Timer/counter #2 - source (1=512KHz,0=2KHz) +#define SYSCON1_UART1EN (1<<8) // UART #1 enable +#define SYSCON1_BZTOG (1<<9) // Buzzer bit +#define SYSCON1_BZMOD (1<<10) // Buzzer mode (0=direct,1=TC1) +#define SYSCON1_DBGEN (1<<11) // Enable debug mode +#define SYSCON1_LCDEN (1<<12) // Enable LCD +#define SYSCON1_CDENTX (1<<13) // Enable Tx on CODEC +#define SYSCON1_CDENRX (1<<14) // Enable Rx on CODEC +#define SYSCON1_SIREN (1<<15) // Enable SIR protocol on UART #1 +#define SYSCON1_ADCKSEL (3<<16) // Microwire clock +#define SYSCON1_EXCKEN (1<<18) // External expansion clock enable +#define SYSCON1_WAKEDIS (1<<19) // Disable wakeup from snooze (do not disturb) +#define SYSCON1_IRTXM (1<<20) // IrDA Tx mode + +#define SYSCON2 0x80001100 // System control register #2 +#define SYSCON2_SERSEL (1<<0) // 0=master/slave SSI, 1=CODEC +#define SYSCON2_KBD6 (1<<1) // 0=8 bit keyboard, 1=6 bit +#define SYSCON2_DRAMSZ (1<<2) // DRAM width 0=32, 1=16 +#define SYSCON2_KBWEN (1<<3) // 1=allow wake up from keyboard +#define SYSCON2_SS2TXEN (1<<4) // Enable Tx on SS2 +#define SYSCON2_PCMCIA1 (1<<5) // Enable PCMCIA slot #1 +#define SYSCON2_PCMCIA2 (1<<6) // Enable PCMCIA slot #2 +#define SYSCON2_SS2RXEN (1<<7) // Enable Rx on SS2 +#define SYSCON2_UART2EN (1<<8) // Enable UART #2 +#define SYSCON2_SS2MAEN (1<<9) // Enable master mode on SS2 +#define SYSCON2_SNZPOL (1<<10) // Polarity of LCD during snooze +#define SYSCON2_LCDSNZE (1<<11) +#define SYSCON2_OSTB (1<<12) // Operating system timing 0=512KHz, 1=500KHz +#define SYSCON2_CLKENSL (1<<13) // Source of run/clken signal 0=CLKEN, 1=RUN +#define SYSCON2_BUZFREQ (1<<14) // Buzzer frequency 0=timer, 1=fixed PLL/xtal + +#define SYSCON3 0x80002200 // System control #3 +#define SYSCON3_CLKCTL(n) (n<<1) // Processor block speed ((n+1)*18.432)MHz + +#define SYSFLG1 0x80000140 // System flags #1 +#define SYSFLG1_MCDR (1<<0) // Media changed - direct read +#define SYSFLG1_DCDET (1<<1) // 0=mains power, 1=battery +#define SYSFLG1_WUDR (1<<2) // Wakeup direct +#define SYSFLG1_WUON (1<<3) // Woken up +#define SYSFLG1_DID (0xF<<4) // Display ID +#define SYSFLG1_CTS (1<<8) // UART1 CTS +#define SYSFLG1_DSR (1<<9) // UART1 DSR +#define SYSFLG1_DCD (1<<10) // UART1 DCD +#define SYSFLG1_UBUSY1 (1<<11) // UART1 Tx busy +#define SYSFLG1_NBFLG (1<<12) // New battery flag +#define SYSFLG1_RSTFLG (1<<13) // Reset (button) flag +#define SYSFLG1_PFFLG (1<<14) // Power fail flag +#define SYSFLG1_CLDFLG (1<<15) // Cold start flag +#define SYSFLG1_RTCDIV (0x3F<<16) // Real time clock divider (counter) +#define SYSFLG1_URXFE1 (1<<22) // UART1 Rx FIFO empty +#define SYSFLG1_UTXFF1 (1<<23) // UART1 Tx FIFO full +#define SYSFLG1_CRXFE (1<<24) // CODEC Rx FIFO empty +#define SYSFLG1_CTXFF (1<<25) // CODEC Tx FIFO full +#define SYSFLG1_SSIBUSY (1<<26) // Synchronous serial interface busy +#define SYSFLG1_BOOTBITS (3<<27) // Boot mode (0=32,1=8,2=16,3=XX) +#define SYSFLG1_ID (1<<29) // ID=1 +#define SYSFLG1_VERID (3<<30) // Board version + +#define SYSFLG2 0x80001140 // System flags #2 + +#define INTSR1 0x80000240 // Interrupt status register #1 +#define INTSR1_EXTFIQ (1<<0) // External fast interrupt +#define INTSR1_BLINT (1<<1) // Battery low interrupt +#define INTSR1_WEINT (1<<2) // Watchdog expired interrupt +#define INTSR1_MCINT (1<<3) // Media changed interrupt +#define INTSR1_CSINT (1<<4) // CODEC sound interrupt +#define INTSR1_EINT1 (1<<5) // External interrupt #1 +#define INTSR1_EINT2 (1<<6) // External interrupt #2 +#define INTSR1_EINT3 (1<<7) // External interrupt #3 +#define INTSR1_TC1OI (1<<8) // Timer/counter #1 underflow +#define INTSR1_TC2OI (1<<9) // Timer/counter #2 underflow +#define INTSR1_RTCMI (1<<10) // Real time clock match +#define INTSR1_TINT (1<<11) // 64Hz tick +#define INTSR1_UTXINT1 (1<<12) // UART1 Tx interrupt +#define INTSR1_URXINT1 (1<<13) // UART1 Rx interrupt +#define INTSR1_UMSINT (1<<14) // UART1 modem line change +#define INTSR1_SSEOTI (1<<15) // Synchronous serial end of transfer +#define INTMR1 0x80000280 // Interrupt mask register #1 + +#define INTSR2 0x80001240 // Interrupt status #2 +#define INTSR2_KBDINT (1<<0) // Keyboard interrupt +#define INTSR2_SS2RX (1<<1) // Synchronous serial #2 Rx +#define INTSR2_SS2TX (1<<2) // Synchronous serial #2 Tx +#define INTSR2_UTXINT2 (1<<12) // UART #2 Tx interrupt +#define INTSR2_URXINT2 (1<<13) // UART #2 Rx interrupt +#define INTMR2 0x80001280 // Interrupt mask #2 + +#define INTSR3 0x80002240 // Interrupt status #3 +#define INTSR3_MCPINT (1<<0) // MCP interrupt +#define INTMR3 0x80002280 // Interrupt mask #3 + +#define UARTDR1 0x80000480 // UART #1 data register +#define UARTDR2 0x80001480 // UART #2 data register +#define UBLCR1 0x800004C0 // UART #1 baud rate / line control +#define UBLCR2 0x800014C0 // UART #2 baud rate / line control +#define UBLCR_BRDV 0xFFF // Baud rate +#define UBLCR_BREAK (1<<12) // Generate break signal +#define UBLCR_PRTEN (1<<13) // Enable parity +#define UBLCR_EVENPRT (1<<14) // 1=even parity, 0=odd +#define UBLCR_XSTOP (1<<15) // 0=1 stop bit, 1=2 stop bits +#define UBLCR_FIFOEN (1<<16) // Enable Tx/Rx FIFOs +#define UBLCR_WRDLEN (3<<17) // Word (character) length field +#define UBLCR_WRDLEN5 (0<<17) +#define UBLCR_WRDLEN6 (1<<17) +#define UBLCR_WRDLEN7 (2<<17) +#define UBLCR_WRDLEN8 (3<<17) +#define UART_DIVISOR 230400 +#define UART_BITRATE(baud) ((UART_DIVISOR/(baud))-1) + +#define MEMCFG1 0x80000180 // Memory configuration register #1 +#define MEMCFG2 0x800001C0 // Memory configuration register #2 + +#define DRFPR 0x80000200 // DRAM refresh period + +#define LCDCON 0x800002C0 // LDC control +#define LCDCON_BUFSIZ 0x00001FFF // Video buffer size +#define LCDCON_BUFSIZ_S 0 // Position of buffer size +#define LCDCON_LINE_LENGTH 0x0007E000 // Line length +#define LCDCON_LINE_LENGTH_S 13 // Position of line length +#define LCDCON_PIX_PRESCALE 0x01F80000 // Pixel prescale value +#define LCDCON_PIX_PRESCALE_S 19 // Position of prescale value +#define LCDCON_AC_PRESCALE 0x3E000000 // LCD AC bias frequency +#define LCDCON_AC_PRESCALE_S 25 // Position to AC bias +#define LCDCON_GSEN 0x40000000 // Enable greyscale +#define LCDCON_GSMD 0x80000000 // Greyscale mode + // 00 - 1bpp, 01 - 2bpp, 11 - 4 bpp + +#define TC1D 0x80000300 // Timer/Counter #1 register +#define TC2D 0x80000340 // Timer/Counter #2 register +#define RTCDR 0x80000380 // Real time clock data register +#define RTCMR 0x800003C0 // Real time clock match register + +#define PMPCON 0x80000400 // DC-DC pump control + +#define CODR 0x80000440 // CODEC data register + +#define SYNCIO 0x80000500 // Synchronous I/O data register + +#define PALLSW 0x80000540 // LCD palette - LSW (Pixel values 0..7) +#define PALMSW 0x80000580 // LCD palette - MSW (Pixel values 8..15) + +#define STFCLR 0x800005C0 // Clear startup reason flags +#define BLEOI 0x80000600 // Clear battery low interrupt +#define MCEOI 0x80000640 // Clear media changed interrupt +#define TEOI 0x80000680 // Clear tick/watchdog interrupt +#define TC1EOI 0x800006C0 // Clear timer/counter #1 interrupt +#define TC2EOI 0x80000700 // Clear timer/counter #2 interrupt +#define RTCEOI 0x80000740 // Clear real time clock interrupt +#define UMSEOI 0x80000780 // Clear UART modem status change interrupt +#define COEOI 0x800007C0 // Clear CODEC sound interrupt + +#define HALT 0x80000800 // Enter 'idle' state +#define STDBY 0x80000840 // Enter 'standby' state + +#define FRBADDR 0x80001000 // LCD frame buffer start + +#define SNZDISP 0x800012C0 // Snooze display size + +#define SS2DR 0x80001500 // Master/slave SSI2 register + +#define SRXEOF 0x80001600 // Clear Rx FIFO overflow flag +#define SS2POP 0x800016C0 // Pop SSI2 residual byte into FIFO + +#define KBDEOI 0x80001700 // Clear keyboard interrupt + +#define SNOOZE 0x80001800 // Enter 'snooze' state + +#define MCCR 0x80002000 // MCP control register +#define MCDR0 0x80002040 // MCP data register #0 +#define MCDR1 0x80002080 // MCP data register #1 +#define MCDR2 0x800020C0 // MCP data register #2 +#define MCSR 0x80002100 // MCP status register + +#define LEDFLSH 0x800022C0 // LED flash control +#define LEDFLSH_ENABLE (1<<6) // LED enabled +#define LEDFLSH_DUTY(n) ((n-1)<<2) // LED on ratio +#define LEDFLSH_PERIOD(n) (n-1) // LED active time (1..4) + +/*---------------------------------------------------------------------------*/ +/* end of hal_cl7211.h */ +#endif /* CYGONCE_HAL_CL7211_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/hal_diag.h @@ -0,0 +1,67 @@ +#ifndef CYGONCE_HAL_DIAG_H +#define CYGONCE_HAL_DIAG_H + +/*============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors: nickg, gthomas +// Date: 1998-09-11 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +/*---------------------------------------------------------------------------*/ +/* functions implemented in hal_diag.c */ + +externC void hal_diag_init(void); +externC void hal_diag_write_char(char c); +externC void hal_diag_read_char(char *c); + +/*---------------------------------------------------------------------------*/ + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +/*---------------------------------------------------------------------------*/ +/* end of hal_diag.h */ +#endif /* CYGONCE_HAL_DIAG_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/hal_platform_ints.h @@ -0,0 +1,85 @@ +#ifndef CYGONCE_HAL_PLATFORM_INTS_H +#define CYGONCE_HAL_PLATFORM_INTS_H +//========================================================================== +// +// hal_platform_ints.h +// +// HAL Interrupt and clock support +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-21 +// Purpose: Define Interrupt support +// Description: The interrupt details for the CL7211 are defined here. +// Usage: +// #include <cyg/hal/hal_platform_ints.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#define CYGNUM_HAL_INTERRUPT_unused 0 +#define CYGNUM_HAL_INTERRUPT_EXTFIQ 1 +#define CYGNUM_HAL_INTERRUPT_BLINT 2 +#define CYGNUM_HAL_INTERRUPT_WEINT 3 +#define CYGNUM_HAL_INTERRUPT_MCINT 4 +#define CYGNUM_HAL_INTERRUPT_CSINT 5 +#define CYGNUM_HAL_INTERRUPT_EINT1 6 +#define CYGNUM_HAL_INTERRUPT_EINT2 7 +#define CYGNUM_HAL_INTERRUPT_EINT3 8 +#define CYGNUM_HAL_INTERRUPT_TC1OI 9 +#define CYGNUM_HAL_INTERRUPT_TC2OI 10 +#define CYGNUM_HAL_INTERRUPT_RTCMI 11 +#define CYGNUM_HAL_INTERRUPT_TINT 12 +#define CYGNUM_HAL_INTERRUPT_UTXINT1 13 +#define CYGNUM_HAL_INTERRUPT_URXINT1 14 +#define CYGNUM_HAL_INTERRUPT_UMSINT 15 +#define CYGNUM_HAL_INTERRUPT_SSEOTI 16 +#define CYGNUM_HAL_INTERRUPT_KBDINT 17 +#define CYGNUM_HAL_INTERRUPT_SS2RX 18 +#define CYGNUM_HAL_INTERRUPT_SS2TX 19 +#define CYGNUM_HAL_INTERRUPT_UTXINT2 20 +#define CYGNUM_HAL_INTERRUPT_URXINT2 21 +#if defined(__CL7211) +#define CYGNUM_HAL_INTERRUPT_MCPINT 22 +#endif + +#define CYGNUM_HAL_ISR_MIN 0 +#if defined(__CL7211) +#define CYGNUM_HAL_ISR_MAX 22 +#else +#define CYGNUM_HAL_ISR_MAX 21 +#endif +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) + +// The vector used by the Real time clock +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TC2OI + +#endif // CYGONCE_HAL_PLATFORM_INTS_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/hal_platform_setup.h @@ -0,0 +1,394 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-21 +// Purpose: Cirrus CL7211 platform specific support routines +// Description: +// Usage: #include <cyg/hal/hal_platform_setup.h> +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_cl7211.h> // Platform specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions + +#define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) + +// +// Memory map - set up by ROM (GDB stubs) +// +// Region Logical Address Physical Address +// DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below) +// Expansion 2 0x20000000 0x20000000 +// Expansion 3 0x30000000 0x30000000 +// PCMCIA 0 0x40000000 0x40000000 +// PCMCIA 1 0x50000000 0x50000000 +// SRAM 0x60000000..0x600007FF 0x60000000 +// I/O 0x80000000 0x80000000 +// MMU Tables 0xC00y0000 +// LCD buffer 0xC0000000..0xC001FFFF 0xC0000000 +// ROM 0xE0000000..0xEFFFFFFF 0x00000000 +// ROM 0xF0000000..0xFFFFFFFF 0x10000000 + +#ifdef CYGHWR_HAL_ARM_CL7211_LCD_INSTALLED +#define MMU_BASE 0xC0020000 +#define PTE_BASE 0xC0024000 +#define LCD_BUFFER_SIZE 0x00020000 +#else +#define MMU_BASE 0xC0000000 +#define PTE_BASE 0xC0004000 +#define LCD_BUFFER_SIZE 0x00000000 +#endif +#if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2) +#define MMU_TABLES_SIZE 0x4000+0x1000+0x1000 // RAM used for PTE entries +#define DRAM_LA_END 0x00200000-MMU_TABLES_SIZE +#elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16) +#define MMU_TABLES_SIZE 0x4000+0x4000+0x1000 // RAM used for PTE entries +#define DRAM_LA_END 0x01000000-MMU_TABLES_SIZE +#endif +#define DRAM_LA_START 0x00000000 +#define DRAM_PA MMU_BASE+MMU_TABLES_SIZE +#define LCD_LA_START 0xC0000000 +#define LCD_LA_END 0xC0020000 +#define LCD_PA 0xC0000000 +#define ROM0_LA_START 0xE0000000 +#define ROM0_PA 0x00000000 +#define ROM1_LA_START 0xF0000000 +#define ROM1_LA_END 0x00000000 +#define ROM1_PA 0x10000000 +#define EXPANSION2_LA_START 0x20000000 +#define EXPANSION2_PA 0x20000000 +#define EXPANSION3_LA_START 0x30000000 +#define EXPANSION3_PA 0x30000000 +#define PCMCIA0_LA_START 0x40000000 +#define PCMCIA0_PA 0x40000000 +#define PCMCIA1_LA_START 0x50000000 +#define PCMCIA1_PA 0x50000000 +#define SRAM_LA_START 0x60000000 +#define SRAM_LA_END 0x60001000 +#define SRAM_PA 0x60000000 +#define IO_LA_START 0x80000000 +#define IO_LA_END 0x80003000 +#define IO_PA 0x80000000 + +#if (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 2) +// Note: The DRAM on this board is very irregular in that every +// other 256K piece is missing. E.g. only these [physical] +// addresses are valid: +// 0xC0000000..0xC003FFFF +// 0xC0080000..0xC00BFFFF +// 0xC0200000..0xC023FFFF Note the additional GAP! +// etc. +// 0xC0800000..0xC083FFFF Note the additional GAP! +// 0xC0880000..0xC08CFFFF +// 0xC0A00000..0xC0A3FFFF +// etc. +// The MMU mapping code takes this into consideration and creates +// a continuous logical map for the DRAM. +#define MAP_DRAM \ +/* Map DRAM */ ;\ + ldr r3,=DRAM_LA_START ;\ + ldr r4,=DRAM_LA_END ;\ + ldr r5,=DRAM_PA ;\ +/* 0x00000000..0x000FFFFF */ ;\ + mov r6,r2 /* Set up page table descriptor */ ;\ + ldr r7,=MMU_L1_TYPE_Page ;\ + orr r6,r6,r7 ;\ + str r6,[r1],#4 /* Store PTE, update pointer */ ;\ +10: mov r6,r5 /* Build page table entry */ ;\ + ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\ + orr r6,r6,r7 ;\ + ldr r7,=MMU_PAGE_SIZE ;\ + str r6,[r2],#4 /* Next page */ ;\ + add r3,r3,r7 ;\ + add r5,r5,r7 ;\ + ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE ;\ + cmp r3,r8 /* Done with first 1M? */ ;\ + beq 20f ;\ + ldr r7,=0x40000 /* Special check for 256K boundary */ ;\ + and r7,r7,r5 ;\ + cmp r7,#0 ;\ + beq 10b ;\ + add r5,r5,r7 /* Skip 256K hole */ ;\ + ldr r7,=0x100000 ;\ + and r7,r5,r7 ;\ + beq 10b ;\ + add r5,r5,r7 /* Nothing at 0xC0100000 */ ;\ + ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\ + and r7,r5,r7 ;\ + beq 10b ;\ + add r5,r5,r7 ;\ + b 10b ;\ +20: ;\ +/* 0x00100000..0x001FFFFF */ ;\ + mov r6,r2 /* Set up page table descriptor */ ;\ + ldr r7,=MMU_L1_TYPE_Page ;\ + orr r6,r6,r7 ;\ + str r6,[r1],#4 /* Store PTE, update pointer */ ;\ +10: mov r6,r5 /* Build page table entry */ ;\ + ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\ + orr r6,r6,r7 ;\ + ldr r7,=MMU_PAGE_SIZE ;\ + str r6,[r2],#4 /* Next page */ ;\ + add r3,r3,r7 ;\ + cmp r3,r4 /* Done with first DRAM? */ ;\ + beq 20f ;\ + add r5,r5,r7 ;\ + ldr r7,=0x40000 /* Special check for 256K boundary */ ;\ + and r7,r7,r5 ;\ + cmp r7,#0 ;\ + beq 10b ;\ + add r5,r5,r7 /* Skip 256K hole */ ;\ + ldr r7,=0x100000 ;\ + and r7,r5,r7 ;\ + beq 10b ;\ + add r5,r5,r7 /* Nothing at 0xC0300000 */ ;\ + ldr r7,=0x400000 /* Also nothing at 0xC0400000 */ ;\ + and r7,r5,r7 ;\ + beq 10b ;\ + add r5,r5,r7 ;\ + b 10b ;\ +20: ; +#elif (CYGHWR_HAL_ARM_CL7211_DRAM_SIZE == 16) +// The 16M board is arranged as: +// 0xC0000000..0xC07FFFFF +// 0xC1000000..0xC17FFFFF +#define MAP_DRAM \ +/* Map DRAM */ ;\ + ldr r3,=DRAM_LA_START ;\ + ldr r4,=DRAM_LA_END ;\ + ldr r5,=DRAM_PA ;\ +/* 0xXXX00000..0xXXXFFFFF */ ;\ +10: mov r6,r2 /* Set up page table descriptor */ ;\ + ldr r7,=MMU_L1_TYPE_Page ;\ + orr r6,r6,r7 ;\ + str r6,[r1],#4 /* Store PTE, update pointer */ ;\ + ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE ;\ + ldr r6,=DRAM_PA+0x00800000 /* Need to skip at 8M boundary */ ;\ + cmp r5,r6 ;\ + bne 15f ;\ + ldr r5,=DRAM_PA+0x01000000 /* Next chunk of DRAM */ ;\ +15: mov r6,r5 /* Build page table entry */ ;\ + ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\ + orr r6,r6,r7 ;\ + ldr r7,=MMU_PAGE_SIZE ;\ + str r6,[r2],#4 /* Next page */ ;\ + add r3,r3,r7 ;\ + add r5,r5,r7 ;\ + cmp r3,r4 /* End of DRAM? */ ;\ + beq 20f ;\ + sub r8,r8,#1 /* End of 1M section? */ ;\ + cmp r8,#0 ;\ + bne 15b /* Next page */ ;\ + b 10b /* Next section */ ;\ +20: +#else +#err Invalid DRAM size selected +#endif + +#ifdef CYG_HAL_ARM_CL7111 // CL7111, 710 processor +#define MMU_INITIALIZE \ + ldr r1,=MMU_Control_Init ;\ + mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\ + ldr r1,=MMU_BASE ;\ + mcr MMU_CP,0,r1,MMU_Base,c0 ;\ + mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */ ;\ + mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\ + ldr r1,=0xFFFFFFFF ;\ + mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\ + ldr r2,=10f ;\ + ldr r1,=MMU_Control_Init|MMU_Control_M ;\ + mcr MMU_CP,0,r1,MMU_Control,c0 ;\ + mov pc,r2 /* Change address spaces */ ;\ + nop ;\ + nop ;\ + nop ;\ +10: +#else // EP7211, 720T processor +#define MMU_INITIALIZE \ + ldr r1,=MMU_Control_Init ;\ + mcr MMU_CP,0,r1,MMU_Control,c0 /* MMU off */ ;\ + ldr r1,=MMU_BASE ;\ + mcr MMU_CP,0,r1,MMU_Base,c0 ;\ + mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB - 720 style */ ;\ + mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */ ;\ + ldr r1,=0xFFFFFFFF ;\ + mcr MMU_CP,0,r1,MMU_DomainAccess,c0 ;\ + ldr r2,=10f ;\ + ldr r1,=MMU_Control_Init|MMU_Control_M ;\ + mcr MMU_CP,0,r1,MMU_Control,c0 ;\ + mov pc,r2 /* Change address spaces */ ;\ + nop ;\ + nop ;\ + nop ;\ +10: +#endif + +#define PLATFORM_SETUP1 \ +/* Initialize memory configuration */ ;\ + ldr r1,=MEMCFG1 ;\ + ldr r2,=0x8200A080 /* FIXME - what is this? */ ;\ + str r2,[r1] ;\ + ldr r1,=MEMCFG2 ;\ + ldr r2,=0xFEFC0000 ;\ + str r2,[r1] ;\ + ldr r1,=DRFPR ;\ + ldr r2,=0x81 /* DRAM refresh = 64KHz */ ;\ + strb r2,[r1] ;\ +/* Initialize MMU to create new memory map */ ;\ + ldr r1,=MMU_BASE ;\ + ldr r2,=PTE_BASE ;\ + MAP_DRAM ;\ +/* Nothing until PCMCIA0 */ ;\ + ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\ + add r2,r2,r3 ;\ + ldr r3,=~0x3FF ;\ + and r2,r2,r3 ;\ + ldr r3,=(DRAM_LA_END+0x000FFFFF)&0xFFF00000 ;\ + ldr r4,=EXPANSION2_LA_START ;\ + ldr r5,=MMU_L1_TYPE_Fault ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +10: str r5,[r1],#4 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ +/* EXPANSION2, EXNAPSION3, PCMCIA0, PCMCIA1 */ ;\ + ldr r3,=EXPANSION2_LA_START ;\ + ldr r4,=SRAM_LA_START ;\ + ldr r5,=EXPANSION2_PA ;\ + ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +10: orr r0,r5,r6 ;\ + str r0,[r1],#4 ;\ + add r5,r5,r7 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ +/* SRAM */ ;\ + ldr r3,=SRAM_LA_START ;\ + ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\ + orr r4,r4,r2 ;\ + str r4,[r1],#4 ;\ + ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\ + orr r4,r3,r4 ;\ + str r4,[r2],#4 ;\ + ldr r3,=SRAM_LA_START+MMU_PAGE_SIZE ;\ + ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE ;\ + ldr r5,=MMU_L2_TYPE_Fault ;\ + ldr r7,=MMU_PAGE_SIZE ;\ +10: str r5,[r2],#4 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ + ldr r4,=IO_LA_START ;\ + ldr r5,=MMU_L1_TYPE_Fault ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +20: str r5,[r1],#4 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 20b ;\ +/* I/O */ ;\ + ldr r3,=0x3FF /* Page tables need 2K boundary */ ;\ + add r2,r2,r3 ;\ + ldr r3,=~0x3FF ;\ + and r2,r2,r3 ;\ + ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0) ;\ + orr r4,r4,r2 ;\ + str r4,[r1],#4 ;\ + ldr r3,=IO_LA_START ;\ + ldr r4,=IO_LA_END ;\ + ldr r7,=MMU_PAGE_SIZE ;\ + ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All ;\ +10: str r5,[r2],#4 ;\ + add r5,r5,r7 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ + ldr r4,=IO_LA_START+MMU_SECTION_SIZE ;\ + ldr r5,=MMU_L2_TYPE_Fault ;\ + ldr r7,=MMU_PAGE_SIZE ;\ +10: str r5,[r2],#4 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ + ldr r4,=LCD_LA_START ;\ + ldr r5,=MMU_L1_TYPE_Fault ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +20: str r5,[r1],#4 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 20b ;\ +/* LCD Buffer & Unmapped DRAM (holes and all) */ ;\ + ldr r3,=LCD_LA_START ;\ + ldr r4,=ROM0_LA_START ;\ + ldr r5,=LCD_PA ;\ + ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +10: orr r0,r5,r6 ;\ + str r0,[r1],#4 ;\ + add r5,r5,r7 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ +/* ROM0, ROM1 */ ;\ + ldr r3,=ROM0_LA_START ;\ + ldr r4,=ROM1_LA_END ;\ + ldr r5,=ROM0_PA ;\ + ldr r6,=MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Cacheable ;\ + ldr r7,=MMU_SECTION_SIZE ;\ +10: orr r0,r5,r6 ;\ + str r0,[r1],#4 ;\ + add r5,r5,r7 ;\ + add r3,r3,r7 ;\ + cmp r3,r4 ;\ + bne 10b ;\ +/* Now initialize the MMU to use this new page table */ ;\ + MMU_INITIALIZE + +#else + +#define PLATFORM_SETUP1 +#endif + + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/hal_arm_cl7211.h @@ -0,0 +1,209 @@ +#ifndef CYGONCE_PKGCONF_HAL_ARM_CL7211_H +#define CYGONCE_PKGCONF_HAL_ARM_CL7211_H +// ==================================================================== +// +// pkgconf/hal_arm_cl7211.h +// +// HAL configuration file +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-04-21 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_ARM_CL7211 { + display "Cirrus Logic CLxx11 evaluation boards" + type radio + parent CYGPKG_HAL_ARM + description " + The CLxx11 HAL package provides the support needed to run + eCos on a Cirrus Logic CLxx11-1 eval board." + } + + cdl_option CYGHWR_HAL_ARM_CLxx11_CL7111 { + display "CL7111-1 variant" + parent CYGPKG_HAL_ARM_CL7211 + platform cl7111 + type radio + description " + Cirrus Logic CL7111 board with ARM710C processor." + } + + cdl_option CYGHWR_HAL_ARM_CLxx11_CL7211 { + display "CL7211-1 variant" + parent CYGPKG_HAL_ARM_CL7211 + platform cl7211 + type radio + description " + Cirrus Logic CL7211 board with ARM720 processor." + } + + cdl_option CYGHWR_HAL_ARM_CL7211_STARTUP { + display "Startup type" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values ram rom stubs + startup + description " + When targetting the CLxx11 eval boards it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'rom' + when building a stand-alone application which will be put + into ROM. Selection of 'stubs' is for the special case of + building the eCos GDB stubs themselves." + } + + }}CFG_DATA */ + +#define CYGHWR_HAL_ARM_CL7211_STARTUP ram + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_DIAG_PORT { + display "Diagnostic serial port" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 0 1 + description " + The CLxx11 boards have two separate serial ports. This option + chooses which of these ports will be used." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_DIAG_PORT 0 + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_DIAG_BAUD { + display "Diagnostic serial port baud rate" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 9600 19200 38400 115200 + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_DIAG_BAUD 38400 + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_GDB_PORT { + display "GDB serial port" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 0 1 + description " + The CLxx11 boards have two separate serial ports. This option + chooses which of these ports will be used to connect to a host + running GDB." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_GDB_PORT 0 + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_GDB_BAUD { + display "GDB serial port baud rate" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 9600 19200 38400 115200 + description " + This option controls the baud rate used for the GDB connection." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_GDB_BAUD 38400 + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK { + display "Processor clock rate" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 18432 36864 49152 73728 + description " + The processor on the CL7211 can run at various frequencies." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK 73728 + +/* --------------------------------------------------------------------- + {{CFG_DATA + cdl_option CYGHWR_HAL_ARM_CL7211_DRAM_SIZE { + display "DRAM size" + parent CYGPKG_HAL_ARM_CL7211 + type enum + legal_values 2 16 + description " + The CLxx11 boards can have various amounts of DRAM installed. + The machine needs to be initialized differently, depending + upon the amount installed." + } + + }}CFG_DATA */ +#define CYGHWR_HAL_ARM_CL7211_DRAM_SIZE 16 + +/* ---------------------------------------------------------------------------- + {{CFG_DATA + + cdl_option CYGHWR_HAL_ARM_CL7211_LCD_INSTALLED { + display "LCD panel" + type bool + parent CYGPKG_HAL_ARM_CL7211 + description " + If an LCD panel is installed, 128K of DRAM will be dedicated to the + LCD buffer by the system intialization." + } + + }}CFG_DATA */ +#undef CYGHWR_HAL_ARM_CL7211_LCD_INSTALLED + +// Real-time clock/counter specifics + +#define CYGNUM_HAL_RTC_NUMERATOR 1000000000 +#define CYGNUM_HAL_RTC_DENOMINATOR 100 +#define CYGNUM_HAL_RTC_PERIOD 5120 // Assumes 512KHz clock + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_ARM_CL7211_H */ +/* EOF hal_arm_cl7211.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_ram.ldi @@ -0,0 +1,51 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +// eCos memory layout - Mon May 17 08:04:39 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0x8000, LENGTH = 0x1b8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x8000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_ram.mlt @@ -0,0 +1,11 @@ +version 0 +region ram 8000 1b8000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 8000 8000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 1 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_rom.ldi @@ -0,0 +1,53 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + + +// eCos memory layout - Mon May 17 08:14:13 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0xc0000000, LENGTH = 0x200000 + rom : ORIGIN = 0xe0000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xe0000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0xc0000000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_rom.mlt @@ -0,0 +1,12 @@ +version 0 +region ram c0000000 200000 0 ! +region rom e0000000 40000 1 ! +section data 0 1 1 1 1 1 0 0 c0000000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 e0000000 e0000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_stubs.ldi @@ -0,0 +1,52 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +// eCos memory layout - Mon May 17 08:06:28 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0x1000, LENGTH = 0x7000 + rom : ORIGIN = 0xf0028000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xf0028000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7111_stubs.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 1000 7000 0 ! +region rom f0028000 40000 1 ! +section data 0 1 1 1 1 1 0 0 1000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 f0028000 f0028000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_ram.ldi @@ -0,0 +1,51 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +// eCos memory layout - Mon May 17 08:04:39 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0x8000, LENGTH = 0x1b8000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (ram, 0x8000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_ram.mlt @@ -0,0 +1,11 @@ +version 0 +region ram 8000 1b8000 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 8000 8000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 1 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_rom.ldi @@ -0,0 +1,53 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + + +// eCos memory layout - Mon May 17 08:14:13 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0xc0000000, LENGTH = 0x200000 + rom : ORIGIN = 0xe0000000, LENGTH = 0x40000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xe0000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0xc0000000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_rom.mlt @@ -0,0 +1,12 @@ +version 0 +region ram c0000000 200000 0 ! +region rom e0000000 40000 1 ! +section data 0 1 1 1 1 1 0 0 c0000000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 e0000000 e0000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_stubs.ldi @@ -0,0 +1,52 @@ +//=========================================================================== +// +// MLT linker script export +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +// eCos memory layout - Tue Jun 15 18:13:06 1999 + +// This is a generated file - do not edit + +MEMORY +{ + ram : ORIGIN = 0x1000, LENGTH = 0x7000 + rom : ORIGIN = 0xe0000000, LENGTH = 0x800000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0xe0000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x1000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/pkgconf/mlt_arm_cl7211_stubs.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 1000 7000 0 ! +region rom e0000000 800000 1 !This is ROM bank 0, physical address 0x00000000.When running eCos, this space is remapped to 0xE0000000. +section data 0 1 1 1 1 1 0 0 1000 bss ! +section bss 0 4 0 1 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 e0000000 e0000000 text text ! +section text 0 1 0 1 0 1 0 1 fini fini ! +section fini 0 1 0 1 0 1 0 1 rodata rodata ! +section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 1 0 1 0 1 0 1 fixup fixup ! +section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/include/plf_stub.h @@ -0,0 +1,82 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov, gthomas +// Date: 1999-04-21 +// Purpose: Platform HAL stub support for Cirrus CL7211 boards. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_arm_cl7211.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/arm_stub.h> // architecture stub support + +//---------------------------------------------------------------------------- +// Define serial stuff. + +extern void hal_cl7211_init_serial(void); +extern int hal_cl7211_get_char(void); +extern void hal_cl7211_put_char(int c); +extern int hal_cl7211_interruptible(int); + +#define HAL_STUB_PLATFORM_INIT_SERIAL() hal_cl7211_init_serial() +#define HAL_STUB_PLATFORM_GET_CHAR() hal_cl7211_get_char() +#define HAL_STUB_PLATFORM_PUT_CHAR(c) hal_cl7211_put_char((c)) +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) +#define HAL_STUB_PLATFORM_INTERRUPTIBLE (&hal_cl7211_interruptible) +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Stub initializer. +#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +// Reset. +#define HAL_STUB_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/misc/PKGconf.mak @@ -0,0 +1,57 @@ +#=============================================================================== +# +# makefile +# +# hal/arm/cl7211/misc +# +#=============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#=============================================================================== + +PACKAGE := hal_arm_cl7211 +include ../../../../../pkgconf/pkgconf.mak +include ../../../../../pkgconf/system.mak + +ifdef CYG_HAL_STARTUP_STUBS +PROGS := gdb_module +OTHER_PROGS := gdb_module.img +endif +ifdef CYG_HAL_STARTUP_RAM +PROGS := prog_flash +ifdef CYG_HAL_CL7111 +PROGS += lcd_test +endif +endif +WHEREAMI := misc + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.prv + +ifdef CYG_HAL_STARTUP_STUBS +gdb_module.img: gdb_module.stamp + $(OBJCOPY) --strip-all gdb_module$(EXEEXT) gdb_module.img.XX + $(OBJCOPY) -O binary gdb_module gdb_module.bin + $(RM) -f gdb_module.img.XX +endif + + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/misc/STUBS_config @@ -0,0 +1,36 @@ +#! /bin/sh + +# usage: STUBS_config <repository> [cl7211 | cl7111] + +if [ "$2"x = "x" ]; then + CL7x11="cl7211" +else + CL7x11=$2 +fi + +tcl $1/pkgconf.tcl \ + --target=arm --platform=${CL7x11} --startup=stubs \ + --disable CYGPKG_KERNEL --disable CYGPKG_UITRON \ + --disable CYGPKG_LIBC --disable CYGPKG_LIBM \ + --disable CYGPKG_ERROR --disable CYGPKG_IO \ + --disable CYGPKG_IO_SERIAL --disable CYGPKG_DEVICES_WALLCLOCK \ + --disable CYGPKG_DEVICES_WATCHDOG + +patch <<END_OF_PATCH -p0 +--- pkgconf/hal.h~ Thu Jul 8 08:26:44 1999 ++++ pkgconf/hal.h Wed Jul 28 10:51:07 1999 +@@ -369,10 +369,10 @@ + + }}CFG_DATA */ + +-#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS ++#define CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + #undef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT +-#define CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT ++#undef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + + /* + * NOTE: +END_OF_PATCH
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/misc/gdb_module.c @@ -0,0 +1,64 @@ +//========================================================================== +// +// gdb_module.c +// +// Cirrus CL7211 eval board GDB stubs (module wrapper) +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-05-11 +// Description: Cirrus CL7211 FLASH module for eCos GDB stubs +//####DESCRIPTIONEND#### + +// +// This is the module 'wrapper' for the GDB stubs +// + +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_stub.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +void cyg_start (void) +{ + for(;;) breakpoint(); +} +#else + +#include <cyg/infra/testcase.h> + +void cyg_start (void) +{ + CYG_TEST_INIT(); + CYG_TEST_PASS_FINISH("N/A: Stand-alone GDB stubs only"); +} +#endif + + +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/misc/lcd_test.c @@ -0,0 +1,363 @@ +//========================================================================== +// +// lcd_test.c +// +// Cirrus CL7211 eval board LCD test code +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-05-15 +// Description: Tool used to test LCD controller +//####DESCRIPTIONEND#### + +#include <pkgconf/kernel.h> // Configuration header +#include <cyg/kernel/kapi.h> +#include <cyg/infra/diag.h> + +#include <cyg/hal/hal_cl7211.h> // Board definitions + +#ifndef FALSE +#define FALSE 0 +#define TRUE 1 +#endif + +#define STACK_SIZE 4096 +static char stack[STACK_SIZE]; +static cyg_thread thread_data; +static cyg_handle_t thread_handle; + +// 8x8 Font - from Helios + +#define FIRST_CHAR 0x20 +#define LAST_CHAR 0x7E +#define FONT_HEIGHT 8 +#define FONT_WIDTH 8 +static char font_table[LAST_CHAR-FIRST_CHAR+1][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* */ + { 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x18, 0x00 }, /* ! */ + { 0x36, 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* " */ + { 0x6C, 0x6C, 0xFE, 0x6C, 0xFE, 0x6C, 0x6C, 0x00 }, /* # */ + { 0x30, 0xFC, 0x16, 0x7C, 0xD0, 0x7E, 0x18, 0x00 }, /* $ */ + { 0x06, 0x66, 0x30, 0x18, 0x0C, 0x66, 0x60, 0x00 }, /* % */ + { 0x1C, 0x36, 0x36, 0x1C, 0xB6, 0x66, 0xDC, 0x00 }, /* & */ + { 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ' */ + { 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00 }, /* ( */ + { 0x0C, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0C, 0x00 }, /* ) */ + { 0x00, 0x18, 0x7E, 0x3C, 0x7E, 0x18, 0x00, 0x00 }, /* * */ + { 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00 }, /* + */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x0C }, /* , */ + { 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00 }, /* - */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00 }, /* . */ + { 0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00, 0x00 }, /* / */ + { 0x3C, 0x66, 0x76, 0x7E, 0x6E, 0x66, 0x3C, 0x00 }, /* 0 */ + { 0x18, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00 }, /* 1 */ + { 0x3C, 0x66, 0x60, 0x30, 0x18, 0x0C, 0x7E, 0x00 }, /* 2 */ + { 0x3C, 0x66, 0x60, 0x38, 0x60, 0x66, 0x3C, 0x00 }, /* 3 */ + { 0x30, 0x38, 0x3C, 0x36, 0x7E, 0x30, 0x30, 0x00 }, /* 4 */ + { 0x7E, 0x06, 0x3E, 0x60, 0x60, 0x66, 0x3C, 0x00 }, /* 5 */ + { 0x38, 0x0C, 0x06, 0x3E, 0x66, 0x66, 0x3C, 0x00 }, /* 6 */ + { 0x7E, 0x60, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00 }, /* 7 */ + { 0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C, 0x00 }, /* 8 */ + { 0x3C, 0x66, 0x66, 0x7C, 0x60, 0x30, 0x1C, 0x00 }, /* 9 */ + { 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00 }, /* : */ + { 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x0C }, /* ; */ + { 0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00 }, /* < */ + { 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00 }, /* = */ + { 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00 }, /* > */ + { 0x3C, 0x66, 0x30, 0x18, 0x18, 0x00, 0x18, 0x00 }, /* ? */ + { 0x3C, 0x66, 0x76, 0x56, 0x76, 0x06, 0x3C, 0x00 }, /* @ */ + { 0x3C, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00 }, /* A */ + { 0x3E, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3E, 0x00 }, /* B */ + { 0x3C, 0x66, 0x06, 0x06, 0x06, 0x66, 0x3C, 0x00 }, /* C */ + { 0x1E, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1E, 0x00 }, /* D */ + { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x7E, 0x00 }, /* E */ + { 0x7E, 0x06, 0x06, 0x3E, 0x06, 0x06, 0x06, 0x00 }, /* F */ + { 0x3C, 0x66, 0x06, 0x76, 0x66, 0x66, 0x3C, 0x00 }, /* G */ + { 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66, 0x00 }, /* H */ + { 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00 }, /* I */ + { 0x7C, 0x30, 0x30, 0x30, 0x30, 0x36, 0x1C, 0x00 }, /* J */ + { 0x66, 0x36, 0x1E, 0x0E, 0x1E, 0x36, 0x66, 0x00 }, /* K */ + { 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x7E, 0x00 }, /* L */ + { 0xC6, 0xEE, 0xFE, 0xD6, 0xD6, 0xC6, 0xC6, 0x00 }, /* M */ + { 0x66, 0x66, 0x6E, 0x7E, 0x76, 0x66, 0x66, 0x00 }, /* N */ + { 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* O */ + { 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x06, 0x00 }, /* P */ + { 0x3C, 0x66, 0x66, 0x66, 0x56, 0x36, 0x6C, 0x00 }, /* Q */ + { 0x3E, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x66, 0x00 }, /* R */ + { 0x3C, 0x66, 0x06, 0x3C, 0x60, 0x66, 0x3C, 0x00 }, /* S */ + { 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00 }, /* T */ + { 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* U */ + { 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00 }, /* V */ + { 0xC6, 0xC6, 0xD6, 0xD6, 0xFE, 0xEE, 0xC6, 0x00 }, /* W */ + { 0x66, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x66, 0x00 }, /* X */ + { 0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18, 0x00 }, /* Y */ + { 0x7E, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x7E, 0x00 }, /* Z */ + { 0x3E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x3E, 0x00 }, /* [ */ + { 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00, 0x00 }, /* \ */ + { 0x7C, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7C, 0x00 }, /* ] */ + { 0x3C, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ^ */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF }, /* _ */ + { 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /* ` */ + { 0x00, 0x00, 0x3C, 0x60, 0x7C, 0x66, 0x7C, 0x00 }, /* a */ + { 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x3E, 0x00 }, /* b */ + { 0x00, 0x00, 0x3C, 0x66, 0x06, 0x66, 0x3C, 0x00 }, /* c */ + { 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x00 }, /* d */ + { 0x00, 0x00, 0x3C, 0x66, 0x7E, 0x06, 0x3C, 0x00 }, /* e */ + { 0x38, 0x0C, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x00 }, /* f */ + { 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x3C }, /* g */ + { 0x06, 0x06, 0x3E, 0x66, 0x66, 0x66, 0x66, 0x00 }, /* h */ + { 0x18, 0x00, 0x1C, 0x18, 0x18, 0x18, 0x3C, 0x00 }, /* i */ + { 0x18, 0x00, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x0E }, /* j */ + { 0x06, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x00 }, /* k */ + { 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00 }, /* l */ + { 0x00, 0x00, 0x6C, 0xFE, 0xD6, 0xD6, 0xC6, 0x00 }, /* m */ + { 0x00, 0x00, 0x3E, 0x66, 0x66, 0x66, 0x66, 0x00 }, /* n */ + { 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C, 0x00 }, /* o */ + { 0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x06 }, /* p */ + { 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0xE0 }, /* q */ + { 0x00, 0x00, 0x36, 0x6E, 0x06, 0x06, 0x06, 0x00 }, /* r */ + { 0x00, 0x00, 0x7C, 0x06, 0x3C, 0x60, 0x3E, 0x00 }, /* s */ + { 0x0C, 0x0C, 0x3E, 0x0C, 0x0C, 0x0C, 0x38, 0x00 }, /* t */ + { 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x7C, 0x00 }, /* u */ + { 0x00, 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x00 }, /* v */ + { 0x00, 0x00, 0xC6, 0xD6, 0xD6, 0xFE, 0x6C, 0x00 }, /* w */ + { 0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66, 0x00 }, /* x */ + { 0x00, 0x00, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x3C }, /* y */ + { 0x00, 0x00, 0x7E, 0x30, 0x18, 0x0C, 0x7E, 0x00 }, /* z */ + { 0x30, 0x18, 0x18, 0x0E, 0x18, 0x18, 0x30, 0x00 }, /* { */ + { 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00 }, /* | */ + { 0x0C, 0x18, 0x18, 0x70, 0x18, 0x18, 0x0C, 0x00 }, /* } */ + { 0x8C, 0xD6, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00 } /* ~ */ +}; + +// Physical screen info +int lcd_depth; // Should be 1, 2, or 4 +int lcd_width = 320; +int lcd_height = 240; +cyg_uint8 *lcd_base = 0xC0000000; + +// Virtual screen info +int curX = 0; // Last used position +int curY = 0; +int width = 320 / FONT_WIDTH; +int height = 240 / FONT_HEIGHT; +int fg = 0x0F; +int bg = 0x00; + +// FUNCTIONS + +static void +cyg_test_exit(void) +{ + while (TRUE) ; +} + +void +lcd_on(int depth) +{ + cyg_int32 ctl_word; + lcd_depth = depth; + switch (depth) { + case 1: + *(volatile cyg_int32 *)PALLSW = 0xF0F0F0F0; + *(volatile cyg_int32 *)PALMSW = 0xF0F0F0F0; + ctl_word = 0; + break; + case 2: + *(volatile cyg_int32 *)PALLSW = 0xFA50FA50; + *(volatile cyg_int32 *)PALMSW = 0xFA50FA50; + ctl_word = LCDCON_GSEN; + break; + case 4: + *(volatile cyg_int32 *)PALLSW = 0x76543210; + *(volatile cyg_int32 *)PALMSW = 0xFEDCBA98; + ctl_word = LCDCON_GSEN | LCDCON_GSMD; + break; + } + // Video buffer size + ctl_word |= ((lcd_width * lcd_height * lcd_depth) / 128 - 1) << LCDCON_BUFSIZ_S; + // Line length + ctl_word |= ((lcd_width / 16) - 1) << LCDCON_LINE_LENGTH_S; + // Pixel prescale + ctl_word |= ((526628 / (lcd_height * lcd_width)) - 1) << LCDCON_PIX_PRESCALE_S; + // AC frequency bias + ctl_word |= 0 << LCDCON_AC_PRESCALE_S; + *(volatile cyg_int32 *)LCDCON = ctl_word; + diag_printf("Depth: %d, ctl: %x\n", depth, ctl_word); + + *(volatile cyg_uint8 *)PDDR = 0x20; // Enable video + *(volatile cyg_uint8 *)PEDDR = 0x0F; // Register E data direction + *(volatile cyg_uint8 *)PEDR |= 0x01; // Enable PE2 + + *(volatile cyg_uint32 *)PMPCON = 0x500; // Enable DC-to-DC pump #1 + + *(volatile cyg_uint8 *)FRBADDR = 0x0C; // Highest order nibble of LCD frame address + + *(volatile cyg_uint32 *)SYSCON1 |= SYSCON1_LCDEN; +} + +// Clear screen +static void +lcd_clear(void) +{ + cyg_int8 *ptr = lcd_base; + int i; + for (i = 0; i < (lcd_width*lcd_height*lcd_depth)/8; i++) { + *ptr++ = 0; + } + curX = 0; curY = 0; +} + +// Render a character at position (X,Y) with current background/foreground +static void +lcd_drawc(cyg_int8 c, int x, int y) +{ + // Note: this only works for fonts which are a multiple of 8 bits wide! + cyg_uint8 *bufptr, bits; + int l, p; + switch (lcd_depth) { + case 1: + bufptr = lcd_base + ((y * FONT_HEIGHT * (lcd_width*lcd_depth)) + (x * FONT_WIDTH)) / 8; + for (l = 0; l < FONT_HEIGHT; l++) { + *bufptr = font_table[c][l]; + bufptr += (lcd_width*lcd_depth)/8; + } + break; + case 2: + diag_printf("Depth 2 not implemented\n"); + break; + case 4: + bufptr = lcd_base + ((y * FONT_HEIGHT * (lcd_width*lcd_depth)) + (x * FONT_WIDTH * lcd_depth)) / 8; + for (l = 0; l < FONT_HEIGHT; l++) { + bits = font_table[c][l]; + for (p = 0; p < 8; p += 2) { +// switch ((bits>>6) & 0x03) { + switch (bits & 0x03) { + case 0: + *bufptr++ = (bg << 4) | bg; + break; + case 1: + *bufptr++ = (bg << 4) | fg; + break; + case 2: + *bufptr++ = (fg << 4) | bg; + break; + case 3: + *bufptr++ = (fg << 4) | fg; + break; + } + bits >>= 2; +// bits <<= 2; + } + bufptr += (lcd_width*lcd_depth)/8 - 4;; + } + break; + } +} + +static void +lcd_putc(cyg_int8 c) +{ + switch (c) { + case '\r': + curX = 0; + break; + case '\n': + curY++; + break; + case '\b': + curX--; + if (curX < 0) { + curY--; + if (curY < 0) curY = 0; + curX = width-1; + } + default: + lcd_drawc(c, curX, curY); + curX++; + if (curX == width) { + curY++; + curX = 0; + } + } +} + +static void +lcd_test(int depth) +{ + int i, j; + diag_printf("Set depth %d\n", depth); + lcd_on(depth); + lcd_clear(); + for (j = 0; j < 5; j++) { + for (i = 0; i < width; i++) { + lcd_putc('A'); + } + } + lcd_putc('\n'); + lcd_putc('\n'); + cyg_thread_delay(5*100); + for (j = 0; j < 5; j++) { + for (i = FIRST_CHAR; i <= LAST_CHAR; i++) { + lcd_putc(i); + } + } + cyg_thread_delay(5*100); +} + +static void +lcd_exercise(void) +{ + diag_printf("LCD test here!\n"); + + lcd_test(1); +// lcd_test(2); + lcd_test(4); + + diag_printf("All done!\n"); + cyg_test_exit(); +} + +externC void +cyg_start( void ) +{ + // Create a main thread, so we can run the scheduler and have time 'pass' + cyg_thread_create(10, // Priority - just a number + lcd_exercise, // entry + 1, // index + "LCD_test_thread", // Name + &stack[0], // Stack + STACK_SIZE, // Size + &thread_handle, // Handle + &thread_data // Thread data structure + ); + cyg_thread_resume(thread_handle); // Start it + cyg_scheduler_start(); +} // cyg_package_start() +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/misc/prog_flash.c @@ -0,0 +1,312 @@ +//========================================================================== +// +// prog_flash.c +// +// Cirrus CL7211 eval board FLASH program tool +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-05-12 +// Description: Tool used to program onboard FLASH image +//####DESCRIPTIONEND#### + +// +// This program will program the FLASH on the CL7211 board from a fixed buffer +// + +#include <pkgconf/kernel.h> // Configuration header +#include <cyg/kernel/kapi.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> + +#ifndef FALSE +#define FALSE 0 +#define TRUE 1 +#endif + +#define STACK_SIZE 4096 +static char stack[STACK_SIZE]; +static cyg_thread thread_data; +static cyg_handle_t thread_handle; + +void identify_FLASH(void); +int write_flash(long *data, volatile long *mem); +int erase_sector(volatile long *mem); + +// Note: these are mapped addresses +// 0xE0000000 = ROM Bank 0 +// 0xF0000000 = ROM Bank 1 +volatile unsigned long *FLASH = (volatile unsigned long *)0xE0000000; + +long *flash_buffer = (long *)0x60000; +long *flash_buffer_end = (long *)0x64000; +long *ROM_address = (long *)0xE07E0000; + +// Adapted from Cirrus sample code +#define ATMEL_SEQ_ADD1 0x00015554>>2 +#define ATMEL_SEQ_ADD2 0x0000AAA8>>2 +#define ATMEL_START_CMD1 0xAAAAAAAA +#define ATMEL_START_CMD2 0x55555555 +#define ATMEL_ID_CMD 0x90909090 +#define ATMEL_PROG_CMD 0xA0A0A0A0 +#define ATMEL_ERASE_CMD 0x80808080 +#define ATMEL_SECTOR_ERASE_CMD 0x30303030 +#define ATMEL_STOP_CMD 0xF0F0F0F0 +#define ATMEL_BUSY_TOGGLE 0x00400040 +#define ATMEL_ERASE_TOGGLE 0x00440044 + +#define ATMEL_MANUF 0x1F +#define ATMEL_AT29C040_ID 0X5B +#define ATMEL_AT29C040A_ID 0XA4 +#define ATMEL_AT29C1024_ID 0X25 +#define ATMEL_SECTOR_SIZE 256 +#define ATMEL_MAX_SECTORS 2048 + +#define INTEL_MANUF 0x0089 +#define INTEL_STOP_CMD 0x00FF00FF +#define INTEL_PROG_CMD 0x00400040 +#define INTEL_ERASE_CMD 0x00200020 +#define INTEL_ERASE_CONFIRM 0x00D000D0 +#define INTEL_READ_STATUS 0x00700070 +#define INTEL_CLEAR_STATUS 0x00500050 +#define INTEL_SB_WSMS 0x00800080 // Write state machine = ready +#define INTEL_SB_ERASE_ERROR 0x00200020 // Erase failure +#define INTEL_SB_PROG_ERROR 0x00100010 // Programming failure + +#define ERASE_TIMEOUT 10 // seconds + +int manuf_code, device_code, sector_size, max_no_of_sectors, word_mode; + +// FUNCTIONS + +static void +cyg_test_exit(void) +{ + while (TRUE) ; +} + +static void +program_flash(void) +{ + diag_printf("PROGRAM FLASH here!\n"); + HAL_UCACHE_SYNC(); // ROM space is marked cacheable which causes problems! + HAL_UCACHE_DISABLE(); // So, just disable caches. + identify_FLASH(); + diag_printf("About to program FLASH using data at %x..%x\n", flash_buffer, flash_buffer_end); + diag_printf("*** Press RESET now to abort!\n"); + cyg_thread_delay(5*100); + diag_printf("\n"); + diag_printf("... Erase sector\n"); + if (erase_sector(ROM_address)) { + diag_printf("... Programming FLASH\n"); + while (flash_buffer < flash_buffer_end) { + if (!write_flash(flash_buffer++, ROM_address++)) break; + } + } + + // Exit Program Mode + switch (manuf_code) { + case ATMEL_MANUF: + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_STOP_CMD; + break; + case INTEL_MANUF: + FLASH[0] = INTEL_STOP_CMD; + break; + } + diag_printf("All done!\n"); + cyg_test_exit(); +} + +void +identify_FLASH(void ) +{ + // Enter Software Product Identification Mode + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_ID_CMD; + + // Wait at least 10ms + cyg_thread_delay(2); + + // Read Manufacturer and device code from the device + manuf_code = FLASH[0] >> 16; + device_code = FLASH[1] >> 16; + + diag_printf("manufacturer: 0x%04x, device: 0x%04x\n", manuf_code, device_code); + + // Exit Software Product Identification Mode + switch (manuf_code) { + case ATMEL_MANUF: + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_STOP_CMD; + break; + case INTEL_MANUF: + FLASH[0] = INTEL_STOP_CMD; + break; + default: + diag_printf("Unrecognized FLASH manufacturer - I give up!\n"); + cyg_test_exit(); + } +} + +void +spin(void) +{ + volatile int i; + for (i = 0; i < 100; i++) ; +} + +int +write_flash(long *data, volatile long *mem) +{ + long data1, data2; + long status; + int timer; + switch (manuf_code) { + case ATMEL_MANUF: + // Enter Program Mode + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_PROG_CMD; + // Send data to selected address + *mem = *data; + while (TRUE) { + data1 = *mem; // Read cell back twice + data2 = *mem; + // Bit 6 toggles between reads while programming in progress + if ((data1 & ATMEL_BUSY_TOGGLE) == (data2 & ATMEL_BUSY_TOGGLE)) break; + } + break; + case INTEL_MANUF: + // Clear current errors + FLASH[0] = INTEL_CLEAR_STATUS; + // Issue program command + FLASH[0] = INTEL_PROG_CMD; + // Send data to selected address + *mem = *data; + timer = 10000; + // Read the status register to wait for programming complete + do { + spin(); + status = FLASH[0]; + } while (((status & INTEL_SB_WSMS) != INTEL_SB_WSMS) && + (--timer > 0)); + // Check for errors + if (timer == 0) { + diag_printf("Programming at 0x%08x timed out - status: 0x%08x\n", mem, status); + } + if ((status & INTEL_SB_PROG_ERROR) != 0) { + diag_printf("Device reports programming error at 0x%08x - status: 0x%08x\n", mem, status); + } + // Exit program mode + FLASH[0] = INTEL_STOP_CMD; + break; + } + if (*mem != *data) { + diag_printf("Programming failed at 0x%08x - write: 0x%08x, read: 0x%08x\n", + mem, *data, *mem); + return (FALSE); + } + return (TRUE); +} + +int +erase_sector(volatile long *mem) +{ + long data1, data2; + long status; + int timer; + switch (manuf_code) { + case ATMEL_MANUF: + // Erase sector command + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_ERASE_CMD; + FLASH[ATMEL_SEQ_ADD1] = ATMEL_START_CMD1; + FLASH[ATMEL_SEQ_ADD2] = ATMEL_START_CMD2; + *mem = ATMEL_SECTOR_ERASE_CMD; + while (TRUE) { + data1 = *mem; // Read cell back twice + data2 = *mem; + // Bits 6+2 toggle between reads while programming in progress + if ((data1 & ATMEL_ERASE_TOGGLE) == (data2 & ATMEL_ERASE_TOGGLE)) break; + } + break; + case INTEL_MANUF: + // Clear current errors + FLASH[0] = INTEL_CLEAR_STATUS; + // Issue erase block command + FLASH[0] = INTEL_ERASE_CMD; + *mem = INTEL_ERASE_CONFIRM; + timer = ERASE_TIMEOUT*50; + // Read the status register while erase in progress + do { + cyg_thread_delay(2); + status = FLASH[0]; + } while (((status & INTEL_SB_WSMS) != INTEL_SB_WSMS) && + (--timer > 0)); + // Check for errors + if (timer == 0) { + diag_printf("Erase not complete after %d seconds - status: 0x%08x\n", + ERASE_TIMEOUT, status); + } + if ((status & INTEL_SB_ERASE_ERROR) != 0) { + diag_printf("Device reports erase error - status: 0x%08x\n", status); + } + // Exit erase mode + FLASH[0] = INTEL_STOP_CMD; + break; + } + if (*mem != 0xFFFFFFFF) { + diag_printf("Erase failed at 0x%08x - read: 0x%08x\n", + mem, *mem); + return (FALSE); + } + return (TRUE); +} + +externC void +cyg_start( void ) +{ + // Create a main thread, so we can run the scheduler and have time 'pass' + cyg_thread_create(10, // Priority - just a number + program_flash, // entry + 1, // index + "program_thread", // Name + &stack[0], // Stack + STACK_SIZE, // Size + &thread_handle, // Handle + &thread_data // Thread data structure + ); + cyg_thread_resume(thread_handle); // Start it + cyg_scheduler_start(); +} // cyg_package_start() +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/src/PKGconf.mak @@ -0,0 +1,41 @@ +#============================================================================== +# +# makefile +# +# hal/arm/cl7211/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_arm_cl7211 +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := hal_diag.c plf_stub.c cl7211_misc.c +OTHER_OBJS := +OTHER_TARGETS := +OTHER_CLEAN := +OTHER_DEPS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/src/cl7211_misc.c @@ -0,0 +1,336 @@ +//========================================================================== +// +// cl7211_misc.c +// +// HAL misc board support code for ARM CL7211-1 +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-20 +// Purpose: HAL board support +// Description: Implementations of HAL board interfaces +// +//####DESCRIPTIONEND#### +// +//========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_cl7211.h> // Hardware definitions + +#define CYGHWR_HAL_ARM_CL7211_BATLOW +#ifdef CYGHWR_HAL_ARM_CL7211_BATLOW +#include <cyg/hal/hal_intr.h> // HAL interrupt macros +#include <cyg/hal/drv_api.h> // HAL ISR support +static cyg_interrupt batlow_interrupt; +static cyg_handle_t batlow_interrupt_handle; +#endif + +#if (CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK == 18432) +#define CPU_CLOCK 0 +#elif (CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK == 36864) +#define CPU_CLOCK 1 +#elif (CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK == 49152) +#define CPU_CLOCK 2 +#elif (CYGHWR_HAL_ARM_CL7211_PROCESSOR_CLOCK == 73728) +#define CPU_CLOCK 3 +#else +#err Invalid CPU clock frequency +#endif + +static cyg_uint32 _period; + +// Use Timer/Counter #2 for system clock + +void hal_clock_initialize(cyg_uint32 period) +{ + volatile cyg_uint32 *syscon1 = (volatile cyg_uint32 *)SYSCON1; + volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D; + // Set timer to 512KHz, prescale mode + *syscon1 = (*syscon1 & ~(SYSCON1_TC2M|SYSCON1_TC2S)) | SYSCON1_TC2S | SYSCON1_TC2M; + // Initialize counter + *tc2d = period; + _period = period; +} + +// This routine is called during a clock interrupt. + +void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period) +{ + volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D; + if (period != _period) { + *tc2d = period; + _period = period; + } +} + +// Read the current value of the clock, returning the number of hardware "ticks" +// that have occurred (i.e. how far away the current value is from the start) + +void hal_clock_read(cyg_uint32 *pvalue) +{ + volatile cyg_int32 *tc2d = (volatile cyg_int32 *)TC2D; + static cyg_int32 clock_val; + clock_val = *tc2d & 0x0000FFFF; // Register has only 16 bits + if (clock_val & 0x00008000) clock_val |= 0xFFFF8000; // Extend sign bit + *pvalue = (cyg_uint32)(_period - clock_val); // 'clock_val' counts down and wraps +} + +// These tables map the various [soft] interrupt numbers onto the hardware + +static cyg_uint32 hal_interrupt_bitmap[] = { + 0, // CYGNUM_HAL_INTERRUPT_unused 0 + INTSR1_EXTFIQ, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1 + INTSR1_BLINT, // CYGNUM_HAL_INTERRUPT_BLINT 2 + INTSR1_WEINT, // CYGNUM_HAL_INTERRUPT_WEINT 3 + INTSR1_MCINT, // CYGNUM_HAL_INTERRUPT_MCINT 4 + INTSR1_CSINT, // CYGNUM_HAL_INTERRUPT_CSINT 5 + INTSR1_EINT1, // CYGNUM_HAL_INTERRUPT_EINT1 6 + INTSR1_EINT2, // CYGNUM_HAL_INTERRUPT_EINT2 7 + INTSR1_EINT3, // CYGNUM_HAL_INTERRUPT_EINT3 8 + INTSR1_TC1OI, // CYGNUM_HAL_INTERRUPT_TC1OI 9 + INTSR1_TC2OI, // CYGNUM_HAL_INTERRUPT_TC2OI 10 + INTSR1_RTCMI, // CYGNUM_HAL_INTERRUPT_RTCMI 11 + INTSR1_TINT, // CYGNUM_HAL_INTERRUPT_TINT 12 + INTSR1_UTXINT1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13 + INTSR1_URXINT1, // CYGNUM_HAL_INTERRUPT_URXINT1 14 + INTSR1_UMSINT, // CYGNUM_HAL_INTERRUPT_UMSINT 15 + INTSR1_SSEOTI, // CYGNUM_HAL_INTERRUPT_SSEOTI 16 + INTSR2_KBDINT, // CYGNUM_HAL_INTERRUPT_KBDINT 17 + INTSR2_SS2RX, // CYGNUM_HAL_INTERRUPT_SS2RX 18 + INTSR2_SS2TX, // CYGNUM_HAL_INTERRUPT_SS2TX 19 + INTSR2_UTXINT2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20 + INTSR2_URXINT2, // CYGNUM_HAL_INTERRUPT_URXINT2 21 +#if defined(__CL7211) + INTSR3_MCPINT // CYGNUM_HAL_INTERRUPT_MCPINT 22 +#endif +}; + +static cyg_uint32 hal_interrupt_mask_regmap[] = { + 0, // CYGNUM_HAL_INTERRUPT_unused 0 + INTMR1, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1 + INTMR1, // CYGNUM_HAL_INTERRUPT_BLINT 2 + INTMR1, // CYGNUM_HAL_INTERRUPT_WEINT 3 + INTMR1, // CYGNUM_HAL_INTERRUPT_MCINT 4 + INTMR1, // CYGNUM_HAL_INTERRUPT_CSINT 5 + INTMR1, // CYGNUM_HAL_INTERRUPT_EINT1 6 + INTMR1, // CYGNUM_HAL_INTERRUPT_EINT2 7 + INTMR1, // CYGNUM_HAL_INTERRUPT_EINT3 8 + INTMR1, // CYGNUM_HAL_INTERRUPT_TC1OI 9 + INTMR1, // CYGNUM_HAL_INTERRUPT_TC2OI 10 + INTMR1, // CYGNUM_HAL_INTERRUPT_RTCMI 11 + INTMR1, // CYGNUM_HAL_INTERRUPT_TINT 12 + INTMR1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13 + INTMR1, // CYGNUM_HAL_INTERRUPT_URXINT1 14 + INTMR1, // CYGNUM_HAL_INTERRUPT_UMSINT 15 + INTMR1, // CYGNUM_HAL_INTERRUPT_SSEOTI 16 + INTMR2, // CYGNUM_HAL_INTERRUPT_KBDINT 17 + INTMR2, // CYGNUM_HAL_INTERRUPT_SS2RX 18 + INTMR2, // CYGNUM_HAL_INTERRUPT_SS2TX 19 + INTMR2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20 + INTMR2, // CYGNUM_HAL_INTERRUPT_URXINT2 21 +#if defined(__CL7211) + INTMR3, // CYGNUM_HAL_INTERRUPT_MCPINT 22 +#endif +}; + +static cyg_uint32 hal_interrupt_clear_map[] = { + 0, // CYGNUM_HAL_INTERRUPT_unused 0 + 0, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1 + BLEOI, // CYGNUM_HAL_INTERRUPT_BLINT 2 + TEOI, // CYGNUM_HAL_INTERRUPT_WEINT 3 + MCEOI, // CYGNUM_HAL_INTERRUPT_MCINT 4 + COEOI, // CYGNUM_HAL_INTERRUPT_CSINT 5 + 0, // CYGNUM_HAL_INTERRUPT_EINT1 6 + 0, // CYGNUM_HAL_INTERRUPT_EINT2 7 + 0, // CYGNUM_HAL_INTERRUPT_EINT3 8 + TC1EOI, // CYGNUM_HAL_INTERRUPT_TC1OI 9 + TC2EOI, // CYGNUM_HAL_INTERRUPT_TC2OI 10 + RTCEOI, // CYGNUM_HAL_INTERRUPT_RTCMI 11 + TEOI, // CYGNUM_HAL_INTERRUPT_TINT 12 + 0, // CYGNUM_HAL_INTERRUPT_UTXINT1 13 + 0, // CYGNUM_HAL_INTERRUPT_URXINT1 14 + UMSEOI, // CYGNUM_HAL_INTERRUPT_UMSINT 15 + 0, // CYGNUM_HAL_INTERRUPT_SSEOTI 16 + 0, // CYGNUM_HAL_INTERRUPT_KBDINT 17 + 0, // CYGNUM_HAL_INTERRUPT_SS2RX 18 + 0, // CYGNUM_HAL_INTERRUPT_SS2TX 19 + 0, // CYGNUM_HAL_INTERRUPT_UTXINT2 20 + 0, // CYGNUM_HAL_INTERRUPT_URXINT2 21 +#if defined(__CL7211) + 0, // CYGNUM_HAL_INTERRUPT_MCPINT 22 +#endif +}; + +static struct regmap { + int first_int, last_int; + cyg_uint32 stat_reg, mask_reg; +} hal_interrupt_status_regmap[] = { + { CYGNUM_HAL_INTERRUPT_EXTFIQ, CYGNUM_HAL_INTERRUPT_SSEOTI, INTSR1, INTMR1}, + { CYGNUM_HAL_INTERRUPT_KBDINT, CYGNUM_HAL_INTERRUPT_URXINT2, INTSR2, INTMR2}, +#if defined(__CL7211) + { CYGNUM_HAL_INTERRUPT_MCPINT, CYGNUM_HAL_INTERRUPT_MCPINT, INTSR3, INTMR3}, +#endif + { 0, 0, 0} +}; + +#ifdef CYGHWR_HAL_ARM_CL7211_BATLOW +// This ISR is called when the battery low interrupt occurs +int +cyg_hal_batlow_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) +{ + diag_printf("Battery low\n"); + cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_BLINT); + // Presumably, one would leave this masked until the battery changed + cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_BLINT); + return 0; // No need to run DSR +} +#endif + +// +// Early stage hardware initialization +// Some initialization has already been done before we get here. For now +// just set up the interrupt environment. + +void hal_hardware_init(void) +{ + volatile cyg_uint32 *icr; + int vector; + // Clear and initialize instruction cache + HAL_ICACHE_INVALIDATE_ALL(); + HAL_ICACHE_ENABLE(); + // Any hardware/platform initialization that needs to be done. +#if 0 + diag_printf("IMR1: %04x, IMR2: %04x\n", + *(volatile cyg_uint32 *)INTMR1, + *(volatile cyg_uint32 *)INTMR2); + diag_printf("Memcfg1: %08x, Memcfg2: %08x, DRAM refresh: %08x\n", + *(volatile cyg_uint32 *)MEMCFG1, + *(volatile cyg_uint32 *)MEMCFG2, + *(volatile cyg_uint8 *)DRFPR); +#endif + // Reset all interrupt masks (disable all interrupt sources) + *(volatile cyg_uint32 *)INTMR1 = 0; + *(volatile cyg_uint32 *)INTMR2 = 0; +#if defined(__CL7211) + *(volatile cyg_uint32 *)INTMR3 = 0; + *(volatile cyg_uint8 *)SYSCON3 = SYSCON3_CLKCTL(CPU_CLOCK); +#endif + for (vector = CYGNUM_HAL_ISR_MIN; vector < CYGNUM_HAL_ISR_COUNT; vector++) { + icr = (volatile cyg_uint32 *)hal_interrupt_clear_map[vector]; + if (icr) *icr = 0; // Just a write clears the latch + } + // Turn on the DIAG LED to let the world know the board is alive + *(volatile unsigned char *)LEDFLSH = LEDFLSH_ENABLE|LEDFLSH_DUTY(16)|LEDFLSH_PERIOD(1); +#ifdef CYGHWR_HAL_ARM_CL7211_BATLOW + cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_BLINT, + 99, // Priority - what goes here? + 0, // Data item passed to interrupt handler + cyg_hal_batlow_isr, + 0, + &batlow_interrupt_handle, + &batlow_interrupt); + cyg_drv_interrupt_attach(batlow_interrupt_handle); + cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_BLINT); +#endif +} + +// +// This routine is called to respond to a hardware interrupt (IRQ). It +// should interrogate the hardware and return the IRQ vector number. + +// This code is a little convoluted to keep it general while still avoiding +// reading the hardware a lot, since the interrupt status is split across +// three separate registers. + +int hal_IRQ_handler(void) +{ + struct regmap *map = hal_interrupt_status_regmap; + cyg_uint32 stat; + int vector; + while (map->first_int) { + stat = *(volatile cyg_uint32 *)map->stat_reg & *(volatile cyg_uint32 *)map->mask_reg; + for (vector = map->first_int; vector <= map->last_int; vector++) { + if (stat & hal_interrupt_bitmap[vector]) return vector; + } + map++; // Next interrupt status register + } + return CYGNUM_HAL_INTERRUPT_unused; // This shouldn't happen! +} + +// +// Interrupt control +// + +void hal_interrupt_mask(int vector) +{ + volatile cyg_uint32 *imr; + imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector]; + *imr &= ~hal_interrupt_bitmap[vector]; +} + +void hal_interrupt_unmask(int vector) +{ + volatile cyg_uint32 *imr; + imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector]; + *imr |= hal_interrupt_bitmap[vector]; +} + +void hal_interrupt_acknowledge(int vector) +{ + // Some interrupt sources have a register for this. + volatile cyg_uint32 *icr; + icr = (volatile cyg_uint32 *)hal_interrupt_clear_map[vector]; + if (icr) { + *icr = 0; // Any data clears interrupt + } +} + +void hal_interrupt_configure(int vector, int level, int up) +{ + // No interrupts are configurable on this hardware +} + +void hal_interrupt_set_level(int vector, int level) +{ + // No interrupts are configurable on this hardware +} + +/*------------------------------------------------------------------------*/ +// EOF hal_misc.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/src/hal_diag.c @@ -0,0 +1,261 @@ +/*============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg, gthomas +// Contributors:nickg, gthomas +// Date: 1998-03-02 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//===========================================================================*/ + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_arch.h> // basic machine info +#include <cyg/hal/hal_intr.h> // interrupt macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/drv_api.h> +#endif +#include <cyg/hal/hal_cl7211.h> // Hardware definitions + +#if CYGHWR_HAL_ARM_CL7211_DIAG_PORT == 0 +#define CYG_DIAG_DEV_DATA UARTDR1 +#define CYG_DIAG_DEV_BLCR UBLCR1 +#define CYG_DIAG_DEV_STAT SYSFLG1 +#define CYG_DIAG_DEV_CTRL SYSCON1 +#define CYG_DIAG_DEV_INT CYGNUM_HAL_INTERRUPT_URXINT1 +#else +#define CYG_DIAG_DEV_DATA UARTDR2 +#define CYG_DIAG_DEV_STAT SYSFLG2 +#define CYG_DIAG_DEV_CTRL SYSCON2 +#define CYG_DIAG_DEV_BLCR UBLCR2 +#define CYG_DIAG_DEV_INT CYGNUM_HAL_INTERRUPT_URXINT2 +#endif + +// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e. +// totally stand-alone) system. + +#ifdef CYG_HAL_STARTUP_STUBS +#define CYG_HAL_STARTUP_ROM +#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#endif + +#if defined(CYG_HAL_STARTUP_ROM) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#define HAL_DIAG_USES_HARDWARE +#else +#if CYGHWR_HAL_ARM_CL7211_DIAG_PORT != CYGHWR_HAL_ARM_CL7211_GDB_PORT +#define HAL_DIAG_USES_HARDWARE +#endif +#endif + +/*---------------------------------------------------------------------------*/ +// CL7211 Serial Port (UARTx) for Debug + +// Actually send character down the wire +static void +hal_diag_write_char_serial(char c) +{ + cyg_uint32 stat; + // Wait for Tx FIFO not full + do { + stat = *(volatile cyg_uint32 *)CYG_DIAG_DEV_STAT; + } while ((stat & SYSFLG1_UTXFF1) != 0) ; + *(volatile cyg_uint8 *)CYG_DIAG_DEV_DATA = c; +} + +static bool +hal_diag_read_serial(char *c) +{ + long timeout = 1000000000; // A long time... + cyg_uint32 stat, val; + + do { + stat = *(volatile cyg_uint32 *)CYG_DIAG_DEV_STAT; + if (--timeout == 0) return false; + } while ((stat & SYSFLG1_URXFE1) != 0); + // Need to read 32 bits + val = *(volatile cyg_uint32 *)CYG_DIAG_DEV_DATA & 0xFF; + *c = val; + return true; +} + +#ifdef HAL_DIAG_USES_HARDWARE + +void hal_diag_init(void) +{ + static int init = 0; +#ifndef CYG_HAL_STARTUP_ROM + char *msg = "\n\rRAM CL7211 eCos\n\r"; +#endif + if (init++) return; + + // Enable port + *(volatile cyg_uint32 *)CYG_DIAG_DEV_CTRL |= SYSCON1_UART1EN; + // Configure + *(volatile cyg_uint32 *)CYG_DIAG_DEV_BLCR = + UART_BITRATE(CYGHWR_HAL_ARM_CL7211_DIAG_BAUD) | + UBLCR_FIFOEN | UBLCR_WRDLEN8; +#ifndef CYG_HAL_STARTUP_ROM + while (*msg) hal_diag_write_char(*msg++); +#endif +} + +#ifndef CYG_HAL_STARTUP_ROM +#define DIAG_BUFSIZE 2048 +static char diag_buffer[DIAG_BUFSIZE]; +static int diag_bp = 0; +#endif + +void hal_diag_write_char(char c) +{ + hal_diag_init(); +#ifndef CYG_HAL_STARTUP_ROM + diag_buffer[diag_bp++] = c; + if (diag_bp == sizeof(diag_buffer)) diag_bp = 0; +#endif + hal_diag_write_char_serial(c); +} + +void hal_diag_read_char(char *c) +{ + while (!hal_diag_read_serial(c)) ; +} + +#else // HAL_DIAG relies on GDB + +// Initialize diag port +void hal_diag_init(void) +{ +#if 0 // Assume port is already setup + // Enable port + *(volatile cyg_uint32 *)CYG_DIAG_DEV_CTRL |= SYSCON1_UART1EN; + // Configure + *(volatile cyg_uint32 *)CYG_DIAG_DEV_BLCR = + UART_BITRATE(CYGHWR_HAL_ARM_CL7211_DIAG_BAUD) | + UBLCR_FIFOEN | UBLCR_WRDLEN8; +#endif +} + +void +hal_diag_read_char(char *c) +{ + while (!hal_diag_read_serial(c)) ; +} + +void +hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + + HAL_DISABLE_INTERRUPTS(old); + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + if (!hal_diag_read_serial(&c1)) + continue; // No response - try sending packet again + + if( c1 == '+' ) + break; // a good acknowledge + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + cyg_drv_interrupt_acknowledge(CYG_DIAG_DEV_INT); + if( c1 == 3 ) { + // Ctrl-C: breakpoint. + cyg_hal_gdb_interrupt (__builtin_return_address(0)); + break; + } +#endif + // otherwise, loop round again + } + + pos = 0; + + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS(old); + + } +} +#endif + +/*---------------------------------------------------------------------------*/ +/* End of hal_diag.c */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/src/plf_stub.c @@ -0,0 +1,157 @@ +//============================================================================= +// +// plf_stub.c +// +// Platform specific code for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors:gthomas, jskov +// Date: 1999-04-21 +// Purpose: Platform specific code for GDB stub support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/hal/hal_stub.h> + +#include <cyg/hal/hal_io.h> // HAL IO macros +#include <cyg/hal/hal_cl7211.h> // Hardware definitions +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/hal_intr.h> // HAL interrupt macros +#include <cyg/hal/drv_api.h> // HAL ISR support +#endif + +#if CYGHWR_HAL_ARM_CL7211_GDB_PORT == 0 +#define CYG_GDB_DEV_DATA UARTDR1 +#define CYG_GDB_DEV_BLCR UBLCR1 +#define CYG_GDB_DEV_STAT SYSFLG1 +#define CYG_GDB_DEV_CTRL SYSCON1 +#define CYG_GDB_DEV_INT CYGNUM_HAL_INTERRUPT_URXINT1 +#else +#define CYG_GDB_DEV_DATA UARTDR2 +#define CYG_GDB_DEV_STAT SYSFLG2 +#define CYG_GDB_DEV_CTRL SYSCON2 +#define CYG_GDB_DEV_BLCR UBLCR2 +#define CYG_GDB_DEV_INT CYGNUM_HAL_INTERRUPT_URXINT2 +#endif + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +static cyg_interrupt gdb_interrupt; +static cyg_handle_t gdb_interrupt_handle; +#endif + +//----------------------------------------------------------------------------- +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + +// This ISR is called only for serial receive interrupts. +int +cyg_hal_gdb_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs) +{ + cyg_uint8 c; + + c = hal_cl7211_get_char(); // Fetch the character + if( 3 == c ) { // ^C + // Ctrl-C: set a breakpoint at PC so GDB will display the + // correct program context when stopping rather than the + // interrupt handler. + cyg_hal_gdb_interrupt (regs->pc); + cyg_drv_interrupt_acknowledge(CYG_GDB_DEV_INT); + } + return 0; // No need to run DSR +} + +int +hal_cl7211_interruptible(int state) +{ + if (state) { + cyg_drv_interrupt_unmask(CYG_GDB_DEV_INT); + } else { + cyg_drv_interrupt_mask(CYG_GDB_DEV_INT); + } + + return 0; +} +#endif + +// Initialize the current serial port. +void hal_cl7211_init_serial(void) +{ + // Enable port + *(volatile cyg_uint32 *)CYG_GDB_DEV_CTRL |= SYSCON1_UART1EN; + // Configure + *(volatile cyg_uint32 *)CYG_GDB_DEV_BLCR = + UART_BITRATE(CYGHWR_HAL_ARM_CL7211_GDB_BAUD) | + UBLCR_FIFOEN | UBLCR_WRDLEN8; + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + cyg_drv_interrupt_create(CYG_GDB_DEV_INT, + 99, // Priority - what goes here? + 0, // Data item passed to interrupt handler + cyg_hal_gdb_isr, + 0, + &gdb_interrupt_handle, + &gdb_interrupt); + cyg_drv_interrupt_attach(gdb_interrupt_handle); + cyg_drv_interrupt_unmask(CYG_GDB_DEV_INT); +#endif +} + +// Write C to the current serial port. +void hal_cl7211_put_char(int c) +{ + cyg_uint32 stat; + // Wait for Tx FIFO not full + do { + stat = *(volatile cyg_uint32 *)CYG_GDB_DEV_STAT; + } while ((stat & SYSFLG1_UTXFF1) != 0) ; + *(volatile cyg_uint32 *)CYG_GDB_DEV_DATA = c; +} + +// Read one character from the current serial port. +int hal_cl7211_get_char(void) +{ + cyg_uint32 stat, val; + do { + stat = *(volatile cyg_uint32 *)CYG_GDB_DEV_STAT; + } while ((stat & SYSFLG1_URXFE1) != 0); + // Need to read 32 bits + val = *(volatile cyg_uint32 *)CYG_GDB_DEV_DATA & 0xFF; + return val; +} + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +//----------------------------------------------------------------------------- +// End of plf_stub.c
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/support/Makefile @@ -0,0 +1,10 @@ +# +# eCos support tools for EP7211 +# + +DL_FILES = dl_7211.o io.o + +all: dl_7211 + +dl_7211: $(DL_FILES) + $(CC) -o $@ $(DL_FILES) \ No newline at end of file
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/support/bootcode.h @@ -0,0 +1,131 @@ +// THIS IS A GENERATED FILE...DO NOT EDIT! +char pcBoot[2048] = { + 20, 208, 159, 229, 1, 0, 160, 227, 203, 0, 0, 235, 180, 0, 0, 235, + 2, 1, 160, 227, 64, 8, 128, 229, 252, 255, 255, 234, 0, 8, 0, 16, + 2, 1, 160, 227, 4, 0, 45, 229, 0, 0, 157, 229, 64, 1, 144, 229, + 1, 5, 16, 227, 3, 0, 0, 10, 0, 0, 157, 229, 64, 1, 144, 229, + 1, 5, 16, 227, 251, 255, 255, 26, 0, 0, 157, 229, 128, 4, 144, 229, +255, 0, 0, 226, 4, 208, 141, 226, 14, 240, 160, 225, 255, 0, 0, 226, + 2, 17, 160, 227, 4, 16, 45, 229, 0, 16, 157, 229, 64, 17, 145, 229, + 2, 5, 17, 227, 3, 0, 0, 10, 0, 16, 157, 229, 64, 17, 145, 229, + 2, 5, 17, 227, 251, 255, 255, 26, 0, 16, 157, 229, 4, 208, 141, 226, +128, 4, 161, 229, 14, 240, 160, 225, 13, 192, 160, 225, 0, 216, 45, 233, + 4, 176, 76, 226, 2, 1, 160, 227, 4, 0, 45, 229, 219, 255, 255, 235, + 48, 0, 64, 226, 5, 0, 80, 227, 0, 241, 143, 144, 23, 0, 0, 234, + 6, 0, 0, 234, 8, 0, 0, 234, 10, 0, 0, 234, 12, 0, 0, 234, + 14, 0, 0, 234, 7, 8, 160, 227, 1, 0, 128, 226, 13, 0, 0, 234, + 23, 0, 160, 227, 7, 8, 128, 226, 10, 0, 0, 234, 11, 0, 160, 227, + 7, 8, 128, 226, 7, 0, 0, 234, 7, 0, 160, 227, 7, 8, 128, 226, + 4, 0, 0, 234, 5, 0, 160, 227, 7, 8, 128, 226, 1, 0, 0, 234, + 7, 8, 160, 227, 3, 0, 128, 226, 0, 16, 157, 229, 192, 4, 161, 229, +190, 255, 255, 235, 45, 0, 80, 227, 252, 255, 255, 26, 0, 168, 27, 233, + 13, 192, 160, 225, 0, 216, 45, 233, 4, 176, 76, 226, 183, 255, 255, 235, + 0, 16, 160, 225, 181, 255, 255, 235, 0, 20, 129, 225, 179, 255, 255, 235, + 0, 24, 129, 225, 177, 255, 255, 235, 0, 12, 129, 225, 0, 32, 144, 229, +255, 0, 2, 226, 188, 255, 255, 235, 255, 48, 160, 227, 34, 4, 3, 224, +185, 255, 255, 235, 34, 8, 3, 224, 183, 255, 255, 235, 34, 12, 160, 225, + 0, 104, 27, 233, 180, 255, 255, 234, 13, 192, 160, 225, 0, 216, 45, 233, + 4, 176, 76, 226, 161, 255, 255, 235, 0, 16, 160, 225, 159, 255, 255, 235, + 0, 20, 129, 225, 157, 255, 255, 235, 0, 24, 129, 225, 155, 255, 255, 235, + 0, 28, 129, 225, 153, 255, 255, 235, 0, 32, 160, 225, 151, 255, 255, 235, + 0, 36, 130, 225, 149, 255, 255, 235, 0, 40, 130, 225, 147, 255, 255, 235, + 0, 12, 130, 225, 0, 0, 129, 229, 0, 168, 27, 233, 13, 192, 160, 225, +240, 223, 45, 233, 4, 176, 76, 226, 8, 208, 77, 226, 3, 129, 160, 227, +138, 255, 255, 235, 0, 16, 160, 225, 136, 255, 255, 235, 0, 20, 129, 225, +134, 255, 255, 235, 0, 24, 129, 225, 132, 255, 255, 235, 0, 28, 129, 225, +130, 255, 255, 235, 0, 32, 160, 225, 128, 255, 255, 235, 0, 36, 130, 225, +126, 255, 255, 235, 0, 40, 130, 225, 124, 255, 255, 235, 0, 76, 130, 225, + 0, 32, 160, 227, 0, 0, 84, 227, 4, 0, 0, 154, 119, 255, 255, 235, + 2, 0, 200, 231, 1, 32, 130, 226, 4, 0, 82, 225, 250, 255, 255, 58, + 15, 34, 1, 226, 7, 114, 98, 226, 15, 98, 193, 227, 92, 0, 0, 235, + 0, 80, 160, 225, 0, 0, 80, 227, 15, 0, 0, 154, 4, 144, 134, 224, + 1, 0, 69, 226, 0, 160, 160, 225, 13, 32, 160, 225, 4, 16, 141, 226, + 85, 0, 0, 235, 4, 16, 157, 229, 1, 0, 89, 225, 3, 0, 0, 58, + 7, 0, 160, 225, 137, 0, 0, 235, 48, 0, 133, 226, 110, 255, 255, 235, + 10, 80, 160, 225, 0, 0, 90, 227, 240, 255, 255, 138, 0, 80, 160, 227, + 0, 0, 84, 227, 9, 0, 0, 154, 5, 32, 136, 224, 5, 16, 134, 224, + 7, 0, 160, 225, 1, 59, 160, 227, 147, 0, 0, 235, 44, 0, 160, 227, + 97, 255, 255, 235, 1, 91, 133, 226, 4, 0, 85, 225, 245, 255, 255, 58, +240, 175, 27, 233, 13, 192, 160, 225, 0, 216, 45, 233, 4, 176, 76, 226, + 63, 0, 160, 227, 88, 255, 255, 235, 72, 255, 255, 235, 66, 0, 80, 227, + 7, 0, 0, 10, 70, 0, 80, 227, 9, 0, 0, 10, 82, 0, 80, 227, + 5, 0, 0, 10, 87, 0, 80, 227, 244, 255, 255, 26, 153, 255, 255, 235, +242, 255, 255, 234, 91, 255, 255, 235, 240, 255, 255, 234, 127, 255, 255, 235, +238, 255, 255, 234, 168, 255, 255, 235, 236, 255, 255, 234, 2, 17, 160, 227, + 0, 32, 160, 227, 2, 49, 160, 227, 1, 58, 131, 226, 128, 34, 129, 229, +128, 34, 131, 229, 128, 35, 129, 229, 192, 35, 129, 229, 128, 192, 160, 227, + 2, 201, 140, 226, 128, 193, 129, 229, 129, 192, 160, 227, 0, 0, 80, 227, + 64, 39, 129, 229, 0, 194, 129, 229, 2, 5, 160, 3, 0, 1, 145, 21, +255, 4, 192, 19, 127, 8, 192, 19, 254, 12, 192, 19, 255, 0, 192, 19, + 0, 1, 129, 229, 5, 0, 160, 227, 0, 1, 163, 229, 64, 32, 193, 229, +254, 0, 160, 227, 65, 0, 193, 229, 67, 32, 193, 229, 15, 0, 160, 227, +192, 0, 193, 229, 1, 32, 193, 5, 1, 0, 209, 21, 4, 0, 0, 18, + 1, 0, 193, 21, 3, 32, 193, 229, 2, 0, 160, 227, 128, 0, 193, 229, + 14, 240, 160, 225, 71, 0, 160, 227, 14, 240, 160, 225, 0, 0, 80, 227, + 1, 0, 0, 186, 71, 0, 80, 227, 1, 0, 0, 186, 0, 0, 160, 227, + 14, 240, 160, 225, 8, 0, 80, 227, 0, 7, 160, 177, 0, 0, 129, 181, + 1, 9, 160, 179, 4, 0, 0, 186, 242, 56, 160, 227, 255, 52, 131, 226, +128, 8, 131, 224, 0, 0, 129, 229, 2, 8, 160, 227, 0, 0, 130, 229, + 1, 0, 160, 227, 14, 240, 160, 225, 4, 0, 45, 229, 128, 16, 160, 227, + 2, 21, 129, 226, 0, 0, 157, 229, 0, 0, 144, 229, 255, 4, 192, 227, +127, 8, 192, 227, 255, 12, 192, 227, 127, 0, 192, 227, 1, 0, 80, 225, +247, 255, 255, 26, 80, 16, 160, 227, 5, 22, 129, 226, 0, 0, 157, 229, + 4, 208, 141, 226, 0, 16, 128, 229, 14, 240, 160, 225, 13, 192, 160, 225, + 48, 216, 45, 233, 4, 176, 76, 226, 0, 64, 160, 225, 8, 208, 77, 226, + 0, 80, 160, 227, 210, 255, 255, 235, 0, 0, 80, 227, 10, 0, 0, 218, + 13, 32, 160, 225, 4, 16, 141, 226, 5, 0, 160, 225, 206, 255, 255, 235, + 4, 0, 160, 225, 4, 16, 157, 229, 4, 0, 0, 235, 1, 80, 133, 226, +199, 255, 255, 235, 5, 0, 80, 225, 244, 255, 255, 202, 48, 168, 27, 233, + 13, 192, 160, 225, 0, 216, 45, 233, 4, 176, 76, 226, 4, 0, 45, 229, + 0, 0, 81, 227, 15, 0, 0, 186, 2, 5, 81, 227, 13, 0, 0, 170, + 32, 48, 160, 227, 2, 54, 131, 226, 65, 17, 160, 225, 0, 32, 157, 229, + 1, 49, 130, 231, 208, 32, 160, 227, 13, 38, 130, 226, 0, 48, 157, 229, + 1, 33, 131, 231, 199, 255, 255, 235, 255, 0, 160, 227, 255, 8, 128, 226, + 0, 16, 157, 229, 0, 0, 129, 229, 0, 168, 27, 233, 13, 192, 160, 225, +240, 216, 45, 233, 4, 176, 76, 226, 0, 80, 160, 225, 1, 64, 160, 225, + 4, 0, 45, 229, 0, 0, 84, 227, 4, 0, 0, 186, 2, 5, 84, 227, + 2, 0, 0, 170, 3, 0, 132, 224, 2, 5, 80, 227, 0, 0, 0, 218, +240, 168, 27, 233, 0, 96, 160, 227, 0, 0, 83, 227, 13, 0, 0, 218, + 64, 112, 160, 227, 1, 117, 135, 226, 0, 0, 157, 229, 0, 112, 128, 229, + 6, 16, 146, 231, 6, 0, 132, 224, 64, 193, 160, 225, 0, 0, 157, 229, + 12, 17, 128, 231, 5, 0, 160, 225, 166, 255, 255, 235, 4, 96, 134, 226, + 3, 0, 86, 225, 243, 255, 255, 186, 255, 16, 160, 227, 255, 24, 129, 226, + 0, 0, 157, 229, 0, 16, 128, 229, 232, 255, 255, 234, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/support/dl_7211.c @@ -0,0 +1,410 @@ +//**************************************************************************** +// +// DOWNLOAD.C - Automates the download of code into the flash on the +// CL-PS7111-DK-D2 board. +// +// Copyright (c) 1999 Cirrus Logic, Inc. +// +// Adapted for Linux by Cygnus Solutions, Inc. +// +//**************************************************************************** +#include <stdio.h> +#include "bootcode.h" + +#define DEFAULT_PORT "/dev/ttyS1" +extern char ReceiveChar(long); +extern void SendChar(long, char); +extern void SetBaud(long, long); +extern int CharRead(long port); +extern void WaitForOutputReady(long port); +extern long OpenPort(char *); + +//**************************************************************************** +// +// WaitFor waits until a specific character is read from the comm port. +// +//**************************************************************************** +void +WaitFor(long lPort, char cWaitChar) +{ + char cChar; + + // + // Wait until we read a specific character from the comm port. + // + while(1) + { + // + // Read a character. + // + cChar = ReceiveChar(lPort); + + // + // Stop waiting if we received the character. + // + if(cChar == cWaitChar) + { + break; + } + } +} + +//**************************************************************************** +// +// This program waits for the '<' character from the boot ROM, sends the boot +// code, waits for the '>' from the boot ROM, waits for the '?' from the boot +// code, changes the serial port rate (preferably to 115200), downloads the +// user data file, and then prints out progress status as the boot code writes +// the user data file to the flash. +// +//**************************************************************************** +void +main(int argc, char *argv[]) +{ + long lPort; + long lRate = 38400; + long lFileSize, lIdx; + char cChar, cFirstChar, *pcFile, cRateChar; + FILE *pFile; + + // + // Make sure that a filename was specified. + // + if(argc < 2) + { + fprintf(stderr, "Usage: download <filename> {<baud rate> {<comm port>}}\n"); + return; + } + + // + // If a baud rate was specified, then read it and make sure it is valid. + // + if(argc > 2) + { + lRate = atoi(argv[2]); + if((lRate != 9600) && (lRate != 19200) && (lRate != 28800) && + (lRate != 38400) && (lRate != 57600) && (lRate != 115200)) + { + fprintf(stderr, "Invalid baud rate.\n"); + return; + } + } + + // + // If a comm port was specified, then read it and make sure it is valid. + // + if(argc > 3) + { + lPort = OpenPort(argv[3]); + } else + { + lPort = OpenPort(DEFAULT_PORT); + } + if (lPort < 0) + { + fprintf(stderr, "Can't open port\n"); + return; + } + + // + // Open the file to be downloaded. + // + pFile = fopen(argv[1], "rb"); + if(!pFile) + { + fprintf(stderr, "Could not open file '%s'.\n", argv[1]); + return; + } + + // + // Get the size of the file. + // + fseek(pFile, 0, SEEK_END); + lFileSize = ftell(pFile); + fseek(pFile, 0, SEEK_SET); + + // + // Allocate memory to hold the file contents. + // + pcFile = (char *)malloc(lFileSize); + if(!pcFile) + { + fprintf(stderr, "Failed to allocate memory for the file.\n"); + return; + } + + // + // Read the contents of the file into memory. + // + if(fread(pcFile, 1, lFileSize, pFile) != lFileSize) + { + fprintf(stderr, "Failed to read file '%s'.\n", argv[1]); + return; + } + + // + // Close the file. + // + fclose(pFile); + + // + // Get the baud rate divisor for the given baud rate. + // + SetBaud(lPort, 9600); + switch(lRate) + { + case 9600: + { + cRateChar = '0'; + break; + } + + case 19200: + { + cRateChar = '1'; + break; + } + + case 28800: + { + cRateChar = '2'; + break; + } + + case 38400: + { + cRateChar = '3'; + break; + } + + case 57600: + { + cRateChar = '4'; + break; + } + + case 115200: + { + cRateChar = '5'; + break; + } + } + + // + // Empty out the input queue. + // + while(CharReady(lPort)) + { + cChar = ReceiveChar(lPort); + } + + // + // Tell the user to reset the board. + // + fprintf(stderr, "Waiting for the board to wakeup..."); + + // + // Wait until we read a '<' from the comm port. + // + WaitFor(lPort, '<'); + + // + // Tell the user that we are downloading the boot code. + // + fprintf(stderr, "\nDownloading boot code...( 0%%)"); + + // + // Write the boot code to the comm port. + // + for(lIdx = 0; lIdx < 2048; lIdx++) + { + // + // Write this character. + // + SendChar(lPort, pcBoot[lIdx]); + + // + // Periodically print out our progress. + // + if((lIdx & 127) == 127) + { + fprintf(stderr, "\b\b\b\b\b%3d%%)", ((lIdx + 1) * 100) / 2048); + } + } + + // + // Wait until we read a '>' from the comm port. + // + WaitFor(lPort, '>'); + + // + // Wait until we read a '?' from the comm port. + // + WaitFor(lPort, '?'); + + // + // Tell the boot code to switch to the desired baud rate. + // + SendChar(lPort, 'B'); + SendChar(lPort, cRateChar); + + // + // Wait until the output buffer is empty. + // + WaitForOutputEmpty(); + + // + // Switch our baud rate to the desired rate. + // + SetBaud(lPort, lRate); + + // + // Send a '-' character until we receive back a '?' character. + // + while(1) + { + // + // Send a '-' character. + // + SendChar(lPort, '-'); + + // + // Wait a little bit. + // + for(lIdx = 0; lIdx < 1024 * 1024; lIdx++) + { + } + + // + // See if there is a character waiting to be read. + // + if(CharReady(lPort)) + { + // + // Read the character. + // + cChar = ReceiveChar(lPort); + + // + // Quit waiting if this is a '?'. + // + if(cChar == '?') + { + break; + } + } + } + + // + // Empty out the input queue. + // + while(CharReady(lPort)) + { + cChar = ReceiveChar(lPort); + } + + // + // Send the program flash command. + // + SendChar(lPort, 'F'); + + // + // We always program the flash at location 0. + // + SendChar(lPort, 0); + SendChar(lPort, 0); + SendChar(lPort, 0); + SendChar(lPort, 0); + + // + // Send the length of the data file. + // + SendChar(lPort, (char)(lFileSize & 0xFF)); + SendChar(lPort, (char)((lFileSize >> 8) & 0xFF)); + SendChar(lPort, (char)((lFileSize >> 16) & 0xFF)); + SendChar(lPort, (char)((lFileSize >> 24) & 0xFF)); + + // + // Tell the user that we are downloading the file data. + // + fprintf(stderr, "\nDownloading file data...( 0%%)"); + + // + // Send the actual data in the file. + // + for(lIdx = 0; lIdx < lFileSize; lIdx++) + { + // + // Send this byte. + // + SendChar(lPort, pcFile[lIdx]); + + // + // Periodically print out our progress. + // + if((lIdx & 127) == 127) + { + fprintf(stderr, "\b\b\b\b\b%3d%%)", ((lIdx + 1) * 100) / lFileSize); + } + } + + // + // Tell the user that we are erasing the flash. + // + fprintf(stderr, "\nErasing the flash...( 0%%)"); + + // + // Wait until the flash has been erased. + // + cFirstChar = cChar = ReceiveChar(lPort); + while(cChar != '1') + { + // + // Print out our progress. + // + fprintf(stderr, "\b\b\b\b\b%3d%%)", + ((cFirstChar - cChar + 1) * 100) / (cFirstChar - '0')); + + // + // Read a character from the boot code. + // + cChar = ReceiveChar(lPort); + } + + // + // Tell the user that we are programming the flash. + // + fprintf(stderr, "\nProgramming the flash...( 0%%)"); + + // + // Wait until the flash has been programmed. + // + lIdx = 0; + while(1) + { + // + // Read a character from the boot code. + // + cChar = ReceiveChar(lPort); + + // + // If the character is a '?', then we are done. + // + if(cChar == '?') + { + break; + } + + // + // Print out our progress. + // + fprintf(stderr, "\b\b\b\b\b%3d%%)", + (++lIdx * 100) / ((lFileSize + 1023) / 1024)); + } + + // + // Tell the user we are done. + // + fprintf(stderr, "\nSuccessfully downloaded '%s'.\n", argv[1]); +} +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/support/io.c @@ -0,0 +1,151 @@ +//========================================================================== +// +// io.c +// +// Linux I/O support for Cirrus CL7211 eval board tools +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-16 +// Description: Linux I/O support for Cirrus CL7211 FLASH tools +//####DESCRIPTIONEND#### + +// +// io.c - I/O functions +// + +#include <stdio.h> +#include <sys/ioctl.h> +#include <fcntl.h> +#include <termios.h> + +char ReceiveChar(long port) +{ + char buf; + int res; + // Port is in non-blocking mode, this needs to have a loop + do { + res = read(port, &buf, 1); + } while (res < 0); +// printf("Read: %c\n", buf); + return buf; +} + +static void +uspin(int len) +{ + volatile int cnt; + while (--len >= 0) { + for (cnt = 1; cnt < 100; cnt++) ; + } +} + +void SendChar(long port, char ch) +{ + char buf = ch; + write(port, &buf, 1); +// printf("Send: %x\n", ch); +// usleep(100); + uspin(100); +} + +void SetBaud(long port, long reqRate) +{ + struct termios buf; + int rate; + + // Get original configuration + if (tcgetattr(port, &buf)) { + fprintf(stderr, "Can't get port config\n"); + return; + } + + // Reset to raw. + buf.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP + |INLCR|IGNCR|ICRNL|IXON); + buf.c_oflag &= ~OPOST; + buf.c_lflag &= ~(ECHO|ECHONL|ICANON|ISIG|IEXTEN); + buf.c_cflag &= ~(CSIZE|PARENB); + buf.c_cflag |= CS8; + + // Set baud rate. + switch (reqRate) { + case 9600: + rate = B9600; + break; + case 38400: + rate = B38400; + break; + case 57600: + rate = B57600; + break; + case 115200: + rate = B115200; + break; + } + cfsetispeed(&buf, rate); + cfsetospeed(&buf, rate); + + // Set data bits. + buf.c_cflag &= ~CSIZE; + buf.c_cflag |= CS8; + + // Set stop bits. + buf.c_cflag &= ~CSTOPB; // One stop + + // Set parity. + buf.c_cflag &= ~(PARENB | PARODD); // no parity. + + // Set the new settings + if (tcsetattr(port, TCSADRAIN, &buf)) { + fprintf(stderr, "Error: tcsetattr\n"); + return; + } + + tcdrain(port); + usleep(1000000/10*2); +} + +int CharReady(long port) +{ + int n, res; + res = ioctl(port, FIONREAD, &n); + return n; // Non-zero if characters ready to read +} + +void WaitForOutputEmpty(long port) +{ + usleep(2000000); +} + +long OpenPort(char *name) +{ + int fd; + fd = open(name, O_RDWR|O_NONBLOCK); + return fd; +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/cl7211/current/tests/PKGconf.mak @@ -0,0 +1,39 @@ +#=============================================================================== +# +# makefile +# +# kernel/tests +# +#=============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#=============================================================================== + +PACKAGE := hal_arm_cl7211 +include ../../../../../pkgconf/pkgconf.mak + +TESTS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst + + +
--- a/packages/hal/common/current/ChangeLog +++ b/packages/hal/common/current/ChangeLog @@ -1,3 +1,8 @@ +1999-08-17 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * tests/intr.c (cyg_start): Use CYG_TEST_NA rather than a pass saying + it's inapplicable + 1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/pkgconf/hal.h: Rename CYG_HAL_MN10300_AM32_STDEVAL1 to @@ -38,6 +43,11 @@ 1999-06-17 Nick Garnett <nickg@cygnus. to enable inclusion of ^C interrupt handler. Added CDL to control it. +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/hal.h: Add support for the PowerPC target MBX860 + platform, CYG_HAL_POWERPC_MBX. + 1999-06-10 Gary Thomas <gthomas@cygnus.co.uk> * src/hal_stub.c: Need to init register pointer.
--- a/packages/hal/common/current/include/pkgconf/hal.h +++ b/packages/hal/common/current/include/pkgconf/hal.h @@ -450,6 +450,11 @@ # define CYG_HAL_POWERPC_MPC8xx # define CYG_HAL_POWERPC_MPC860 #endif +#ifdef CYG_HAL_POWERPC_MBX +# define CYG_HAL_POWERPC_MPC8xx +# define CYG_HAL_POWERPC_MPC860 +# define CYG_HAL_POWERPC_COPY_VECTORS +#endif #ifdef CYG_HAL_POWERPC_SIM # define CYG_HAL_POWERPC_MPC603 #endif
--- a/packages/hal/common/current/tests/intr.c +++ b/packages/hal/common/current/tests/intr.c @@ -121,7 +121,7 @@ cyg_start( void ) #else - CYG_TEST_PASS_FINISH("N/A: Cannot override kernel real-time clock."); + CYG_TEST_NA("Cannot override kernel real-time clock."); #endif }
--- a/packages/hal/mn10300/arch/current/ChangeLog +++ b/packages/hal/mn10300/arch/current/ChangeLog @@ -1,3 +1,14 @@ +1999-08-18 Nick Garnett <nickg@cygnus.co.uk> + + * src/hal_misc.c (cyg_hal_exception_handler): + Use CYGNUM_HAL_EXCEPTION_WATCHDOG rather than + CYGNUM_HAL_INTERRUPT_WATCHDOG in test for watchdog exceptions. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * include/arch.inc: Modified hal_cpu_int_merge to avoid corrupting + any registers other than the one passed as an argument. + 1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> * include/arch.inc: rename CYGPKG_HAL_MN10300_AM32_STDEVAL1 to
--- a/packages/hal/mn10300/arch/current/include/arch.inc +++ b/packages/hal/mn10300/arch/current/include/arch.inc @@ -77,11 +77,13 @@ # Merge the interrupt enable state of the status register in # \sr with the current sr. .macro hal_cpu_int_merge sr - and 0x00000F00,\sr # isolate IE bit - mov psw,d0 - and 0xfffff0ff,d0 - or d0,\sr - mov \sr,psw + movm [d3],(sp) + and 0x00000F00,\sr # isolate IE and IM bits + hal_cpu_get_psw d3 + and 0xfffff0ff,d3 + or \sr,d3 + hal_cpu_set_psw d3 + movm (sp),[d3] .endm # Enable further exception processing, and disable @@ -183,7 +185,7 @@ #------------------------------------------------------------------------------ # temporary trace macros -#if 0 +#if 1 #ifdef CYGPKG_HAL_MN10300_AM31_STDEVAL1 #define TRACE_BASE 0x48100000
--- a/packages/hal/mn10300/arch/current/src/hal_misc.c +++ b/packages/hal/mn10300/arch/current/src/hal_misc.c @@ -181,7 +181,7 @@ cyg_hal_exception_handler(HAL_SavedRegis #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) - if( vector == CYGNUM_HAL_INTERRUPT_WATCHDOG ) + if( vector == CYGNUM_HAL_EXCEPTION_WATCHDOG ) { // Special case the watchdog timer exception, look for an // ISR for it and call it if present. Otherwise pass on to
--- a/packages/hal/powerpc/arch/current/ChangeLog +++ b/packages/hal/powerpc/arch/current/ChangeLog @@ -25,6 +25,7 @@ 1999-06-27 Gary Thomas <gthomas@cygnus * src/hal_intr.c (hal_IRQ_init): New platform dependent function used to setup whatever is necessary to handle interrupts. + Add basic "wiring" of CPM to SIU interrupts. * include/hal_intr.h: Fix CPM interrupt macros - control register is 32 bits, not 16. @@ -33,6 +34,14 @@ 1999-06-24 Jesper Skov <jskov@cygnus.c * misc/CPUMask8xx.c: Added. +1999-06-24 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_misc.c (cyg_hal_exception_handler): If the decrementer + has underflowed when we are returning from an exception, then we + reset it here; this is harmless if all is well, and required if + the QUICC-equipped MPC860 is getting confused about interrupts + following an exception. Only in QUICC configurations. + 1999-06-22 Hugo Tyson <hmt@cygnus.co.uk> * src/vectors.S (_start): Support breaking back into the stub ROM @@ -86,6 +95,14 @@ 1999-06-10 Hugo Tyson <hmt@cygnus.co.u * include/quicc_smc.h, src/ppc_860.h, src/quicc_smc.c: removed; reorganized and renamed into the FADS component. + * src/hal_misc.c (hal_idle_thread_action): Add some useful + debugging for interrupt/clock of the MBX860/PPC860; normally + disabled, so no effect on code. + + * include/ppc_regs.h: Different default value for + CYGARC_REG_IMM_BASE if MBX board (ie. the way CygMon sets it up). + This is a temporary measure. + 1999-06-08 Jesper Skov <jskov@cygnus.co.uk> * include/hal_intr.h:
--- a/packages/hal/powerpc/arch/current/src/hal_misc.c +++ b/packages/hal/powerpc/arch/current/src/hal_misc.c @@ -118,6 +118,38 @@ cyg_hal_exception_handler(HAL_SavedRegis __handle_exception(); +#ifdef CYGPKG_HAL_QUICC + { + // This is unpleasant: it appears that if we interrupt the board + // using ^C coming in on the QUICC's SMC1, by planting a breakpoint + // at the interrupt return address, the decrementer interrupt is + // not taken when the bp exception returns AND WORSE no other + // interrupt is possible until the decrementer fires again. This + // does not apply to simple "incoming character" interrupts; it + // seems it has to be combined with an immediate trap on RTI for + // this to occur. + // + // The solution is to test for decrementer underflow after the + // (any) exception, and maybe reinitialize the decrementer. If the + // decrementer interrupt gets taken, that causes decrementer reinit + // too, and no harm is done. + + cyg_uint32 result; + asm volatile( + "mfdec %0;" + : "=r"(result) + ); + + if ( CYGNUM_HAL_RTC_PERIOD < result ) { + // then we missed a tick, but the exception masked it + // reset the decrementer here + asm volatile( + "mtdec %0;" + : : "r"(CYGNUM_HAL_RTC_PERIOD) + ); + } + } +#endif #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ defined(CYGPKG_HAL_EXCEPTIONS) @@ -189,6 +221,23 @@ hal_default_decrementer_isr(CYG_ADDRWORD void hal_idle_thread_action( cyg_uint32 count ) { +#if 0 +#ifdef CYG_HAL_POWERPC_MPC860 + register cyg_uint32 result; + + cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ; + cyg_uint32 *psimask = (cyg_uint32*)CYGARC_REG_IMM_SIMASK; + cyg_uint32 *psipend = (cyg_uint32*)CYGARC_REG_IMM_SIPEND; + cyg_uint16 *ptbscr = (cyg_uint16*)CYGARC_REG_IMM_TBSCR; + + asm volatile( + "mfdec %0;" + : "=r"(result) + ); + diag_printf( "Dec %08x, TBSCR %04x, vec %d: sivec %08x, simask %08x, sipend %08x\n", + result, (cyg_uint32)(*ptbscr), (*psivec)>>26, *psivec, *psimask, *psipend ); +#endif +#endif } //--------------------------------------------------------------------------- @@ -422,6 +471,12 @@ externC void hal_MMU_init (void) # endif #endif +#ifdef CYGPKG_HAL_POWERPC_MBX // Enable all caches for MBX860 +# ifndef CYG_HAL_ROM_MONITOR // unless we are making a stub rom +# define CYGPRI_INIT_CACHES 1 +# define CYGPRI_ENABLE_CACHES 1 +# endif +#endif // Do not enable caches for the FADS port pro tem; the memory mapping is // not set up.
--- a/packages/hal/powerpc/arch/current/src/vectors.S +++ b/packages/hal/powerpc/arch/current/src/vectors.S @@ -296,6 +296,9 @@ 2: #ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for StubRom-supported startup +#ifdef CYG_HAL_POWERPC_MBX +# define CYGPRI_STUBROM_HAS_RAM_VECTORS +#endif #ifdef CYGPRI_STUBROM_HAS_RAM_VECTORS # ifdef CYG_HAL_STARTUP_RAM
--- a/packages/hal/powerpc/arch/current/tests/intr0.c +++ b/packages/hal/powerpc/arch/current/tests/intr0.c @@ -64,7 +64,11 @@ extern diag_printf( char *format, ... ); // interrupt handlers. #define PIT_PERIOD 5000 +#ifdef CYG_HAL_POWERPC_MBX +#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS +#else #define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors +#endif #define ID_RTC_SEC 12345 #define ID_RTC_ALR 23451
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/ChangeLog @@ -0,0 +1,192 @@ +1999-07-27 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S: Fix typo in PLL setup value. Reported from the net. + +1999-06-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_init): Fix a "default type" warning. + +1999-06-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/hal_diag.c (hal_diag_write_char): Only gobble the GDB ACK + characters if there is no pre-ISR polling call to look for ^C + chars to interrupt the prog. (CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + - should not be enabled if devices are in use) + +1999-06-28 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S (__upmtbl_start): We do not trust rewriting the UPMs + for DRAM timing whilst running out of that very DRAM. So only + init UPMs in ROM start (including when making a stub rom). + +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/hal_diag.c: Support buffering of diagnostic data for later + display. Controlled by CYGDBG_DIAG_BUF. Also, turn on code to + handle GDB ACK characters when stubs are enabled. + +1999-06-25 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S (__upmtbl_start): depending on CYG_HAL_ROM_MONITOR, we + use the OLD TABLES if making a stub rom. For greatest commonality + of startup code between RAM startup development binaries and ROM + startup "product" binaries we completely re-initialize the UPMs + that control DRAM timing even in RAM start when executing out of + that very DRAM. + + It appears that it is OK to rewrite the UPMs with the new timing + data when already running with the old timing data, but not OK to + update from new to new. So we use the old timing data when + building stubs. + + An alternative would be to conditionally not perform the UPM + initialization in RAM startup, but that would weaken the testing + value of RAM startup programs. + +1999-06-24 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S (__upmtbl_start): Use the new tables recently supplied + by email from Motorola; without them, the cache-line-zero + operation only zeros 12 bytes rather than 16. [PR 20226] + +1999-06-24 Hugo Tyson <hmt@cygnus.co.uk> + + * include/plf_stub.h (HAL_STUB_PLATFORM_INIT_BREAK_IRQ): Define + this (empty) for it is required if HAL_DEBUG_GDB_BREAK_SUPPORT is + enabled. Improve HAL_STUB_PLATFORM_SET_BAUD_RATE. + +1999-06-18 John Dallaway <jld@cygnus.co.uk> + + * include/pkgconf/mlt_powerpc_mbx_rom.mlt: + * include/pkgconf/mlt_powerpc_mbx_ram.mlt: + Fix MLT save files to match the default linker script + fragments. + +1999-06-18 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/mlt_powerpc_mbx_rom.mlt: + * include/pkgconf/mlt_powerpc_mbx_ram.mlt: + Initial attempt at getting these to match the reality of the + linker script fragment; we'll have to see whether they're right. + +1999-06-18 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S: Data cache setup in hal_hardware_init: set + force-writethrough mode and explicitly disable little-endian swap + mode, whatever _that_ is. Force-writethrough is required if you + are to enable the data cache, it crashes otherwise. Cause + unknown, could be the memory system doesn't support whatever + access regime is used, or caching problems with loading code + through the stubs? In any case, this is a fine workaround. + + * src/hal_aux.c (CYGARC_MEMDESC_TABLE): Enable caching of the ROM; + seems to do no harm, and helps ROM-based performance. + +1999-06-18 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_powerpc_mbx.h: Fixed CDL description. + +1999-06-17 Hugo Tyson <hmt@cygnus.co.uk> + + * misc/stubrom.perm: New file: a perm for creating an eCos stub + ROM for the MBX. Pro tem, ^C to break is not supported, so the + feature must remain disabled. + + * include/plf_stub.h (HAL_STUB_PLATFORM_INIT): Diddle the LEDs if + ROM start to distinguish eCos stub ROM from CygMon ROM from eCos + app running/internal stubs. + +1999-06-17 Hugo Tyson <hmt@cygnus.co.uk> + + * include/pkgconf/mlt_powerpc_mbx_rom.ldi: Move RAM usage in ROM + startup to 2000 so that we can build stubs that don't fight with + RAM started apps' RAM use from 10000. + +1999-06-17 Hugo Tyson <hmt@cygnus.co.uk> + + * tests/PKGconf.mak: New file, to build that below. + + * tests/mbxtime.cxx: New file, a simple test of the system timer + for a human to check it's roughly seconds. + + * include/pkgconf/mlt_powerpc_mbx_rom.ldi: ROM startup supported. + + * include/pkgconf/hal_powerpc_mbx.h + (CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED): Add this config option to + select 40MHz or 50MHz system clock speed. + + * src/mbx.S (hal_hardware_init): Complete system init for ROM + start; move return address to inside the ROM from wherever we + booted. Proper board clock speed selection. + + * src/hal_diag.c (hal_diag_write_char_serial): Do not encode + packets for GDB if using ROM start. + + * src/hal_aux.c (CYGARC_MEMDESC_TABLE): Map the ROM correctly so + that ROM start works. + +1999-06-15 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S (hal_hardware_init): Add full ROM-type startup code + and some useful LED-diddling routines and macro, to assist in + debugging ROM startup. + + * src/hal_aux.c (CYGARC_MEMDESC_TABLE): Enable memory mapping to + the LED control register so that we can treak them with mem mgt + enabled ie. in a normal execution context. + +1999-06-11 Hugo Tyson <hmt@cygnus.co.uk> + + * src/mbx.S (hal_hardware_init): Set up the base address of the + control registers in IMMR to 0xff000000 (as defined in arch). + Turn off external interrupts, initialize the decrementer. + + * src/PKGconf.mak: Build the new file. + + * src/hal_aux.c (CYGARC_MEMDESC_TABLE): New file, to define this + object for per-platform table-driven memory map initialization. + The table used to be in hal_misc.c in the architectural HAL; this + is platform dependent so better and cleaner here. + +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * ChangeLog: Component created, based partly on the FADS work and + on CygMon's serial IO code for the MBX860, to support the Motorola + MBX860 development board. Actual serial support lies in + neighbouring component HAL_QUICC [hal/powerpc/quicc/...] + + * include/hal_diag.h + * include/plf_stub.h + * include/pkgconf/hal_powerpc_mbx.h + * include/pkgconf/mlt_powerpc_mbx_ram.ldi + * include/pkgconf/mlt_powerpc_mbx_ram.mlt + * include/pkgconf/mlt_powerpc_mbx_rom.ldi + * include/pkgconf/mlt_powerpc_mbx_rom.mlt + * src/PKGconf.mak + * src/hal_diag.c + * src/mbx.S + New files. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/hal_diag.h @@ -0,0 +1,89 @@ +#ifndef CYGONCE_HAL_HAL_DIAG_H +#define CYGONCE_HAL_HAL_DIAG_H + +//============================================================================= +// +// hal_diag.h +// +// HAL Support for Kernel Diagnostic Routines +// +//============================================================================= +//####UNSUPPORTEDBEGIN#### +// +// ------------------------------------------- +// This source file has been contributed to eCos/Cygnus. It may have been +// changed slightly to provide an interface consistent with those of other +// files. +// +// The functionality and contents of this file is supplied "AS IS" +// without any form of support and will not necessarily be kept up +// to date by Cygnus. +// +// All inquiries about this file, or the functionality provided by it, +// should be directed to the 'ecos-discuss' mailing list (see +// http://sourceware.cygnus.com/ecos/intouch.html for details). +// +// Maintained by: <Unmaintained> +// ------------------------------------------- +// +//####UNSUPPORTEDEND#### +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): nickg +// Contributors:nickg +// Date: 1998-03-02 +// Purpose: HAL Support for Kernel Diagnostic Routines +// Description: Diagnostic routines for use during kernel development. +// Usage: #include <cyg/hal/hal_diag.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> + +//----------------------------------------------------------------------------- +// functions implemented in hal_diag.c + +externC void hal_diag_init(void); + +externC void hal_diag_write_char(char c); + +externC void hal_diag_read_char(char *c); + +//----------------------------------------------------------------------------- + +#define HAL_DIAG_INIT() hal_diag_init() + +#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) + +#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) + +//----------------------------------------------------------------------------- +// end of hal_diag.h +#endif // CYGONCE_HAL_HAL_DIAG_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/hal_powerpc_mbx.h @@ -0,0 +1,113 @@ +#ifndef CYGONCE_PKGCONF_HAL_POWERPC_MBX_H +#define CYGONCE_PKGCONF_HAL_POWERPC_MBX_H +//============================================================================= +// +// pkgconf/hal_powerpc_mbx.h +// +// HAL configuration file +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_POWERPC_MBX { + display "Motorola MBX PowerPC evaluation board" + type radio + parent CYGPKG_HAL_POWERPC + requires CYGPKG_HAL_QUICC + platform mbx + description " + The MBX HAL package provides the support needed to run + eCos on a Motorola MBX board equipped with a PowerPC processor." + } + + cdl_option CYGHWR_HAL_POWERPC_MBX_STARTUP { + display "Startup type" + parent CYGPKG_HAL_POWERPC_MBX + #type count + type enum + legal_values ram rom + startup + description " + When targetting the MBX board for RAM bootstrap it is expected + that the image will be downloaded to eCos GDB stub boot ROMs + using powerpc-eabi-gdb." + } + + cdl_option CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED { + display "Development board clock speed (MHz)" + parent CYGPKG_HAL_POWERPC_MBX + #type count + type enum + legal_values 40 50 + description " + MBX Development Boards have various system clock speeds + depending on the processor fitted. Select the clock speed + appropriate for your board so that the system can set the serial + baud rate correctly, amongst other things." + # This is an enum because the system selects code en masse rather + # than doing arithmetic with the value; making it a count and + # setting it to 30, for example, would not work. + } + + }}CFG_DATA */ + +#define CYGHWR_HAL_POWERPC_MBX_STARTUP ram + +#define CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED 50 + +// Real-time clock/counter specifics + +// Period is busclock/16/100. +#define CYGNUM_HAL_RTC_NUMERATOR 1000000000 +#define CYGNUM_HAL_RTC_DENOMINATOR 100 + +#if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define CYGNUM_HAL_RTC_PERIOD 25000 +#elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define CYGNUM_HAL_RTC_PERIOD 31250 +#else +# error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H +#endif + +// 33.3333MHz from FADS port: +//#define CYGNUM_HAL_RTC_PERIOD 20833 + +/* -------------------------------------------------------------------*/ +#endif /* CYGONCE_PKGCONF_HAL_POWERPC_MBX_H */ +/* EOF hal_powerpc_mbx.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.ldi @@ -0,0 +1,48 @@ +//=========================================================================== +// +// RAM startup linker control script +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + ram : ORIGIN = 0x00010000, LENGTH = 0x3f0000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (ram, 0x10000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_ram.mlt @@ -0,0 +1,12 @@ +version 0 +region ram 10000 3f0000 0 ! +section vectors 0 1 0 1 1 1 1 1 10000 10000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 1 0 1 data data ! +section data 0 8 0 1 0 1 0 1 sbss sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 0 0 0 !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.ldi @@ -0,0 +1,49 @@ +//=========================================================================== +// +// ROM startup linker control script +// +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//=========================================================================== + +MEMORY +{ + rom : ORIGIN = 0xfe000000, LENGTH = 0x800000 + ram : ORIGIN = 0x00002000, LENGTH = 0x3fe000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_vectors (rom, 0xfe000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA) + SECTION_data (ram, 0x2000, FOLLOWING (.gcc_except_table)) + SECTION_sbss (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x10), LMA_EQ_VMA) + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/pkgconf/mlt_powerpc_mbx_rom.mlt @@ -0,0 +1,13 @@ +version 0 +region ram 2000 3fe000 0 ! +region rom fe000000 800000 1 ! +section data 0 1 1 1 1 1 0 0 2000 sbss ! +section sbss 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 10 0 1 0 0 0 0 ! +section vectors 0 1 0 1 1 1 1 1 fe000000 fe000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 8 0 1 0 1 0 1 rodata rodata ! +section rodata 0 8 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 1 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/include/plf_stub.h @@ -0,0 +1,93 @@ +#ifndef CYGONCE_HAL_PLF_STUB_H +#define CYGONCE_HAL_PLF_STUB_H + +//============================================================================= +// +// plf_stub.h +// +// Platform header for GDB stub support. +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 1999-02-12 +// Purpose: Platform HAL stub support for PowerPC/MBX board. +// Usage: #include <cyg/hal/plf_stub.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> +#include <pkgconf/hal_powerpc_mbx.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM + +#include <cyg/hal/ppc_stub.h> // architecture stub support + +#include <cyg/hal/quicc/quicc_smc1.h> // QUICC serial IO support + +//---------------------------------------------------------------------------- +// Define serial stuff. All comes from the quicc_smc1.c file. + +#include <cyg/hal/quicc/quicc_smc1.h> + +#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_quicc_init_smc1() +#define HAL_STUB_PLATFORM_GET_CHAR() cyg_quicc_smc1_uart_rcvchar() +#define HAL_STUB_PLATFORM_PUT_CHAR(c) cyg_quicc_smc1_uart_putchar((c)) + +#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) + +//---------------------------------------------------------------------------- +// Stub initializer. +externC void hal_mbx_set_led( int val ); +#ifdef CYG_HAL_STARTUP_ROM +# define HAL_STUB_PLATFORM_INIT() hal_mbx_set_led( 4 ) +// to distinguish eCos stub ROM ready state from either CygMon or app. +#endif + +#define HAL_STUB_PLATFORM_STUBS_INIT() CYG_EMPTY_STATEMENT + +//---------------------------------------------------------------------------- +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT +#endif + +//---------------------------------------------------------------------------- +// Reset. +#define HAL_STUB_PLATFORM_RESET() CYG_EMPTY_STATEMENT + +#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 + +#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + +//----------------------------------------------------------------------------- +#endif // CYGONCE_HAL_PLF_STUB_H +// End of plf_stub.h
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/misc/stubrom.perm @@ -0,0 +1,32 @@ +# +# A configuration for building a GDB stub ROM for the Motorola MBX board, +# with MPC 860 or 821 CPU. +# +# To build the ROMs: +# 1. Create a build directory and cd into it. +# 2. Run: permtest.tcl --srcdir=<SOURCEDIR> <SOURCEDIR>/hal/powerpc/mbx/current/misc/stubrom.perm +# Where <SOURCEDIR> is the path to your source repository. +# (If necessary, make sure the system clock speed is set correctly in +# pkgconf/hal_powerpc_mbx.h: 40MHz (MPC821) versus 50MHz (MPC860) by default) +# 3. Run: make +# 4. Run: make -C hal/common/current/src/stubrom +# +# The file hal/common/current/src/stubrom/stubrom will be an excutable of the ROM. +# Use objcopy to convert this to the appropriate format for your PROM burner: +# powerpc-eabi-objcopy -O binary hal/common/current/src/stubrom/stubrom stubrom.img +# Enjoy! +# + +pkgconf --target=powerpc --platform=mbx --startup=rom --disable-kernel --disable-uitron --disable-libc --disable-libm --disable-io --disable-io_serial --disable-wallclock --disable-watchdog + +header hal.h { + enable CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + disable CYGFUN_HAL_COMMON_KERNEL_SUPPORT + disable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + disable CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT + disable CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + enable CYG_HAL_ROM_MONITOR +} + +# enable CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT excluded for now +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/src/PKGconf.mak @@ -0,0 +1,41 @@ +#============================================================================== +# +# makefile +# +# hal/powerpc/mbx/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_powerpc_mbx +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := hal_diag.c hal_aux.c mbx.S +OTHER_OBJS := +OTHER_TARGETS := +OTHER_CLEAN := +OTHER_DEPS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/src/hal_aux.c @@ -0,0 +1,65 @@ +//============================================================================= +// +// hal_aux.c +// +// HAL auxiliary objects and code; per platform +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1999-06-08 +// Purpose: HAL aux objects: startup tables. +// Description: Tables for per-platform initialization +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt macros +#include <cyg/hal/hal_cache.h> // Cache macros + +// The memory map is weakly defined, allowing the application to redefine +// it if necessary. The regions defined below are the minimum requirements. +CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = { + // Mapping for the Motorola MBX860 development board + CYGARC_MEMDESC_CACHE( 0xfe000000, 0x00400000 ), // ROM region + CYGARC_MEMDESC_NOCACHE( 0xff000000, 0x00100000 ), // MCP registers + CYGARC_MEMDESC_NOCACHE( 0xfa100000, 0x00000004 ), // Control/Status+LEDs + CYGARC_MEMDESC_CACHE( 0x00000000, 0x00800000 ), // Main memory + + CYGARC_MEMDESC_TABLE_END +}; + +// EOF hal_aux.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/src/hal_diag.c @@ -0,0 +1,230 @@ +//============================================================================= +// +// hal_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors:hmt +// Date: 1999-06-08 +// Purpose: HAL diagnostic output +// Description: Implementations of HAL diagnostic output support. +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros + +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt macros + +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#include <cyg/hal/hal_stub.h> // hal_output_gdb_string +#endif + +#include <cyg/hal/ppc_regs.h> +#include <cyg/hal/quicc/quicc_smc1.h> + +//----------------------------------------------------------------------------- +// Select default diag channel to use + +//#define CYG_KERNEL_DIAG_ROMART +//#define CYG_KERNEL_DIAG_SERIAL + +#if !defined(CYG_KERNEL_DIAG_SERIAL) +#define CYG_KERNEL_DIAG_SERIAL +#endif + +#ifdef CYGDBG_DIAG_BUF +// Keep diag messages in a buffer for later [re]display + +int enable_diag_uart = 1; +int enable_diag_buf = 1; +static char diag_buf[40960*4]; +static int diag_buf_ptr = 0; + +static void +diag_putc(char c) +{ + if (enable_diag_buf) { + diag_buf[diag_buf_ptr++] = c; + if (diag_buf_ptr == sizeof(diag_buf)) diag_buf_ptr--; + } +} + +void +dump_diag_buf(int start, int len) +{ + int i; + enable_diag_uart = 1; + enable_diag_buf = 0; + if (len == 0) len = diag_buf_ptr; + diag_printf("\nDiag buf\n"); + for (i = start; i < len; i++) { + hal_diag_write_char(diag_buf[i]); + } +} +#endif // CYGDBG_DIAG_BUF + + +//----------------------------------------------------------------------------- +// MBX board specific serial output; using GDB protocol by default: + + +#if defined(CYG_KERNEL_DIAG_SERIAL) + +void hal_diag_init(void) +{ + static int init = 0; + if (init) return; + init++; + // init the actual serial port + cyg_quicc_init_smc1(); +#ifndef CYG_HAL_STARTUP_ROM + // We are talking to GDB; ack the "go" packet! + cyg_quicc_smc1_uart_putchar('+'); +#endif +} + +void hal_diag_write_char_serial( char c ) +{ + unsigned long __state; + HAL_DISABLE_INTERRUPTS(__state) + cyg_quicc_smc1_uart_putchar(c); + HAL_RESTORE_INTERRUPTS(__state); +} + +#ifdef CYG_HAL_STARTUP_ROM +void hal_diag_write_char(char c) +{ +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + hal_diag_write_char_serial(c); +} + +#else // RAM start so encode for GDB + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + +#ifdef CYGDBG_DIAG_BUF + diag_putc(c); + if (!enable_diag_uart) return; +#endif // CYGDBG_DIAG_BUF + + // No need to send CRs + if( c == '\r' ) return; + + line[pos++] = c; + + if( c == '\n' || pos == sizeof(line) ) + { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + + HAL_DISABLE_INTERRUPTS(old); + + while(1) + { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for( i = 0; i < pos; i++ ) + { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + +#ifndef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + // only gobble characters if no interrupt handler to grab ^Cs + // is installed (which is exclusive with device driver use) + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + c = cyg_quicc_smc1_uart_rcvchar(); + + if( c == '+' ) + break; // a good acknowledge +#if 0 + if( c1 == 3 ) { + // Ctrl-C: breakpoint. + breakpoint(); + break; + } +#endif + // otherwise, loop round again +#else + break; +#endif + } + + pos = 0; + + // And re-enable interrupts + HAL_RESTORE_INTERRUPTS(old); + + } +} +#endif // NOT def CYG_HAL_STARTUP_ROM + + +void hal_diag_read_char(char *c) +{ + *c = cyg_quicc_smc1_uart_rcvchar(); +} + +#endif // CYG_KERNEL_DIAG_SERIAL + +// EOF hal_diag.c
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/src/mbx.S @@ -0,0 +1,653 @@ +##============================================================================= +## +## mbx.S +## +## MBX board hardware setup +## +##============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +##============================================================================= +#######DESCRIPTIONBEGIN#### +## +## Author(s): hmt +## Contributors:hmt +## Date: 1999-06-08 +## Purpose: MBX board hardware setup +## Description: This file contains any code needed to initialize the +## hardware on a MBX860 or 821 PowerPC board. +## +######DESCRIPTIONEND#### +## +##============================================================================= + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <pkgconf/hal_powerpc.h> +#include <pkgconf/hal_powerpc_mbx.h> + +#include <cyg/hal/ppc.inc> /* register symbols et al */ +#include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */ + /* registers, IMM layout... */ +#include <cyg/hal/quicc/ppc8xx.h> /* more of the same */ + +#------------------------------------------------------------------------------ +# this is kept thus for commonality with CygMon code + +#if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define __40MHZ 1 +#elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define __50MHZ 1 +#else +# error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H +#endif + +#------------------------------------------------------------------------------ +# this is controlled with one define for tidiness: +# (and it is undefined by default) + +//#define CYGPRI_RAM_START_PROGRAMS_UPMS + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYGPRI_RAM_START_PROGRAMS_UPMS) +# define CYGPRI_DO_PROGRAM_UPMS +#endif + +#if defined(CYGPRI_RAM_START_PROGRAMS_UPMS) && defined(CYG_HAL_ROM_MONITOR) +/* use old tables in a StubROM build iff RAM start will reprogram them */ +# define CYGPRI_USE_OLD_UPM_TABLES +#endif + +/* The intention is that we only set up the UPMs in ROM start, be it actual + * ROM application start or Stub ROMs that we built from the same sources. + * + * The alternative approach - in which we have reliability doubts - is to + * program the UPMs with *old* timing data in StubROM start, then + * *reprogram* them with *new* timing data in RAM start - and of course + * program with *new* timing data in plain ROM application start. + * (Re-programming from new to new timing data fails - hence the suspicion + * of reprogramming _at_all_, hence this private configuration) + * + * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour + * - programming the UPMs exactly once - is obtained. Define it to get the + * latter, untrusted behaviour. + */ + +#------------------------------------------------------------------------------ + +// LED macro uses r3, r5: r4 left alone +#define LED( x ) \ + lwi r5,0xfa100001; \ + lwi r3,((x) & 0xe); \ + stb r3,0(r5) + + +#------------------------------------------------------------------------------ + +FUNC_START( hal_hardware_init ) + + # Throughout this routine, r4 is the base address of the control + # registers. r3 and r5 are scratch in general. + + lwi r4,CYGARC_REG_IMM_BASE # base address of control registers + mtspr CYGARC_REG_IMMR,r4 + + LED( 0 ) # turn all LEDs on + +#define CACHE_UNLOCKALL 0x0a00 +#define CACHE_DISABLE 0x0400 +#define CACHE_INVALIDATEALL 0x0c00 +#define CACHE_ENABLE 0x0200 +#define CACHE_ENABLEBIT 0x8000 + +#define CACHE_FORCEWRITETHROUGH 0x0100 +#define CACHE_NOWRITETHROUGH 0x0300 +#define CACHE_CLEAR_LE_SWAP 0x0700 + + # DATA CACHE + mfspr r3,CYGARC_REG_DC_CST /* clear error bits */ + lis r3,CACHE_UNLOCKALL + sync + mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */ + + lis r3,CACHE_INVALIDATEALL + sync + mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */ + + lis r3,CACHE_DISABLE + sync + mtspr CYGARC_REG_DC_CST,r3 /* disable */ + + lis r3,CACHE_FORCEWRITETHROUGH + sync + mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */ + + lis r3,CACHE_CLEAR_LE_SWAP + sync + mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */ + /* (dunno what this is, but it sounds like a bad thing) */ + + # INSTRUCTION CACHE (no writeback modes) + mfspr r3,CYGARC_REG_IC_CST /* clear error bits */ + lis r3,CACHE_UNLOCKALL + mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */ + isync + lis r3,CACHE_INVALIDATEALL + mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */ + isync + lis r3,CACHE_DISABLE + mtspr CYGARC_REG_IC_CST,r3 /* disable */ + isync + + sync + + /* + * SIU Initialization. + */ +/* lwi r3,0x0062A900*/ +/* lwi r3,0x006A2900*/ + lwi r3,0x00602400 + stw r3,SIUMCR(r4) + + /* + * Enable bus monitor. Disable Watchdog timer. + */ + lwi r3,0xffffff88 + stw r3,SYPCR(r4) + + /* + * Clear REFA & REFB. Enable but freeze timebase. + */ + lwi r3,0x00c2 + sth r3,TBSCR(r4) + + /* + * Unlock some RTC registers (see section 5.11.2) + */ + lwi r3,0x55ccaa33 + stw r3,RTCSCK(r4) + stw r3,RTCK(r4) + stw r3,RTSECK(r4) + stw r3,RTCALK(r4) + + /* + * Clear SERC & ALR. RTC runs on freeze. Enable RTC. + */ + li r3,0x00c3 + sth r3,RTCSC(r4) + + /* + * Clear periodic timer interrupt status. + * Enable periodic timer and stop it on freeze. + */ + li r3,0x0083 + sth r3,PISCR(r4) + +#ifdef CYGPRI_DO_PROGRAM_UPMS + /* + * Perform UPM programming by writing to its 64 RAM locations. + * Note that UPM initialization must be done before the Bank Register + * initialization. Otherwise, system may hang when writing to Bank + * Registers in certain cases. + */ + lis r5,__upmtbl_start@h + ori r5,r5,__upmtbl_start@l + lis r6,__upmtbl_end@h + ori r6,r6,__upmtbl_end@l + sub r7,r6,r5 /* size of table */ + srawi r7,r7,2 /* in words */ + + li r6,0x0000 /* Command - OP=Write, UPMA, MAD=0 */ + 1: + lwz r3,0(r5) /* get data from table */ + stw r3,MDR(r4) /* store the data to MD register */ + stw r6,MCR(r4) /* issue command to MCR register */ + addi r5,r5,4 /* next entry in the table */ + addi r6,r6,1 /* next MAD address */ + cmpw r6,r7 /* done yet ? */ + blt 1b +#endif // CYGPRI_DO_PROGRAM_UPMS + + /* + * Set refresh timer prescaler to divide by 8. + */ + li r3,PTP_DIV32 + sth r3,MPTPR(r4) + + /* + * See Table 15-16 MPC860 User's Manual. + * + * PTA = 0x13 (clock dependent) + * PTAE = enabled + * AMA = 0 + * DSA = 2 cycle disable + * G0CLA = A12 + * GPL_A4DIS = 0 + * RLFA = 0 + * WLFA = 0 + * TLFA = 0 + */ +#ifdef __50MHZ + lwi r3,0x18801000 +#else + lwi r3,0x13801000 +#endif + stw r3,MAMR(r4) + + /* + * Base Register initialization. + */ + /* BOOT ROM */ + lwi r3,0xfe000401 # 8-bit, GPCM +#ifdef __50MHZ + lwi r5,0xff800960 /* for 120nS devices, else 0xff800940 */ +#else + lwi r5,0xff800930 +#endif + stw r3,BR0(r4) + stw r5,OR0(r4) + + /* ONBOARD DRAM */ + lwi r3,0x00000081 # 32-bit, UPMA + lwi r5,0xffc00400 + stw r3,BR1(r4) + stw r5,OR1(r4) + + /* DRAM DIMM BANK0 */ + lwi r3,0x00000080 # 32-bit, UPMA, INVALID + lwi r5,0x00000400 + stw r3,BR2(r4) + stw r5,OR2(r4) + + /* DRAM DIMM BANK1 */ + lwi r3,0x00000080 # 32-bit, UPMA, INVALID + lwi r5,0x00000400 + stw r3,BR3(r4) + stw r5,OR3(r4) + + /* NVRAM */ + lwi r3,0xfa000401 # 8-bit, GPCM +#ifdef __50MHZ + lwi r5,0xffe00930 +#else + lwi r5,0xffe00920 +#endif + stw r3,BR4(r4) + stw r5,OR4(r4) + + /* PCI BRIDGE MEM/IO */ + lwi r3,0x80000001 # 32-bit, GPCM + lwi r5,0xa0000108 + stw r3,BR5(r4) + stw r5,OR5(r4) + + /* PCI BRIDGE REGISTERS */ + lwi r3,0xfa210001 # 32-bit, GPCM + lwi r5,0xffff0108 + stw r3,BR6(r4) + stw r5,OR6(r4) + + /* FLASH */ + lwi r3,0xfc000001 # 32-bit, GPCM +#ifdef __50MHZ + lwi r5,0xff800940 +#else + lwi r5,0xff800930 +#endif + stw r3,BR7(r4) + stw r5,OR7(r4) + + /* + * SYSTEM CLOCK CONTROL REGISTER + * + * COM (1:2) = 0 + * TBS (6) = 1 + * RTDIV (7) = 0 + * RTSEL (8) = 0 + * CRQEN (9) = 0 + * PRQEN (10) = 0 + * EBDF (13:14) = 0 + * DFSYNC(17:18) = 0 + * DFBRG (19:20) = 0 + * DFNL (21:23) = 0 + * DFNH (24:26) = 0 + */ + lwi r3,0x02000000 + stw r3,SCCR(r4) + + /* + * The following sets up a 40MHz CPU clock. + * I've seen 2 variations of MBX boards. One + * uses a direct feed (1:1) 40MHz clock on + * EXTCLK inputs. The other uses a 32KHz + * oscillator on the OSCM inputs. + */ + lwz r3,PLPRCR(r4) + rlwinm r3,r3,12,20,31 + cmpwi r3,0 + beq 1f + + /* + * PLL, LOW POWER, AND RESET CONTROL REGISTER + * + * MF (0:11) = depends on source clock + * SPLSS (16) = 1 + * TEXPS (17) = 1 + * TMIST (19) = 1 + * CSRC (21) = 0 + * LPM (22:23) = 0 + * CSR (24) = 0 + * LOLRE (25) = 0 + * FIOPD (26) = 0 + */ + /* MF (0:11) = 0x4c4 = 1220 = (40MHz/32.768KHz) */ +#ifdef __50MHZ + lwi r3,0x5f50d000 +#else + lwi r3,0x4c40d000 +#endif + b 2f + 1: + /* MF (0:11) = 0x000 = 1 = (1:1) */ + lwi r3,0x0000d000 + 2: + stw r3,PLPRCR(r4) + + # mask interrupt sources in the SIU + lis r2,0 + lwi r3,CYGARC_REG_IMM_SIMASK + stw r2,0(r3) + + # set the decrementer to maxint + lwi r2,0 + not r2,r2 + mtdec r2 + + # and enable the timebase and decrementer to make sure + li r2,1 # TBEnable and not TBFreeze + lwi r3,CYGARC_REG_IMM_TBSCR + sth r2,0(r3) + + LED( 8 ) # turn red led off + +#ifdef CYG_HAL_STARTUP_ROM + # move return address to where the ROM is + mflr r3 + andi. r3,r3,0xffff + oris r3,r3,0xfe00 + mtlr r3 +#endif + + blr +FUNC_END( hal_hardware_init ) + + +#ifdef CYGPRI_DO_PROGRAM_UPMS +# ------------------------------------------------------------------------- +# this table initializes the User Programmable Machine (UPM) nastiness +# in the QUICC to control DRAM timing. + +__upmtbl_start: + +#ifdef __25MHZ + /* UPM contents for 25MHz clk. DRAM: EDO,4K,60ns */ + + /* Single read. (offset 0 in upm RAM) */ + .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst read. (offset 8 in upm RAM) */ + .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08 + .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08 + .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Single write. (offset 18 in upm RAM) */ + .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x33ff6c0f + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst write. (offset 20 in upm RAM) */ + .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x03ff2c0c + .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c + .long 0x08ff2c00, 0x33ff6c0f, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Refresh (offset 30 in upm RAM) */ + .long 0xc0ffec04, 0x07ffec04, 0x3fffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Exception. (offset 3c in upm RAM) */ + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 +#endif + +#ifdef __33MHZ + /* UPM contents for 33MHz clk. DRAM: EDO,4K,60ns */ + + /* Single read. (offset 0 in upm RAM) */ + .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst read. (offset 8 in upm RAM) */ + .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08 + .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08 + .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Single write. (offset 18 in upm RAM) */ + .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x33ff6c07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst write. (offset 20 in upm RAM) */ + .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x03ff2c0c + .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c + .long 0x08ff2c00, 0x33ff6c07, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Refresh (offset 30 in upm RAM) */ + .long 0xc0ffec04, 0x03ffec04, 0x1fffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Exception. (offset 3c in upm RAM) */ + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 +#endif + +#ifdef CYGPRI_USE_OLD_UPM_TABLES + + // BUT new tables received from motorola are further down + + // And I just discovered a good reason for using the NEW TABLES: + // with the old tables, the cache zero-a-line command does not + // work. It only zeros the first 12 bytes of the line, not all 16. + // This may be related to having the cache set up write-through, as + // seems necessary to have it work on this platform. + +#ifdef __40MHZ + /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */ + + /* Single read. (offset 0 in upm RAM) */ + .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04 + .long 0x03af2c08, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst read. (offset 8 in upm RAM) */ + .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04 + .long 0x03af2c08, 0x0caf2c04, 0x00af2c04, 0x03af2c08 + .long 0x0caf2c04, 0x00af2c04, 0x03af2c08, 0x0caf2c04 + .long 0x00af2c04, 0x03af2c08, 0xffffec07, 0xffffec07 + + /* Single write. (offset 18 in upm RAM) */ + .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst write. (offset 20 in upm RAM) */ + .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00 + .long 0x0fff2c0c, 0x0cff2c00, 0x03ff2c0c, 0x0cff2c00 + .long 0x03ff2c0c, 0x0cff2c00, 0x33ff6c07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Refresh (offset 30 in upm RAM) */ + .long 0xf0ffec04, 0x00ffec04, 0x0fffec04, 0x0fffec04 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Exception. (offset 3c in upm RAM) */ + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 +#endif + +#ifdef __50MHZ + /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */ + + /* Single read. (offset 0 in upm RAM) */ + .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04 + .long 0x00af2c04, 0x0faf2c08, 0xffffec07, 0xffffec07 + + /* Burst read. (offset 8 in upm RAM) */ + .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04 + .long 0x00af2c04, 0x0faf2c08, 0x0caf2c04, 0x00af2c04 + .long 0x0faf2c08, 0x0caf2c04, 0x00af2c04, 0x0faf2c08 + .long 0x0caf2c04, 0x00af2c04, 0x0faf2c08, 0xffffec07 + + /* Single write. (offset 18 in upm RAM) */ + .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04 + .long 0x00ff2c00, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Burst write. (offset 20 in upm RAM) */ + .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04 + .long 0x00ff2c00, 0x0fff2c08, 0x0cff2c04, 0x00ff2c00 + .long 0x0fff2c00, 0x0cff2c04, 0x00ff2c00, 0x0fff2c08 + .long 0x0cff2c04, 0x00ff2c00, 0xffffec07, 0xffffec07 + + /* Refresh (offset 30 in upm RAM) */ + .long 0xf0ffec04, 0xc0ffec04, 0x00ffec04, 0x0fffec04 + .long 0x1fffec07, 0xffffec07, 0xffffec07, 0xffffec07 + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 + + /* Exception. (offset 3c in upm RAM) */ + .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07 +#endif + +#else // !CYGPRI_USE_OLD_UPM_TABLES: use the NEW TABLES + + // for RAM startup or ROM application when NOT making a stub rom, + // ie. CYG_HAL_ROM_MONITOR not defined. + +#ifdef __40MHZ + /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */ + .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x30af0c00 + .long 0xf1bf4805, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x03af0c08 + .long 0x0caf0c04, 0x03af0c08, 0x0caf0c04, 0x03af0c08 + .long 0x0caf0c04, 0x30af0c00, 0xf3bf4805, 0xffffc005 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x33ff4804 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c + .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c + .long 0x0cff0c00, 0x33ff4804, 0xffffc005, 0xffffc005 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004 + .long 0x3fffc004, 0xffffc005, 0xffffc005, 0xffffc005 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007 +#endif + +#ifdef __50MHZ + /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */ + + .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x10af0c04 + .long 0xf0af0c00, 0xf3bf4805, 0xffffc005, 0xffffc005 + + .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x00af0c04 + .long 0x07af0c08, 0x0caf0c04, 0x01af0c04, 0x0faf0c08 + .long 0x0caf0c04, 0x01af0c04, 0x0faf0c08, 0x0caf0c04 + .long 0x10af0c04, 0xf0afc000, 0xf3bf4805, 0xffffc005 + + .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x13ff4804 + .long 0xffffc004, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c + .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c + .long 0x0cff0c00, 0x13ff4804, 0xffffc004, 0xffffc005 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004 + .long 0x1fffc004, 0xffffc004, 0xffffc005, 0xffffc005 + .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005 + + .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007 +#endif +#endif // OLD/NEW TABLES == CYGPRI_USE_OLD_UPM_TABLES or not. + // depending on CYG_HAL_ROM_MONITOR and whether RAM + // start re-initializes. + +__upmtbl_end: +#endif // CYGPRI_DO_PROGRAM_UPMS + +FUNC_START(hal_mbx_set_led) + andi. r3,r3,0x0e + lwi r4,0xfa100001 + stb r3,0(r4) + blr +FUNC_END(hal_mbx_set_led) + +FUNC_START(hal_mbx_flash_led) + lwi r4,0xfa100001 + 1: + li r5,10 + stb r5,0(r4) + + lis r5,10 + mtctr r5 + 2: + bdnz 2b + + li r5,12 + stb r5,0(r4) + + lis r5,10 + mtctr r5 + 3: + bdnz 3b + + subi r3,r3,1 + cmpwi r3,0 + bge 1b + + li r5,6 + stb r5,0(r4) + + lis r5,20 + mtctr r5 + 4: + bdnz 4b + + blr +FUNC_END(hal_mbx_flash_led) + + +#------------------------------------------------------------------------------ +# end of mbx.S
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/tests/PKGconf.mak @@ -0,0 +1,40 @@ +#============================================================================= +# +# makefile +# +# hal/powerpc/mbx/tests +# +#============================================================================= +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================= + + +PACKAGE := hal_powerpc_mbx +include ../../../../../pkgconf/pkgconf.mak + +TESTS := mbxtime + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst + + +
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/mbx/current/tests/mbxtime.cxx @@ -0,0 +1,190 @@ +/*================================================================= +// +// mbxtime.cxx +// +// PowerPC MBX HAL timing tests +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-06-01 +//####DESCRIPTIONEND#### +*/ + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> + +#include <cyg/infra/cyg_type.h> +#include <cyg/infra/cyg_ass.h> +#include <cyg/infra/testcase.h> + +#ifdef CYGPKG_KERNEL + +#include <pkgconf/kernel.h> + +#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK + +#include <cyg/hal/hal_arch.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/hal/hal_diag.h> + +#include <pkgconf/infra.h> + +#include <cyg/infra/diag.h> + +#include <cyg/kernel/thread.hxx> +#include <cyg/kernel/thread.inl> +#include <cyg/kernel/sched.hxx> +#include <cyg/kernel/sched.inl> + +// ------------------------------------------------------------------------ + +externC void hal_mbx_flash_led( int count ); +externC void hal_mbx_set_led( int val ); + +// ------------------------------------------------------------------------- + +static void entry1( CYG_ADDRWORD arg ) +{ + int i; + char *s = "tick 00"; + extern Cyg_Thread thread2; + CYG_TEST_INFO( "Starting measured seconds..." ); + for ( i = 0; i < 20 ; i++ ) { + Cyg_Thread::self()->delay( 100 ); // units should be centiSeconds + + hal_mbx_set_led( ((~i) & 7)<<1 ); + + if ( '9' == s[ 6 ]++ ) { + s[ 6 ] = '0'; + s[ 5 ] ++; + } + CYG_TEST_INFO( s ); + } + + CYG_TEST_PASS( "Done measured seconds..." ); + + hal_mbx_flash_led( 5 ); + + thread2.resume(); +} + +//--------------------------------------------------------------- + +#define LOOPS 30 + +int loops[ LOOPS ] = { 0,0,0,0,0 , 0,0,0,0,0 , + 0,0,0,0,0 , 0,0,0,0,0 , + 0,0,0,0,0 , 0,0,0,0,0 }; + +char s[] = "0 count 00 loops 00000"; + +static void entry2( CYG_ADDRWORD arg ) +{ +#if 0 // Do not bother with this on PPC + int i, t1, t2, a; + for ( a = 0; a < 10; a++, (*s)++ ) { + CYG_TEST_INFO( "------------------------------------------" ); + HAL_CLOCK_READ( &t1 ); + do { + t2 = t1; + HAL_CLOCK_READ( &t1 ); + } while ( t1 >= t2 ); + + for ( i = 0; i < LOOPS; i++ ) { + register int z = 0; + while ( t1 <= i ) { + z++; + HAL_CLOCK_READ( &t1 ); + } + loops[ i ] = z; + } + + s[9] = '0'; + s[8] = '0'; + for ( i = 0; i < LOOPS; i++ ) { + s[ sizeof( s ) - 2 ] = '0' + loops[ i ] / 1 % 10; + s[ sizeof( s ) - 3 ] = '0' + loops[ i ] / 10 % 10; + s[ sizeof( s ) - 4 ] = '0' + loops[ i ] / 100 % 10; + s[ sizeof( s ) - 5 ] = '0' + loops[ i ] / 1000 % 10; + s[ sizeof( s ) - 6 ] = '0' + loops[ i ] / 10000 % 10; + CYG_TEST_INFO( s ); + if ( '9' == s[9]++ ) { + s[9] = '0'; + s[8]++; + } + } + } +#endif + CYG_TEST_PASS( "Counted loops per timer tick" ); + CYG_TEST_EXIT( "All done" ); +} + +// ------------------------------------------------------------------------- + +static char stack1[ CYGNUM_HAL_STACK_SIZE_TYPICAL ]; +static char stack2[ CYGNUM_HAL_STACK_SIZE_TYPICAL ]; + +static Cyg_Thread thread1 CYG_INIT_PRIORITY( APPLICATION ) + = Cyg_Thread( 2u, entry1, 0u, "timed minute thread", + (CYG_ADDRWORD)stack1, + (CYG_ADDRWORD)CYGNUM_HAL_STACK_SIZE_TYPICAL ); + +static Cyg_Thread thread2 CYG_INIT_PRIORITY( APPLICATION ) + = Cyg_Thread( 4u, entry2, 0u, "uS clock loops timing thread", + (CYG_ADDRWORD)stack2, + (CYG_ADDRWORD)CYGNUM_HAL_STACK_SIZE_TYPICAL ); + +// ------------------------------------------------------------------------- + +externC void +cyg_user_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_INFO( "cyg_user_start()" ); + thread1.resume(); +} + +// ------------------------------------------------------------------------- + +#else // ! CYGVAR_KERNEL_COUNTERS_CLOCK +#define N_A_MSG "no kernel clock" +#endif // CYGVAR_KERNEL_COUNTERS_CLOCK +#else // ! CYGPKG_KERNEL +#define N_A_MSG "no kernel" +#endif // CYGPKG_KERNEL + +#ifdef N_A_MSG +externC void +cyg_start( void ) +{ + CYG_TEST_INIT(); + CYG_TEST_NA( N_A_MSG ); +} +#endif // N_A_MSG defined ie. we are N/A. + +/* EOF mbxtime.cxx */
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/ChangeLog @@ -0,0 +1,86 @@ +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/quicc_smc1.c: Many changes which allow these routines to + cooperate when the SMC is being used by a serial "driver" as well. + In particular, remove "hard coded" resources on the SMC. + Note: there is some lingering problem with the transmit routines + [globally] after the serial driver re-inits the SMC. Of course + this problem is intermittent, so it's hard to fix. + +1999-06-24 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c (cyg_hal_gdb_isr): Add this routine to trap ^C + events and stop the system, if CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT. + +1999-06-24 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c (cyg_quicc_init_smc1): Remove unused, commented + out code, that was left over from CygMon version of this file. + +1999-06-18 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c (init_smc1_uart): Use default 38400 Baud, + because it is better. + +1999-06-18 Jesper Skov <jskov@cygnus.co.uk> + + * include/pkgconf/hal_quicc.h: Fixed CDL description. + +1999-06-17 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c (init_smc1_uart): Initialize the baud rate + depending on the system clock setting. + +1999-06-15 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c: Moved include of ppc8xx.h + + * src/ppc8xx.h: Removed, to... + + * include/ppc8xx.h: New file. Moved here so that platform startup + code can share it. + +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * src/quicc_smc1.c: Make this file safe for compilation even when + no PowerPC 860 is in use; pkgconf can enable this component for + any target, potentially. + +1999-06-10 Hugo Tyson <hmt@cygnus.co.uk> + + * ChangeLog: Component created, based partly on the FADS work and + on CygMon's serial IO code for the MBX860, to support the Motorola + MBX860 QUICC serial controller for basic IO. + Initially only used in the neighbouring platform component + HAL_POWERPC_MBX [hal/powerpc/mbx/....] + + * include/quicc_smc1.h + * include/pkgconf/hal_quicc.h + * src/PKGconf.mak + * src/ppc8xx.h + * src/quicc_smc1.c + New files. + +//=========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/include/pkgconf/hal_quicc.h @@ -0,0 +1,65 @@ +#ifndef CYGONCE_PKGCONF_HAL_QUICC_H +#define CYGONCE_PKGCONF_HAL_QUICC_H +//============================================================================= +// +// pkgconf/hal_quicc.h +// +// HAL configuration file +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): hmt +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: To allow the user to edit HAL configuration options. +// Description: +// +//####DESCRIPTIONEND#### +// +//============================================================================= + + +/* --------------------------------------------------------------------- + {{CFG_DATA + + cdl_package CYGPKG_HAL_QUICC { + display "Motorola MBX PowerQUICC support" + type bool + parent CYGPKG_HAL_POWERPC + description " + The QUICC package provides some of the support needed + to run eCos on a Motorola MBX board, using the QUICC + feature of the MPC860 and MPC821 CPUs. + Currently only serial IO via SMC1 is provided by + this package." + } + + }}CFG_DATA */ + +/* -------------------------------------------------------------------*/ + +#endif /* CYGONCE_PKGCONF_HAL_QUICC_H */ +/* EOF hal_quicc.h */
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/include/ppc8xx.h @@ -0,0 +1,931 @@ +#ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H +#define CYGONCE_HAL_PPC_QUICC_PPC8XX_H + +//========================================================================== +// +// ppc8xx.h +// +// PowerPC QUICC register definitions +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): cygnus +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: Provide PPC QUICC definitions +// Description: Provide PPC QUICC definitions +// Usage: THIS IS NOT AN EXTERNAL API +// This file is in the include dir to share it between +// QUICC serial code and MBX initialization code. +// #include <cyg/hal/quicc/ppc8xx.h> +// ... +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifdef __ASSEMBLER__ + +#define SIUMCR 0x000 /* SIU Module configuration */ +#define SYPCR 0x004 /* SIU System Protection Control */ +#define SIPEND 0x010 /* SIU Interrupt Pending Register */ +#define SIMASK 0x014 /* SIU Interrupt MASK Register */ +#define SIEL 0x018 /* SIU Interrupt Edge/Level Register */ +#define SIVEC 0x01C /* SIU Interrupt Vector Register */ +#define SDCR 0x030 /* SDMA Config Register */ +#define BR0 0x100 /* Base Register 0 */ +#define OR0 0x104 /* Option Register 0 */ +#define BR1 0x108 /* Base Register 1 */ +#define OR1 0x10C /* Option Register 1 */ +#define BR2 0x110 /* Base Register 2 */ +#define OR2 0x114 /* Option Register 2 */ +#define BR3 0x118 /* Base Register 2 */ +#define OR3 0x11C /* Option Register 2 */ +#define BR4 0x120 /* Base Register 2 */ +#define OR4 0x124 /* Option Register 2 */ +#define BR5 0x128 /* Base Register 2 */ +#define OR5 0x12C /* Option Register 2 */ +#define BR6 0x130 /* Base Register 2 */ +#define OR6 0x134 /* Option Register 2 */ +#define BR7 0x138 /* Base Register 2 */ +#define OR7 0x13C /* Option Register 2 */ +#define MCR 0x168 /* Memory Command */ +#define MAMR 0x170 /* Machine A Mode Register */ +#define MPTPR 0x17A /* Memory Periodic Timer Prescaler */ +#define MDR 0x17C /* Memory Data */ +#define TBSCR 0x200 /* Time Base Status and Control Register */ +#define RTCSC 0x220 /* Real Timer Clock Status and Control */ +#define PISCR 0x240 /* PIT Status and Control */ +#define SCCR 0x280 /* System Clock Control Register */ +#define PLPRCR 0x284 /* PLL, Low power & Reset Control Register */ +#define RTCSCK 0x320 +#define RTCK 0x324 +#define RTSECK 0x328 +#define RTCALK 0x32C + +#else + +/***************************************************************** + Communications Processor Buffer Descriptor +*****************************************************************/ +struct cp_bufdesc { + volatile unsigned short ctrl; /* status/control register */ + volatile unsigned short length; /* buffer length */ + volatile char *buffer; /* buffer pointer */ +}; + +/***************************************************************** + HDLC parameter RAM +*****************************************************************/ + +struct hdlc_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * HDLC specific parameter RAM + */ + unsigned char RSRVD1[4]; + unsigned long c_mask; /* CRC constant */ + unsigned long c_pres; /* CRC preset */ + unsigned short disfc; /* discarded frame counter */ + unsigned short crcec; /* CRC error counter */ + unsigned short abtsc; /* abort sequence counter */ + unsigned short nmarc; /* nonmatching address rx cnt */ + unsigned short retrc; /* frame retransmission cnt */ + unsigned short mflr; /* maximum frame length reg */ + unsigned short max_cnt; /* maximum length counter */ + unsigned short rfthr; /* received frames threshold */ + unsigned short rfcnt; /* received frames count */ + unsigned short hmask; /* user defined frm addr mask */ + unsigned short haddr1; /* user defined frm address 1 */ + unsigned short haddr2; /* user defined frm address 2 */ + unsigned short haddr3; /* user defined frm address 3 */ + unsigned short haddr4; /* user defined frm address 4 */ + unsigned short tmp; /* temp */ + unsigned short tmp_mb; /* temp */ +}; + + +/***************************************************************** + ASYNC HDLC parameter RAM +*****************************************************************/ + +struct async_hdlc_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * ASYNC HDLC specific parameter RAM + */ + unsigned char RSRVD1[4]; + unsigned long c_mask; /* CRC constant */ + unsigned long c_pres; /* CRC preset */ + unsigned short bof; /* begining of flag character */ + unsigned short eof; /* end of flag character */ + unsigned short esc; /* control escape character */ + unsigned char RSRVD2[4]; + unsigned short zero; /* zero */ + unsigned char RSRVD3[2]; + unsigned short rfthr; /* received frames threshold */ + unsigned char RSRVD4[4]; + unsigned long txctl_tbl; /* Tx ctl char mapping table */ + unsigned long rxctl_tbl; /* Rx ctl char mapping table */ + unsigned short nof; /* Number of opening flags */ +}; + + +/***************************************************************** + UART parameter RAM +*****************************************************************/ + +/* + * bits in uart control characters table + */ +#define CC_INVALID 0x8000 /* control character is valid */ +#define CC_REJ 0x4000 /* don't store char in buffer */ +#define CC_CHAR 0x00ff /* control character */ + +/* UART */ +struct uart_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rx_temp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * UART specific parameter RAM + */ + unsigned char RSRVD1[8]; + unsigned short max_idl; /* maximum idle characters */ + unsigned short idlc; /* rx idle counter (internal) */ + unsigned short brkcr; /* break count register */ + + unsigned short parec; /* Rx parity error counter */ + unsigned short frmer; /* Rx framing error counter */ + unsigned short nosec; /* Rx noise counter */ + unsigned short brkec; /* Rx break character counter */ + unsigned short brkln; /* Reaceive break length */ + + unsigned short uaddr1; /* address character 1 */ + unsigned short uaddr2; /* address character 2 */ + unsigned short rtemp; /* temp storage */ + unsigned short toseq; /* Tx out of sequence char */ + unsigned short cc[8]; /* Rx control characters */ + unsigned short rccm; /* Rx control char mask */ + unsigned short rccr; /* Rx control char register */ + unsigned short rlbc; /* Receive last break char */ +}; + + + +/***************************************************************** + BISYNC parameter RAM +*****************************************************************/ + +struct bisync_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * BISYNC specific parameter RAM + */ + unsigned char RSRVD1[4]; + unsigned long crcc; /* CRC Constant Temp Value */ + unsigned short prcrc; /* Preset Receiver CRC-16/LRC */ + unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */ + unsigned short parec; /* Receive Parity Error Counter */ + unsigned short bsync; /* BISYNC SYNC Character */ + unsigned short bdle; /* BISYNC DLE Character */ + unsigned short cc[8]; /* Rx control characters */ + unsigned short rccm; /* Receive Control Character Mask */ +}; + +/***************************************************************** + IOM2 parameter RAM + (overlaid on tx bd[5] of SCC channel[2]) +*****************************************************************/ +struct iom2_pram { + unsigned short ci_data; /* ci data */ + unsigned short monitor_data; /* monitor data */ + unsigned short tstate; /* transmitter state */ + unsigned short rstate; /* receiver state */ +}; + +/***************************************************************** + SPI/SMC parameter RAM + (overlaid on tx bd[6,7] of SCC channel[2]) +*****************************************************************/ + +#define SPI_R 0x8000 /* Ready bit in BD */ + +struct spi_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ +}; + +struct smc_uart_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned short max_idl; /* Maximum IDLE Characters */ + unsigned short idlc; /* Temporary IDLE Counter */ + unsigned short brkln; /* Last Rx Break Length */ + unsigned short brkec; /* Rx Break Condition Counter */ + unsigned short brkcr; /* Break Count Register (Tx) */ + unsigned short r_mask; /* Temporary bit mask */ +}; + +struct smc_trnsp_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned short RSRVD[5]; /* RSRVD */ +}; + +struct centronics_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char fcr; /* function code */ + unsigned char smask; /* Status Mask */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned short max_sl; /* Maximum Silence period */ + unsigned short sl_cnt; /* Silence Counter */ + unsigned short char1; /* CONTROL char 1 */ + unsigned short char2; /* CONTROL char 2 */ + unsigned short char3; /* CONTROL char 3 */ + unsigned short char4; /* CONTROL char 4 */ + unsigned short char5; /* CONTROL char 5 */ + unsigned short char6; /* CONTROL char 6 */ + unsigned short char7; /* CONTROL char 7 */ + unsigned short char8; /* CONTROL char 8 */ + unsigned short rccm; /* Rx Control Char Mask */ + unsigned short rccr; /* Rx Char Control Register */ +}; + +struct idma_pram { + unsigned short ibase; /* IDMA BD Base Address */ + unsigned short ibptr; /* IDMA buffer descriptor pointer */ + unsigned long istate; /* IDMA internal state */ + unsigned long itemp; /* IDMA temp */ +}; + +struct ethernet_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * ETHERNET specific parameter RAM + */ + unsigned long c_pres; /* preset CRC */ + unsigned long c_mask; /* constant mask for CRC */ + unsigned long crcec; /* CRC error counter */ + unsigned long alec; /* alighnment error counter */ + unsigned long disfc; /* discard frame counter */ + unsigned short pads; /* short frame PAD characters */ + unsigned short ret_lim; /* retry limit threshold */ + unsigned short ret_cnt; /* retry limit counter */ + unsigned short mflr; /* maximum frame length reg */ + unsigned short minflr; /* minimum frame length reg */ + unsigned short maxd1; /* maximum DMA1 length reg */ + unsigned short maxd2; /* maximum DMA2 length reg */ + unsigned short maxd; /* rx max DMA */ + unsigned short dma_cnt; /* rx dma counter */ + unsigned short max_b; /* max bd byte count */ + unsigned short gaddr1; /* group address filter 1 */ + unsigned short gaddr2; /* group address filter 2 */ + unsigned short gaddr3; /* group address filter 3 */ + unsigned short gaddr4; /* group address filter 4 */ + unsigned long tbuf0_data0; /* save area 0 - current frm */ + unsigned long tbuf0_data1; /* save area 1 - current frm */ + unsigned long tbuf0_rba0; + unsigned long tbuf0_crc; + unsigned short tbuf0_bcnt; + unsigned short paddr_h; /* physical address (MSB) */ + unsigned short paddr_m; /* physical address */ + unsigned short paddr_l; /* physical address (LSB) */ + unsigned short p_per; /* persistence */ + unsigned short rfbd_ptr; /* rx first bd pointer */ + unsigned short tfbd_ptr; /* tx first bd pointer */ + unsigned short tlbd_ptr; /* tx last bd pointer */ + unsigned long tbuf1_data0; /* save area 0 - next frame */ + unsigned long tbuf1_data1; /* save area 1 - next frame */ + unsigned long tbuf1_rba0; + unsigned long tbuf1_crc; + unsigned short tbuf1_bcnt; + unsigned short tx_len; /* tx frame length counter */ + unsigned short iaddr1; /* individual address filter 1*/ + unsigned short iaddr2; /* individual address filter 2*/ + unsigned short iaddr3; /* individual address filter 3*/ + unsigned short iaddr4; /* individual address filter 4*/ + unsigned short boff_cnt; /* back-off counter */ + unsigned short taddr_h; /* temp address (MSB) */ + unsigned short taddr_m; /* temp address */ + unsigned short taddr_l; /* temp address (LSB) */ +}; + +struct transparent_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * TRANSPARENT specific parameter RAM + */ + unsigned long crc_p; /* CRC Preset */ + unsigned long crc_c; /* CRC constant */ +}; + +struct timer_pram { + /* + * RISC timers parameter RAM + */ + unsigned short tm_base; /* RISC timer table base adr */ + unsigned short tm_ptr; /* RISC timer table pointer */ + unsigned short r_tmr; /* RISC timer mode register */ + unsigned short r_tmv; /* RISC timer valid register */ + unsigned long tm_cmd; /* RISC timer cmd register */ + unsigned long tm_cnt; /* RISC timer internal cnt */ +}; + +struct ucode_pram { + /* + * RISC ucode parameter RAM + */ + unsigned short rev_num; /* Ucode Revision Number */ + unsigned short d_ptr; /* MISC Dump area pointer */ + unsigned long temp1; /* MISC Temp1 */ + unsigned long temp2; /* MISC Temp2 */ +}; + +struct i2c_pram { + /* + * I2C parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ +}; + +/* + * definitions of EPPC memory structures + */ +typedef struct eppc { + /* BASE + 0x0000: INTERNAL REGISTERS */ + + /* SIU */ + volatile unsigned long siu_mcr; /* module configuration reg */ + volatile unsigned long siu_sypcr; /* System protection cnt */ + unsigned char RSRVD58[0x6]; + volatile unsigned short siu_swsr; /* sw service */ + volatile unsigned long siu_sipend; /* Interrupt pend reg */ + volatile unsigned long siu_simask; /* Interrupt mask reg */ + volatile unsigned long siu_siel; /* Interrupt edge level mask reg */ + volatile unsigned long siu_sivec; /* Interrupt vector */ + volatile unsigned long siu_tesr; /* Transfer error status */ + volatile unsigned char RSRVD1[0xc]; + volatile unsigned long dma_sdcr; /* SDMA configuration reg */ + unsigned char RSRVD55[0x4c]; + + /* PCMCIA */ + volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */ + volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */ + volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */ + volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */ + volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */ + volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */ + volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */ + volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */ + volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */ + volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */ + volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */ + volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */ + volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */ + volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */ + volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */ + volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */ + volatile unsigned char RSRVD2[0x20]; + volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */ + volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */ + volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */ + volatile unsigned char RSRVD2a[0x4]; + volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */ + volatile unsigned char RSRVD2b[0x4]; + volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */ + volatile unsigned char RSRVD2c[0x4]; + + /* MEMC */ + volatile unsigned long memc_br0; /* base register 0 */ + volatile unsigned long memc_or0; /* option register 0 */ + volatile unsigned long memc_br1; /* base register 1 */ + volatile unsigned long memc_or1; /* option register 1 */ + volatile unsigned long memc_br2; /* base register 2 */ + volatile unsigned long memc_or2; /* option register 2 */ + volatile unsigned long memc_br3; /* base register 3 */ + volatile unsigned long memc_or3; /* option register 3 */ + volatile unsigned long memc_br4; /* base register 3 */ + volatile unsigned long memc_or4; /* option register 3 */ + volatile unsigned long memc_br5; /* base register 3 */ + volatile unsigned long memc_or5; /* option register 3 */ + volatile unsigned long memc_br6; /* base register 3 */ + volatile unsigned long memc_or6; /* option register 3 */ + volatile unsigned long memc_br7; /* base register 3 */ + volatile unsigned long memc_or7; /* option register 3 */ + volatile unsigned char RSRVD3[0x24]; + volatile unsigned long memc_mar; /* Memory address */ + volatile unsigned long memc_mcr; /* Memory command */ + volatile unsigned char RSRVD4[0x4]; + volatile unsigned long memc_mamr; /* Machine A mode */ + volatile unsigned long memc_mbmr; /* Machine B mode */ + volatile unsigned short memc_mstat; /* Memory status */ + volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */ + volatile unsigned long memc_mdr; /* Memory data */ + volatile unsigned char RSRVD5[0x80]; + + /* SYSTEM INTEGRATION TIMERS */ + volatile unsigned short simt_tbscr; /* Time base stat&ctr */ + volatile unsigned char RSRVD100[0x2]; + volatile unsigned long simt_tbreff0; /* Time base reference 0 */ + volatile unsigned long simt_tbreff1; /* Time base reference 1 */ + volatile unsigned char RSRVD6[0x14]; + volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */ + volatile unsigned char RSRVD110[0x2]; + volatile unsigned long simt_rtc; /* Realtime clock */ + volatile unsigned long simt_rtsec; /* Realtime alarm seconds */ + volatile unsigned long simt_rtcal; /* Realtime alarm */ + volatile unsigned char RSRVD56[0x10]; + volatile unsigned long simt_piscr; /* PIT stat&ctrl */ + volatile unsigned long simt_pitc; /* PIT counter */ + volatile unsigned long simt_pitr; /* PIT */ + volatile unsigned char RSRVD7[0x34]; + + /* CLOCKS, RESET */ + volatile unsigned long clkr_sccr; /* System clk cntrl */ + volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */ + volatile unsigned long clkr_rsr; /* reset status */ + volatile unsigned char RSRVD66a[0x74]; + + /* System Integration Timers Keys */ + volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */ + volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */ + volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */ + volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */ + volatile unsigned char RSRVD66b[0x10]; + volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */ + volatile unsigned long simt_rtck; /* Real-Time Clock Key */ + volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */ + volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */ + volatile unsigned char RSRVD66c[0x10]; + volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */ + volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */ + volatile unsigned char RSRVD66d[0x38]; + + + /* Clock and Reset Keys */ + volatile unsigned long clkr_sccrk; /* System Clock Control Key */ + volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */ + volatile unsigned long clkr_rsrk; /* Reset Status Key */ + volatile unsigned char RSRVD66e[0x4b4]; + + volatile unsigned long lcd_lccr; /* configuration Reg */ + volatile unsigned long lcd_lchcr; /* Horizontal ctl Reg */ + volatile unsigned long lcd_lcvcr; /* Vertical ctl Reg */ + unsigned char RSRVD67[4]; + volatile unsigned long lcd_lcfaa; /* Frame buffer A Address */ + volatile unsigned long lcd_lcfba; /* Frame buffer B Address */ + volatile unsigned char lcd_lcsr; /* Status Reg */ + volatile unsigned char RSRVD9[0x7]; + + /* I2C */ + volatile unsigned char i2c_i2mod; /* i2c mode */ + unsigned char RSRVD59[3]; + volatile unsigned char i2c_i2add; /* i2c address */ + unsigned char RSRVD60[3]; + volatile unsigned char i2c_i2brg; /* i2c brg */ + unsigned char RSRVD61[3]; + volatile unsigned char i2c_i2com; /* i2c command */ + unsigned char RSRVD62[3]; + volatile unsigned char i2c_i2cer; /* i2c event */ + unsigned char RSRVD63[3]; + volatile unsigned char i2c_i2cmr; /* i2c mask */ + volatile unsigned char RSRVD10[0x8b]; + + /* DMA */ + volatile unsigned char RSRVD11[0x4]; + volatile unsigned long dma_sdar; /* SDMA address reg */ + volatile unsigned char dma_sdsr; /* SDMA status reg */ + volatile unsigned char RSRVD12[0x3]; + volatile unsigned char dma_sdmr; /* SDMA mask reg */ + volatile unsigned char RSRVD13[0x3]; + volatile unsigned char dma_idsr1; /* IDMA1 status reg */ + volatile unsigned char RSRVD14[0x3]; + volatile unsigned char dma_idmr1; /* IDMA1 mask reg */ + volatile unsigned char RSRVD15[0x3]; + volatile unsigned char dma_idsr2; /* IDMA2 status reg */ + volatile unsigned char RSRVD16[0x3]; + volatile unsigned char dma_idmr2; /* IDMA2 mask reg */ + volatile unsigned char RSRVD17[0x13]; + + /* CPM Interrupt Controller */ + volatile unsigned short cpmi_civr; /* CP interrupt vector reg */ + volatile unsigned char RSRVD19[0xe]; + volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */ + volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */ + volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */ + volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */ + + /* I/O port */ + volatile unsigned short pio_padir; /* port A data direction reg */ + volatile unsigned short pio_papar; /* port A pin assignment reg */ + volatile unsigned short pio_paodr; /* port A open drain reg */ + volatile unsigned short pio_padat; /* port A data register */ + volatile unsigned char RSRVD20[0x8]; + volatile unsigned short pio_pcdir; /* port C data direction reg */ + volatile unsigned short pio_pcpar; /* port C pin assignment reg */ + volatile unsigned short pio_pcso; /* port C special options */ + volatile unsigned short pio_pcdat; /* port C data register */ + volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */ + unsigned char RSRVD64[6]; + volatile unsigned short pio_pddir; /* port D Data Direction reg */ + volatile unsigned short pio_pdpar; /* port D pin assignment reg */ + unsigned char RSRVD65[2]; + volatile unsigned short pio_pddat; /* port D data reg */ + volatile unsigned char RSRVD21[0x8]; + + /* CPM Timer */ + volatile unsigned short timer_tgcr; /* timer global configuration reg */ + volatile unsigned char RSRVD22[0xe]; + volatile unsigned short timer_tmr1; /* timer 1 mode reg */ + volatile unsigned short timer_tmr2; /* timer 2 mode reg */ + volatile unsigned short timer_trr1; /* timer 1 referance reg */ + volatile unsigned short timer_trr2; /* timer 2 referance reg */ + volatile unsigned short timer_tcr1; /* timer 1 capture reg */ + volatile unsigned short timer_tcr2; /* timer 2 capture reg */ + volatile unsigned short timer_tcn1; /* timer 1 counter reg */ + volatile unsigned short timer_tcn2; /* timer 2 counter reg */ + volatile unsigned short timer_tmr3; /* timer 3 mode reg */ + volatile unsigned short timer_tmr4; /* timer 4 mode reg */ + volatile unsigned short timer_trr3; /* timer 3 referance reg */ + volatile unsigned short timer_trr4; /* timer 4 referance reg */ + volatile unsigned short timer_tcr3; /* timer 3 capture reg */ + volatile unsigned short timer_tcr4; /* timer 4 capture reg */ + volatile unsigned short timer_tcn3; /* timer 3 counter reg */ + volatile unsigned short timer_tcn4; /* timer 4 counter reg */ + volatile unsigned short timer_ter1; /* timer 1 event reg */ + volatile unsigned short timer_ter2; /* timer 2 event reg */ + volatile unsigned short timer_ter3; /* timer 3 event reg */ + volatile unsigned short timer_ter4; /* timer 4 event reg */ + volatile unsigned char RSRVD23[0x8]; + + /* CP */ + volatile unsigned short cp_cr; /* command register */ + volatile unsigned char RSRVD24[0x2]; + volatile unsigned short cp_rccr; /* main configuration reg */ + volatile unsigned char RSRVD25; + volatile unsigned char cp_resv1; /* RSRVD reg */ + volatile unsigned long cp_resv2; /* RSRVD reg */ + volatile unsigned short cp_rctr1; /* ram break register 1 */ + volatile unsigned short cp_rctr2; /* ram break register 2 */ + volatile unsigned short cp_rctr3; /* ram break register 3 */ + volatile unsigned short cp_rctr4; /* ram break register 4 */ + volatile unsigned char RSRVD26[0x2]; + volatile unsigned short cp_rter; /* RISC timers event reg */ + volatile unsigned char RSRVD27[0x2]; + volatile unsigned short cp_rtmr; /* RISC timers mask reg */ + volatile unsigned char RSRVD28[0x14]; + + /* BRG */ + volatile unsigned long brgc1; /* BRG1 configuration reg */ + volatile unsigned long brgc2; /* BRG2 configuration reg */ + volatile unsigned long brgc3; /* BRG3 configuration reg */ + volatile unsigned long brgc4; /* BRG4 configuration reg */ + + /* SCC registers */ + struct scc_regs { + volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */ + volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */ + volatile unsigned short scc_psmr; /* protocol specific mode register */ + volatile unsigned char RSRVD29[0x2]; + volatile unsigned short scc_todr; /* SCC transmit on demand */ + volatile unsigned short scc_dsr; /* SCC data sync reg */ + volatile unsigned short scc_scce; /* SCC event reg */ + volatile unsigned char RSRVD30[0x2]; + volatile unsigned short scc_sccm; /* SCC mask reg */ + volatile unsigned char RSRVD31[0x1]; + volatile unsigned char scc_sccs; /* SCC status reg */ + volatile unsigned char RSRVD32[0x8]; + } scc_regs[2]; + + volatile unsigned char RSRVD120[0x40]; + + /* SMC */ + struct smc_regs { + volatile unsigned char RSRVD34[0x2]; + volatile unsigned short smc_smcmr; /* SMC mode reg */ + volatile unsigned char RSRVD35[0x2]; + volatile unsigned char smc_smce; /* SMC event reg */ + volatile unsigned char RSRVD36[0x3]; + volatile unsigned char smc_smcm; /* SMC mask reg */ + volatile unsigned char RSRVD37[0x5]; + } smc_regs[2]; + + /* SPI */ + volatile unsigned short spi_spmode; /* SPI mode reg */ + volatile unsigned char RSRVD38[0x4]; + volatile unsigned char spi_spie; /* SPI event reg */ + volatile unsigned char RSRVD39[0x3]; + volatile unsigned char spi_spim; /* SPI mask reg */ + volatile unsigned char RSRVD40[0x2]; + volatile unsigned char spi_spcom; /* SPI command reg */ + volatile unsigned char RSRVD41[0x4]; + + /* PIP */ + volatile unsigned short pip_pipc; /* pip configuration reg */ + volatile unsigned char RSRVD42[0x2]; + volatile unsigned short pip_ptpr; /* pip timing parameters reg */ + volatile unsigned long pip_pbdir; /* port b data direction reg */ + volatile unsigned long pip_pbpar; /* port b pin assignment reg */ + volatile unsigned char RSRVD43[0x2]; + volatile unsigned short pip_pbodr; /* port b open drain reg */ + volatile unsigned long pip_pbdat; /* port b data reg */ + volatile unsigned char RSRVD44[0x18]; + + /* Serial Interface */ + volatile unsigned long si_simode; /* SI mode register */ + volatile unsigned char si_sigmr; /* SI global mode register */ + volatile unsigned char RSRVD45; + volatile unsigned char si_sistr; /* SI status register */ + volatile unsigned char si_sicmr; /* SI command register */ + volatile unsigned char RSRVD46[0x4]; + volatile unsigned long si_sicr; /* SI clock routing */ + volatile unsigned long si_sirp; /* SI ram pointers */ + volatile unsigned char RSRVD47[0x10c]; + volatile unsigned char si_siram[0x200];/* SI routing ram */ + volatile unsigned short lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */ + volatile unsigned char RSRVD48[0x1000]; + + /* BASE + 0x2000: user data memory */ + volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ + volatile unsigned char udata_bd[0x200]; /*user data Ucode*/ + volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram*/ + volatile unsigned char RSRVD49[0x1500]; + + /* BASE + 0x3c00: PARAMETER RAM */ + union { + struct scc_pram { + union { + struct hdlc_pram h; + struct uart_pram u; + struct bisync_pram b; + struct transparent_pram t; + struct async_hdlc_pram a; + unsigned char RSRVD50[0x80]; + } pscc; /* scc parameter area (protocol dependent) */ + + union { + struct { + struct i2c_pram i2c; + unsigned char RSRVD56[0x18]; + struct idma_pram idma1; + } i2c_idma; + struct { + struct spi_pram spi; + unsigned char RSRVD57[0x8]; + struct timer_pram timer; + struct idma_pram idma2; + } spi_timer_idma; + struct { + union { + struct smc_uart_pram u; + struct smc_trnsp_pram t; + struct centronics_pram c; + } psmc; + unsigned char modem_param[0x40]; + } smc_modem; + struct { + unsigned char RSRVD54[0x40]; + struct ucode_pram ucode; + } pucode; + } pothers; + } scc; + struct ethernet_pram enet_scc; + unsigned char pr[0x100]; + } pram[4]; +} EPPC; + + +static inline EPPC *eppc_base(void) +{ + EPPC *retval; + + asm volatile ( + "mfspr %0,638 \n\t" + "andis. %0,%0,65535 \n\t" + : "=r" (retval) + : /* no inputs */ ); + + return retval; +} + + + +#endif /* __ASSEMBLER__ */ + +/* Memory Periodic Timer Prescaler Register values */ +#define PTP_DIV2 0x2000 +#define PTP_DIV4 0x1000 +#define PTP_DIV8 0x0800 +#define PTP_DIV16 0x0400 +#define PTP_DIV32 0x0200 +#define PTP_DIV64 0x0100 + + +#endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/include/quicc_smc1.h @@ -0,0 +1,50 @@ +#ifndef CYGONCE_HAL_PPC_QUICC_SMC1_H +#define CYGONCE_HAL_PPC_QUICC_SMC1_H +//============================================================================= +// +// quicc_smc1.h +// +// PowerPC QUICC basic Serial IO using port SMC1 +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): cygnus +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: Provide basic Serial IO for MBX board +// Description: Serial IO for MBX boards which connect their debug channel +// to SMC1; or any QUICC user who wants to use SMC1. +// Usage: +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +extern void cyg_quicc_smc1_uart_putchar(char ch); +extern int cyg_quicc_smc1_uart_rcvchar(void); +extern void cyg_quicc_init_smc1(void); + +#endif /* CYGONCE_HAL_PPC_QUICC_SMC1_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/src/PKGconf.mak @@ -0,0 +1,41 @@ +#============================================================================== +# +# makefile +# +# hal/powerpc/quicc/src +# +#============================================================================== +#####COPYRIGHTBEGIN#### +# +# ------------------------------------------- +# The contents of this file are subject to the Cygnus eCos Public License +# Version 1.0 (the "License"); you may not use this file except in +# compliance with the License. You may obtain a copy of the License at +# http://sourceware.cygnus.com/ecos +# +# Software distributed under the License is distributed on an "AS IS" +# basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +# License for the specific language governing rights and limitations under +# the License. +# +# The Original Code is eCos - Embedded Cygnus Operating System, released +# September 30, 1998. +# +# The Initial Developer of the Original Code is Cygnus. Portions created +# by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +# ------------------------------------------- +# +#####COPYRIGHTEND#### +#============================================================================== + +PACKAGE := hal_quicc +include ../../../../../pkgconf/pkgconf.mak + +LIBRARY := libtarget.a +COMPILE := quicc_smc1.c +OTHER_OBJS := +OTHER_TARGETS := +OTHER_CLEAN := +OTHER_DEPS := + +include $(COMPONENT_REPOSITORY)/pkgconf/makrules.src
new file mode 100644 --- /dev/null +++ b/packages/hal/powerpc/quicc/current/src/quicc_smc1.c @@ -0,0 +1,395 @@ +//========================================================================== +// +// quicc_smc1.c +// +// PowerPC QUICC basic Serial IO using port SMC1 +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): cygnus +// Contributors: hmt +// Date: 1999-06-08 +// Purpose: Provide basic Serial IO for MBX board +// Description: Serial IO for MBX boards which connect their debug channel +// to SMC1; or any QUICC user who wants to use SMC1. +// Usage: +// +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/hal.h> +#include <cyg/infra/cyg_type.h> +#include <cyg/hal/hal_cache.h> + +#ifdef CYG_HAL_POWERPC_MPC860 + +#include CYGBLD_HAL_TARGET_H +#include CYGBLD_HAL_PLATFORM_H + +// eCos headers decribing PowerQUICC: +#include <cyg/hal/quicc/ppc8xx.h> + +#include <cyg/hal/quicc/quicc_smc1.h> + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +#include <cyg/hal/hal_stub.h> // target_register_t +#include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK(...) +#endif + +#if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define __40MHZ 1 +#elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED +# define __50MHZ 1 +#else +# error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H +#endif + +#define USE38400BAUD // otherwise it uses 9600 by default + +#define Rxbd 0x2800 /* Rx Buffer Descriptor Offset */ +#define Txbd 0x2808 /* Tx Buffer Descriptor Offset */ + +#define Rxbuf ((volatile char *)eppc + 0x2810) +#define Txbuf ((volatile char *)eppc + 0x2820) + + +/* + * Initialize SMC1 as a uart. + * + * Comments below reference Motorola's "MPC860 User Manual". + * The basic initialization steps are from Section 16.15.8 + * of that manual. + */ +static void +init_smc1_uart(void) +{ + EPPC *eppc; + volatile struct smc_uart_pram *uart_pram; + struct cp_bufdesc *txbd, *rxbd; + + static int init_done = 0; + if (init_done) return; + init_done++; + + eppc = eppc_base(); + + /* SMC1 Uart parameter ram */ + uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u; + + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)eppc + Txbd); + rxbd = (struct cp_bufdesc *)((char *)eppc + Rxbd); + + /* + * Set up the PortB pins for UART operation. + * Set PAR and DIR to allow SMCTXD1 and SMRXD1 + * (Table 16-39) + */ + eppc->pip_pbpar |= 0xc0; + eppc->pip_pbdir &= ~0xc0; + +#ifdef __50MHZ + /* + * Configure BRG for 9600 baud @ 50MHZ sysclk + * (Section 16.13.2) + */ +#ifdef USE38400BAUD + eppc->brgc1 = 0x100a2; +#else + eppc->brgc1 = 0x10288; +#endif +#else + /* + * Configure BRG for 9600 baud @ 40MHz sysclk + * (Section 16.13.2) + */ +#ifdef USE38400BAUD + eppc->brgc1 = 0x10082; +#else + eppc->brgc1 = 0x10204; +#endif +#endif + + /* + * NMSI mode, BRG1 to SMC1 + * (Section 16.12.5.2) + */ + eppc->si_simode = 0; + + /* + * Set pointers to buffer descriptors. + * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) + */ + uart_pram->rbase = Rxbd; + uart_pram->tbase = Txbd; + + /* + * Init Rx & Tx params for SMC1 + */ + eppc->cp_cr = 0x91; + + /* + * SDMA & LCD bus request level 5 + * (Section 16.10.2.1) + */ + eppc->dma_sdcr = 1; + + /* + * Set Rx and Tx function code + * (Section 16.15.4.2) + */ + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + + /* max receive buffer length */ + uart_pram->mrblr = 1; + + /* disable max_idle feature */ + uart_pram->max_idl = 0; + + /* no last brk char received */ + uart_pram->brkln = 0; + + /* no break condition occurred */ + uart_pram->brkec = 0; + + /* 1 break char sent on top XMIT */ + uart_pram->brkcr = 1; + + /* setup RX buffer descriptor */ + rxbd->length = 0; + rxbd->buffer = Rxbuf; + rxbd->ctrl = 0xb000; + + /* setup TX buffer descriptor */ + txbd->length = 1; + txbd->buffer = Txbuf; + txbd->ctrl = 0x2000; + + /* + * Clear any previous events. Mask interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + eppc->smc_regs[0].smc_smce = 0xff; + eppc->smc_regs[0].smc_smcm = 5; + + /* + * Set 8,n,1 characters, then also enable rx and tx. + * (Section 16.15.7.11) + */ + eppc->smc_regs[0].smc_smcmr = 0x4820; + eppc->smc_regs[0].smc_smcmr = 0x4823; + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_CPM_SMC1 ); +#endif +} + + +//#define UART_BUFSIZE 32 + +//static bsp_queue_t uart_queue; +//static char uart_buffer[UART_BUFSIZE]; + +#define QUICC_BD_CTL_Busy 0x8000 // Descriptor/buffer busy +#define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in ring +#define QUICC_BD_CTL_Int 0x1000 // Interrupt enable +#define QUICC_BD_CTL_MASK 0xB000 // User settable bits +#define QUICC_SMCE_TX 0x02 // Tx interrupt +#define QUICC_SMCE_RX 0x01 // Rx interrupt +#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter +#define QUICC_SMCMR_REN (1<<0) // Enable receiver + +#ifdef CYGDBG_DIAG_BUF +extern int enable_diag_uart; +#endif // CYGDBG_DIAG_BUF + +void +cyg_quicc_smc1_uart_putchar(char ch) +{ + volatile struct cp_bufdesc *bd, *first; + EPPC *eppc = eppc_base(); + volatile struct smc_uart_pram *uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u; + int timeout; + + /* tx buffer descriptor */ + bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbptr); + + // Scan for a free buffer + first = bd; + while (bd->ctrl & QUICC_BD_CTL_Busy) { + if (bd->ctrl & QUICC_BD_CTL_Wrap) { + bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase); + } else { + bd++; + } + if (bd == first) break; + } + + while (bd->ctrl & QUICC_BD_CTL_Busy) ; // Wait for buffer free + if (bd->ctrl & QUICC_BD_CTL_Int) { + // This buffer has just completed interrupt output. Reset bits + bd->ctrl &= ~QUICC_BD_CTL_Int; + bd->length = 0; + } + + bd->buffer[bd->length++] = ch; + bd->ctrl |= QUICC_BD_CTL_Busy; + +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; +#endif // CYGDBG_DIAG_BUF + timeout = 0; + while (bd->ctrl & QUICC_BD_CTL_Busy) { +// Wait until buffer free + if (++timeout == 0x7FFFF) { + // A really long time! +#ifdef CYGDBG_DIAG_BUF + diag_printf("bd fail? bd: %x, ctrl: %x, tx state: %x\n", bd, bd->ctrl, uart_pram->tstate); +#endif // CYGDBG_DIAG_BUF + eppc->smc_regs[0].smc_smcmr &= ~QUICC_SMCMR_TEN; // Disable transmitter + bd->ctrl &= ~QUICC_BD_CTL_Busy; + eppc->smc_regs[0].smc_smcmr |= QUICC_SMCMR_TEN; // Enable transmitter + bd->ctrl |= QUICC_BD_CTL_Busy; + timeout = 0; +#ifdef CYGDBG_DIAG_BUF + diag_printf("bd retry? bd: %x, ctrl: %x, tx state: %x\n", bd, bd->ctrl, uart_pram->tstate); + first = (struct cp_bufdesc *)((char *)eppc + uart_pram->tbase); + while (true) { + diag_printf("bd: %x, ctrl: %x, length: %x\n", first, first->ctrl, first->length); + if (first->ctrl & QUICC_BD_CTL_Wrap) break; + first++; + } +#endif // CYGDBG_DIAG_BUF + } + } + while (bd->ctrl & QUICC_BD_CTL_Busy) ; // Wait until buffer free + bd->length = 0; +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF +} + + +int +cyg_quicc_smc1_uart_rcvchar(void) +{ + volatile struct cp_bufdesc *bd; + char ch; + EPPC *eppc = eppc_base(); + volatile struct smc_uart_pram *uart_pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u; + int cache_state; + + /* rx buffer descriptor */ + bd = (struct cp_bufdesc *)((char *)eppc + uart_pram->rbptr); + + while (bd->ctrl & QUICC_BD_CTL_Busy) ; + + ch = bd->buffer[0]; + + bd->length = 0; + bd->buffer[0] = '\0'; + bd->ctrl |= QUICC_BD_CTL_Busy; + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(bd->buffer, uart_pram->mrblr); // Make sure no stale data + } + + return ch; +} + +/* + * Early initialization of comm channels. Must not rely + * on interrupts, yet. Interrupt operation can be enabled + * in _bsp_board_init(). + */ +void +cyg_quicc_init_smc1(void) +{ + EPPC *eppc = eppc_base(); + int i; + + static int init = 0; // It's wrong to do this more than once + if (init) return; + init++; + + /* + * Reset communications processor + */ + eppc->cp_cr = 0x8001; + for (i = 0; i < 100000; i++); + + init_smc1_uart(); +} + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT +// This ISR is called from the interrupt handler. This should only +// happen when there is no real serial driver, so the code shouldn't +// mess anything up. +int cyg_hal_gdb_isr( target_register_t pc ) +{ + EPPC *eppc = eppc_base(); + struct cp_bufdesc *bd; + char ch; + + eppc->smc_regs[0].smc_smce = 0xff; + + /* rx buffer descriptors */ + bd = (struct cp_bufdesc *)((char *)eppc_base() + Rxbd); + + if ((bd->ctrl & 0x8000) == 0) { + // then there be a character waiting + ch = bd->buffer[0]; + bd->length = 1; + bd->ctrl = 0xb000; + + if ( 3 == ch ) { + // Ctrl-C: set a breakpoint at PC so GDB will display the + // correct program context when stopping rather than the + // interrupt handler. + cyg_hal_gdb_interrupt( pc ); + + // Interrupt handled. Don't call ISR proper. At return + // from the VSR, execution will stop at the breakpoint + // just set. + + eppc->cpmi_cisr = 0x10; + return 0; + } + } + eppc->cpmi_cisr = 0x10; // acknowledge the Rx event anyway + // in case it was left over from polled reception + // Not caused by GDB. Call ISR proper. + return 1; +} +#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + +#endif // CYG_HAL_POWERPC_MPC860 +// EOF quicc_smc1.c
--- a/packages/io/serial/current/ChangeLog +++ b/packages/io/serial/current/ChangeLog @@ -1,3 +1,20 @@ +1999-08-18 Jesper Skov <jskov@cygnus.co.uk> + + * tests/tty1.c: + * tests/tty2.c: + * tests/serial1.c: + * tests/serial2.c: + * tests/serial3.c: + * tests/serial4.c: + * tests/serial5.c: + * tests/PKGconf.mak: + Require kernel and kernel C API. + +1999-08-17 Nick Garnett <nickg@cygnus.co.uk> + + * src/mn10300/mn10300_serial.c: Added a simple implementation of a + receive FIFO to try and reduce the overhead of receiving bytes. + 1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> * src/PKGconf.mak: @@ -29,19 +46,69 @@ 1999-08-12 Nick Garnett <nickg@cygnus. Reparent CYGPKG_IO_SERIAL_MN10300 from under CYGPKG_HAL_MN10300 to CYGPKG_HAL_MN10300_AM32_STDEVAL1 since it's stdeval1 specific +1999-07-28 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Update descriptions to be more + generic (CL7x11 instead of CL7211). + +1999-07-28 Jonathan Larmour <jlarmour@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Correct typos in CDL description + for serial port 2 driver + 1999-07-08 Jesper Skov <jskov@cygnus.co.uk> * tests/ser_test_protocol.inl (change_config): Changed implementation. +1999-06-27 Gary Thomas <gthomas@cygnus.co.uk> + + * src/powerpc/quicc_smc_serial.c (quicc_smc_serial_init): More robust + initialization, with data cache disabled. This seems to fix the + random failures described below. + + * tests/ser_test_protocol.inl: Add configuration for QUICC/MBX860. + Added some delays in the configuration change code to make QUICC + happy [didn't help much although the manual says they are required]. + + * src/powerpc/quicc_smc_serial.h (UART_BITRATE): Rewrote macro to + match what the Linux driver uses - still doesn't work well, though. + + * src/powerpc/quicc_smc_serial.c: Lots of changes trying to get the + serial driver working and robust. At this point it works quite well, + using the default buffer sizes. Changing from the defaults seem to + easily break it though, certainly on input. Also, changing the baud + rate seems to not work reliably. + + * src/common/serial.c: Add some tracing/debug info to try and debug + problems with QUICC serial driver. These are hard disabled with + "XX_" prepended to "CYGDBG_DIAG_BUF". Enabling them gives information + about how/when data are delivered from the serial driver. + + * include/pkgconf/io_serial.h: Adjust limits and defaults on number and + size of buffers with values that seem to work. + +1999-06-21 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Fix CDL for number of buffers. + + * src/powerpc/quicc_smc_serial.c: Force number of buffers = 1. + 1999-06-20 Gary Thomas <gthomas@cygnus.co.uk> * include/pkgconf/io_serial.h: Some clean up (removed commented obsolete CDL parenting structure). + Add support for Motorola PowerPC QUICC/SMC. + * src/arm/cl7211_serial.c: * src/arm/aeb_serial.c: * src/arm/pid_serial_with_ints.c: Use #include to get 'diag_printf()' prototypes. +1999-06-17 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c (cl7211_serial_start_xmit): Fix race which + cause xmitter to get stuck. + 1999-05-27 Jesper Skov <jskov@cygnus.co.uk> * tests/ser_test_protocol.inl: Added ability to change options in @@ -56,6 +123,9 @@ 1999-05-27 Jonathan Larmour <jlarmour@ Fix for PR 20047 +1999-05-26 Gary Thomas <gthomas@cygnus.co.uk> + + * tests/ser_test_protocol.inl: Add Cirrus Logic CL7211 setup. 1999-05-25 Jonathan Larmour <jlarmour@cygnus.co.uk> * tests/ser_test_protocol.inl: @@ -71,6 +141,15 @@ 1999-05-18 Jesper Skov <jskov@cygnus.c * src/sparclite/sleb_sdtr.c (sleb_sdtr_rx_DSR): Only read chan if there is one. +1999-05-18 Jesper Skov <jskov@cygnus.co.uk> + PR 19926 + * src/arm/cl7211_serial.c (cl7211_serial_rx_DSR): Only read char + if there is one. + +1999-05-16 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Clean up, first working version. + 1999-05-14 Jesper Skov <jskov@cygnus.co.uk> * tests/ser_test_protocol.inl: Removed workaround for spurious @@ -94,6 +173,9 @@ 1999-05-13 Nick Garnett <nickg@cygnus. * include/pkgconf/io_serial.h: Fix CYGPKG_IO_SERIAL_TX39_JMR3904 parent attribute. +1999-05-11 Gary Thomas <gthomas@cygnus.co.uk> + + * src/arm/cl7211_serial.c: Fix compile problems from merged code. 1999-05-05 Jesper Skov <jskov@cygnus.co.uk> @@ -145,6 +227,10 @@ 1999-04-28 Bart Veer <bartv@cygnus.co. * src/PKGconf.mak (EXTRAS_COMPILE): Use the new rules for generating libextras.a +1999-04-26 Gary Thomas <gthomas@cygnus.co.uk> + + * include/pkgconf/io_serial.h: Add support for Cirrus Logic CL7211. + 1999-04-20 Gary Thomas <gthomas@cygnus.co.uk>
--- a/packages/io/serial/current/include/pkgconf/io_serial.h +++ b/packages/io/serial/current/include/pkgconf/io_serial.h @@ -382,6 +382,104 @@ #define CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BAUD 38400 #define CYGNUM_IO_SERIAL_ARM_AEB_SERIAL1_BUFSIZE 128 +/* ---------------------------------------------------------------------------- + {{CFG_DATA + cdl_component CYGPKG_IO_SERIAL_ARM_CL7211 { + display "ARM CL7x11 (CL7111/CL7211) serial device drivers" + type bool + requires CYGPKG_IO_SERIAL + parent CYGPKG_HAL_ARM_CL7211 + description " + This option enables the serial device drivers for the ARM CL7x11." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_component CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 { + display "ARM CL7x11 serial port 1 driver" + type bool + parent CYGPKG_IO_SERIAL_ARM_CL7211 + description " + This option includes the serial device driver for the ARM CL7x11 port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL1_NAME { + display "Device name for the ARM CL7x11 serial port 1 driver" + type string + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 + description " + This option specifies the name of serial device for the ARM CL7x11 port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BAUD { + display "Baud rate for the ARM CL7x11 serial port 1 driver" + type enum + legal_values 50 75 110 134_5 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 234000 + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 + description " + This option specifies the default baud rate (speed) for the ARM CL7x11 port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BUFSIZE { + display "Buffer size for the ARM CL7x11 serial port 1 driver" + type count + legal_values 0 to 8192 + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 + description " + This option specifies the size of the internal buffers used for the ARM CL7x11 port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_component CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 { + display "ARM CL7x11 serial port 2 driver" + type bool + parent CYGPKG_IO_SERIAL_ARM_CL7211 + description " + This option includes the serial device driver for the ARM CL7x11 port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL2_NAME { + display "Device name for the ARM CL7x11 serial port 2 driver" + type string + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 + description " + This option specifies the name of serial device for the ARM CL7x11 port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BAUD { + display "Baud rate for the ARM CL7x11 serial port 2 driver" + type enum + legal_values 50 75 110 134_5 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 234000 + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 + description " + This option specifies the default baud rate (speed) for the ARM CL7x11 port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BUFSIZE { + display "Buffer size for the ARM CL7x11 serial port 2 driver" + type count + legal_values 0 to 8192 + parent CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 + description " + This option specifies the size of the internal buffers used for the ARM CL7x11 port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + }}CFG_DATA */ +#undef CYGPKG_IO_SERIAL_ARM_CL7211 +#undef CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 +#define CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL1_NAME "/dev/ser1" +#define CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BAUD 38400 +#define CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BUFSIZE 128 +#undef CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 +#define CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL2_NAME "/dev/ser2" +#define CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BAUD 38400 +#define CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BUFSIZE 128 @@ -489,6 +587,228 @@ #define CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BAUD 38400 #define CYGNUM_IO_SERIAL_POWERPC_COGENT_SERIAL_B_BUFSIZE 128 +/* ---------------------------------------------------------------------------- + {{CFG_DATA + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC { + display "PowerPC QUICC/SMC serial device drivers" + type bool + requires CYGPKG_IO_SERIAL + parent CYGPKG_HAL_QUICC + description " + This option enables the serial device drivers for the PowerPC QUICC/SMC." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 { + display "PowerPC QUICC/SMC serial port 1 driver" + type bool + requires CYGPKG_IO_SERIAL + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC + description " + This option includes the serial device driver for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME { + display "Device name for PowerPC QUICC/SMC serial port 1" + type string + requires CYGPKG_IO_SERIAL + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the device name for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD { + display "Baud rate for the PowerPC QUICC/SMC serial port 1" + type enum + legal_values 50 75 110 134_5 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 234000 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the default baud rate (speed) for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 0 to 8192 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the size of the internal buffers used for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG { + display "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 1 to 4 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 16 to 128 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the maximum number of characters per transmit + request to be used for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 2 to 16 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 16 to 128 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM { + display "Number of input buffers for the PowerPC QUICC/SMC serial port 1" + type count + legal_values 2 to 16 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SMC port 1." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_component CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 { + display "PowerPC QUICC/SMC serial port 2 driver" + type bool + requires CYGPKG_IO_SERIAL + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC + description " + This option includes the serial device driver for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME { + display "Device name for PowerPC QUICC/SMC serial port 2" + type string + requires CYGPKG_IO_SERIAL + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the device name for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD { + display "Baud rate for the PowerPC QUICC/SMC serial port 2" + type enum + legal_values 50 75 110 134_5 150 200 300 600 1200 1800 2400 3600 4800 7200 9600 14400 19200 38400 57600 115200 234000 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the default baud rate (speed) for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE { + display "Buffer size for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 0 to 8192 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the size of the internal buffers used for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG { + display "Which baud rate generator to use for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 1 to 4 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies which of the four baud rate generators + to use for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE { + display "Output buffer size for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 16 to 128 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the maximum number of characters per transmit + request to be used for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 2 to 16 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the number of output buffer packets + to be used for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE { + display "Input buffer size for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 16 to 128 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the maximum number of characters per receive + request to be used for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + cdl_option CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM { + display "Number of output buffers for the PowerPC QUICC/SMC serial port 2" + type count + legal_values 2 to 16 + parent CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + description " + This option specifies the number of input buffer packets + to be used for the PowerPC QUICC/SMC port 2." + doc ref/ecos-ref/ecos-device-drivers.html + } + + }}CFG_DATA */ +#undef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC +#undef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 +#define CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME "/dev/ser1" +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD 38400 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE 256 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG 1 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE 16 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM 4 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE 16 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM 4 +#undef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 +#define CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME "/dev/ser2" +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD 38400 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE 256 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG 2 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE 16 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM 4 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE 16 +#define CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM 4 /* ---------------------------------------------------------------------------- {{CFG_DATA
--- a/packages/io/serial/current/src/PKGconf.mak +++ b/packages/io/serial/current/src/PKGconf.mak @@ -40,6 +40,9 @@ endif ifdef CYG_HAL_ARM_AEB EXTRAS_COMPILE += arm/aeb_serial.c endif +ifdef CYG_HAL_ARM_CL7211 +EXTRAS_COMPILE += arm/cl7211_serial.c +endif ifdef CYG_HAL_MN10300_AM31 EXTRAS_COMPILE += mn10300/mn10300_serial.c endif @@ -49,6 +52,9 @@ endif ifdef CYG_HAL_POWERPC_COGENT EXTRAS_COMPILE += powerpc/cogent_serial_with_ints.c endif +ifdef CYGPKG_HAL_QUICC +EXTRAS_COMPILE += powerpc/quicc_smc_serial.c +endif ifdef CYG_HAL_SPARCLITE_SLEB EXTRAS_COMPILE += sparclite/sleb_sdtr.c endif
new file mode 100644 --- /dev/null +++ b/packages/io/serial/current/src/arm/cl7211_serial.c @@ -0,0 +1,381 @@ +//========================================================================== +// +// io/serial/arm/cl7211_serial.c +// +// Cirrus Logic CL7211 Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: CL7211 Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> + +#ifdef CYGPKG_IO_SERIAL_ARM_CL7211 + +#include "cl7211_serial.h" + +typedef struct cl7211_serial_info { + CYG_ADDRWORD data, // Pointer to data register + control, // Pointer to baud rate/line control register + stat, // Pointer to system flags for this port + syscon; // Pointer to system control for this port + CYG_WORD tx_int_num, // Transmit interrupt number + rx_int_num, // Receive interrupt number + ms_int_num; // Modem Status Change interrupt number + cyg_interrupt serial_tx_interrupt, + serial_rx_interrupt, + serial_ms_interrupt; + cyg_handle_t serial_tx_interrupt_handle, + serial_rx_interrupt_handle, + serial_ms_interrupt_handle; + bool tx_enabled; +} cl7211_serial_info; + +static bool cl7211_serial_init(struct cyg_devtab_entry *tab); +static bool cl7211_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo cl7211_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char cl7211_serial_getc(serial_channel *chan); +static bool cl7211_serial_set_config(serial_channel *chan, cyg_serial_info_t *config); +static void cl7211_serial_start_xmit(serial_channel *chan); +static void cl7211_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 cl7211_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void cl7211_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 cl7211_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void cl7211_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); +static cyg_uint32 cl7211_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void cl7211_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(cl7211_serial_funs, + cl7211_serial_putc, + cl7211_serial_getc, + cl7211_serial_set_config, + cl7211_serial_start_xmit, + cl7211_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1 +static cl7211_serial_info cl7211_serial_info1 = {UARTDR1, // Data register + UBLCR1, // Port control + SYSFLG1, // Status + SYSCON1, // System config + CYGNUM_HAL_INTERRUPT_UTXINT1, // Tx interrupt + CYGNUM_HAL_INTERRUPT_URXINT1, // Rx interrupt + 0 /*CYGNUM_HAL_INTERRUPT_UMSINT*/}; // Modem control +#if CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BUFSIZE > 0 +static unsigned char cl7211_serial_out_buf1[CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BUFSIZE]; +static unsigned char cl7211_serial_in_buf1[CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cl7211_serial_channel1, + cl7211_serial_funs, + cl7211_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cl7211_serial_out_buf1[0], sizeof(cl7211_serial_out_buf1), + &cl7211_serial_in_buf1[0], sizeof(cl7211_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(cl7211_serial_channel1, + cl7211_serial_funs, + cl7211_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cl7211_serial_io1, + CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL1_NAME, + 0, // Does not depend on a lower level interface + &serial_devio, + cl7211_serial_init, + cl7211_serial_lookup, // Serial driver may need initializing + &cl7211_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_ARM_CL7212_SERIAL2 + +#ifdef CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL2 +static cl7211_serial_info cl7211_serial_info2 = {UARTDR2, // Data register + UBLCR2, // Port control + SYSFLG2, // Status + SYSCON2, // System config + CYGNUM_HAL_INTERRUPT_UTXINT2, // Tx interrupt + CYGNUM_HAL_INTERRUPT_URXINT2, // Rx interrupt + 0}; // No modem control +#if CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BUFSIZE > 0 +static unsigned char cl7211_serial_out_buf2[CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BUFSIZE]; +static unsigned char cl7211_serial_in_buf2[CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(cl7211_serial_channel2, + cl7211_serial_funs, + cl7211_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &cl7211_serial_out_buf2[0], sizeof(cl7211_serial_out_buf2), + &cl7211_serial_in_buf2[0], sizeof(cl7211_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(cl7211_serial_channel2, + cl7211_serial_funs, + cl7211_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_ARM_CL7211_SERIAL2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +DEVTAB_ENTRY(cl7211_serial_io2, + CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL2_NAME, + 0, // Does not depend on a lower level interface + &serial_devio, + cl7211_serial_init, + cl7211_serial_lookup, // Serial driver may need initializing + &cl7211_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_ARM_CL7212_SERIAL2 + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +cl7211_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + volatile cyg_uint32 *syscon = (volatile cyg_uint32 *)cl7211_chan->syscon; + volatile cyg_uint32 *blcfg = (volatile cyg_uint32 *)cl7211_chan->control; + unsigned int baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + if (baud_divisor == 0) return false; + // Disable port interrupts while changing hardware + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity] | + UBLCR_FIFOEN | UART_BITRATE(baud_divisor); +#ifdef CYGDBG_IO_INIT + diag_printf("Set CTL: %x = %x\n", blcfg, _lcr); +#endif + *blcfg = _lcr; + *syscon |= SYSCON1_UART1EN; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +cl7211_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; +#ifdef CYGDBG_IO_INIT + diag_printf("CL7211 SERIAL init - dev: %x.%d\n", cl7211_chan->control, cl7211_chan->tx_int_num); +#endif + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(cl7211_chan->tx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + cl7211_serial_tx_ISR, + cl7211_serial_tx_DSR, + &cl7211_chan->serial_tx_interrupt_handle, + &cl7211_chan->serial_tx_interrupt); + cyg_drv_interrupt_attach(cl7211_chan->serial_tx_interrupt_handle); + cyg_drv_interrupt_mask(cl7211_chan->tx_int_num); + cl7211_chan->tx_enabled = false; + } + if (chan->in_cbuf.len != 0) { + cyg_drv_interrupt_create(cl7211_chan->rx_int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + cl7211_serial_rx_ISR, + cl7211_serial_rx_DSR, + &cl7211_chan->serial_rx_interrupt_handle, + &cl7211_chan->serial_rx_interrupt); + cyg_drv_interrupt_attach(cl7211_chan->serial_rx_interrupt_handle); + cyg_drv_interrupt_unmask(cl7211_chan->rx_int_num); + } + cl7211_serial_config_port(chan, &chan->config, true); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +cl7211_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +cl7211_serial_putc(serial_channel *chan, unsigned char c) +{ + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + volatile cyg_uint8 *data = (volatile cyg_uint8 *)cl7211_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)cl7211_chan->stat; + if ((*stat & SYSFLG1_UTXFF1) == 0) { +// Transmit buffer/FIFO is not full + *data = c; + return true; + } else { +// No space + return false; + } +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +cl7211_serial_getc(serial_channel *chan) +{ + unsigned char c; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + volatile cyg_uint32 *data = (volatile cyg_uint32 *)cl7211_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)cl7211_chan->stat; + while (*stat & SYSFLG1_URXFE1) ; // Wait for char + c = *data; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static bool +cl7211_serial_set_config(serial_channel *chan, cyg_serial_info_t *config) +{ + return cl7211_serial_config_port(chan, config, false); +} + +// Enable the transmitter (interrupt) on the device +static void +cl7211_serial_start_xmit(serial_channel *chan) +{ + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + cl7211_chan->tx_enabled = true; + cyg_drv_interrupt_unmask(cl7211_chan->tx_int_num); +} + +// Disable the transmitter on the device +static void +cl7211_serial_stop_xmit(serial_channel *chan) +{ + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cl7211_chan->tx_int_num); + cl7211_chan->tx_enabled = false; +} + +// Serial I/O - low level Tx interrupt handler (ISR) +static cyg_uint32 +cl7211_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cl7211_chan->tx_int_num); + cyg_drv_interrupt_acknowledge(cl7211_chan->tx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Tx interrupt handler (DSR) +static void +cl7211_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + (chan->callbacks->xmt_char)(chan); + if (cl7211_chan->tx_enabled) { + cyg_drv_interrupt_unmask(cl7211_chan->tx_int_num); + } +} + +// Serial I/O - low level Rx interrupt handler (ISR) +static cyg_uint32 +cl7211_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cl7211_chan->rx_int_num); + cyg_drv_interrupt_acknowledge(cl7211_chan->rx_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Rx interrupt handler (DSR) +static void +cl7211_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + volatile cyg_uint32 *datreg = (volatile cyg_uint32 *)cl7211_chan->data; + volatile cyg_uint32 *stat = (volatile cyg_uint32 *)cl7211_chan->stat; + if (!(*stat & SYSFLG1_URXFE1)) + (chan->callbacks->rcv_char)(chan, *datreg); + cyg_drv_interrupt_unmask(cl7211_chan->rx_int_num); +} + +// Serial I/O - low level Ms interrupt handler (ISR) +static cyg_uint32 +cl7211_serial_ms_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + cl7211_serial_info *cl7211_chan = (cl7211_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(cl7211_chan->ms_int_num); + cyg_drv_interrupt_acknowledge(cl7211_chan->ms_int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level Ms interrupt handler (DSR) +static void +cl7211_serial_ms_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ +} +#endif // CYGPKG_IO_SERIAL_ARM_CL7211 +
new file mode 100644 --- /dev/null +++ b/packages/io/serial/current/src/arm/cl7211_serial.h @@ -0,0 +1,98 @@ +#ifndef CYGONCE_ARM_CL7211_SERIAL_H +#define CYGONCE_ARM_CL7211_SERIAL_H + +// ==================================================================== +// +// cl7211_serial.h +// +// Device I/O - Description of Cirrus Logic CL7211 serial hardware +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-02-04 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports on Cirrus Logic CL7211 + +#include <cyg/hal/hal_cl7211.h> // Hardware definitions + +static unsigned int select_word_length[] = { + UBLCR_WRDLEN5, // 5 bits / word (char) + UBLCR_WRDLEN6, + UBLCR_WRDLEN7, + UBLCR_WRDLEN8 +}; + +static unsigned int select_stop_bits[] = { + 0, + 0, // 1 stop bit + 0, // 1.5 stop bit + UBLCR_XSTOP // 2 stop bits +}; + +static unsigned int select_parity[] = { + 0, // No parity + UBLCR_PRTEN|UBLCR_EVENPRT, // Even parity + UBLCR_PRTEN, // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +// Baud rate values, based on PLL clock + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 0, // 230400 +}; + +#endif // CYGONCE_ARM_CL7211_SERIAL_H
--- a/packages/io/serial/current/src/mn10300/mn10300_serial.c +++ b/packages/io/serial/current/src/mn10300/mn10300_serial.c @@ -50,6 +50,8 @@ #ifdef CYGPKG_IO_SERIAL_MN10300 +#define CYG_HAL_MN10300_SERIAL_RX_FIFO + //------------------------------------------------------------------------- extern void diag_printf(const char *fmt, ...); @@ -265,16 +267,21 @@ static struct // Info for each serial device controlled typedef struct mn10300_serial_info { - CYG_ADDRWORD base; - CYG_ADDRWORD timer_base; - CYG_WORD timer_select; - CYG_WORD rx_int; - CYG_WORD tx_int; - cyg_bool is_serial2; - cyg_interrupt rx_interrupt; - cyg_interrupt tx_interrupt; - cyg_handle_t rx_interrupt_handle; - cyg_handle_t tx_interrupt_handle; + CYG_ADDRWORD base; + CYG_ADDRWORD timer_base; + CYG_WORD timer_select; + CYG_WORD rx_int; + CYG_WORD tx_int; + cyg_bool is_serial2; + cyg_interrupt rx_interrupt; + cyg_interrupt tx_interrupt; + cyg_handle_t rx_interrupt_handle; + cyg_handle_t tx_interrupt_handle; +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + volatile cyg_int32 fifo_head; + volatile cyg_int32 fifo_tail; + volatile cyg_uint8 fifo[16]; +#endif } mn10300_serial_info; //------------------------------------------------------------------------- @@ -747,6 +754,51 @@ mn10300_serial_stop_xmit(serial_channel #ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + +// This version of the RX ISR implements a simple receive FIFO. The +// MN10300 serial devices do not have hardware FIFOs (as found in +// 16550s for example), and it can be difficult at times to keep up +// with higher baud rates without overrunning. This ISR implements a +// software equivalent of the hardware FIFO, placing recieved +// characters into the FIFO as soon as they arrive. Whenever the DSR +// is run, it collects all the pending characters from the FIFO for +// delivery to the application. Neither the ISR or DSR disable +// interrupts, instead we rely on being able to write the head and +// tail pointers atomically, to implement lock-free synchronization. + +static cyg_uint32 +mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + cyg_uint8 sr = mn10300_read_sr( mn10300_chan); + + while( (sr & SR_RBF) != 0 ) + { + register cyg_int32 head = mn10300_chan->fifo_head; + cyg_uint8 c; + int i; + HAL_READ_UINT8( mn10300_chan->base+SERIAL_RXB, c ); + + mn10300_chan->fifo[head++] = c; + + if( head >= sizeof(mn10300_chan->fifo) ) + head = 0; + + mn10300_chan->fifo_head = head; + + sr = mn10300_read_sr( mn10300_chan); + + } + + cyg_drv_interrupt_acknowledge(mn10300_chan->rx_int); + + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +#else + static cyg_uint32 mn10300_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data) { @@ -759,6 +811,7 @@ mn10300_serial_rx_ISR(cyg_vector_t vecto return CYG_ISR_CALL_DSR; // Cause DSR to be run } +#endif static cyg_uint32 mn10300_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data) @@ -779,6 +832,30 @@ mn10300_serial_tx_ISR(cyg_vector_t vecto #ifndef CYGPKG_IO_SERIAL_MN10300_POLLED_MODE +#ifdef CYG_HAL_MN10300_SERIAL_RX_FIFO + +static void +mn10300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + mn10300_serial_info *mn10300_chan = (mn10300_serial_info *)chan->dev_priv; + register cyg_int32 head = mn10300_chan->fifo_head; + register cyg_int32 tail = mn10300_chan->fifo_tail; + + while( head != tail ) + { + cyg_uint8 c = mn10300_chan->fifo[tail++]; + + if( tail >= sizeof(mn10300_chan->fifo) ) tail = 0; + + (chan->callbacks->rcv_char)(chan, c); + } + + mn10300_chan->fifo_tail = tail; +} + +#else + static void mn10300_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) { @@ -797,6 +874,8 @@ mn10300_serial_rx_DSR(cyg_vector_t vecto cyg_drv_interrupt_unmask(mn10300_chan->rx_int); } +#endif + static void mn10300_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
new file mode 100644 --- /dev/null +++ b/packages/io/serial/current/src/powerpc/quicc_smc_serial.c @@ -0,0 +1,772 @@ +//========================================================================== +// +// io/serial/powerpc/quicc_smc_serial.c +// +// PowerPC QUICC (SMC) Serial I/O Interface Module (interrupt driven) +// +//========================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-20 +// Purpose: QUICC SMC Serial I/O module (interrupt driven version) +// Description: +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include <pkgconf/system.h> +#include <pkgconf/io_serial.h> +#include <pkgconf/io.h> +#include <cyg/io/io.h> +#include <cyg/hal/hal_intr.h> +#include <cyg/io/devtab.h> +#include <cyg/io/serial.h> +#include <cyg/infra/diag.h> +#include <cyg/hal/hal_cache.h> +#include CYGBLD_HAL_PLATFORM_H + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC + +// Buffer descriptor control bits +#define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx) +#define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list +#define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx) +#define QUICC_BD_CTL_MASK 0xB000 // User settable bits + +// SMC Mode Register +#define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length +#define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2) +#define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable) +#define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even) +#define QUICC_SMCMR_UART (2<<4) // UART mode +#define QUICC_SMCMR_TEN (1<<1) // Enable transmitter +#define QUICC_SMCMR_REN (1<<0) // Enable receiver + +// SMC Events (interrupts) +#define QUICC_SMCE_BRK 0x10 // Break received +#define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun +#define QUICC_SMCE_TX 0x02 // Tx interrupt +#define QUICC_SMCE_RX 0x01 // Rx interrupt + +// SMC Commands +#define QUICC_SMC_CMD_InitTxRx (0<<8) +#define QUICC_SMC_CMD_InitTx (1<<8) +#define QUICC_SMC_CMD_InitRx (2<<8) +#define QUICC_SMC_CMD_StopTx (4<<8) +#define QUICC_SMC_CMD_RestartTx (6<<8) +#define QUICC_SMC_CMD_Reset 0x8000 +#define QUICC_SMC_CMD_Go 0x0001 + +#include "quicc_smc_serial.h" + +typedef struct quicc_smc_serial_info { + CYG_ADDRWORD channel; // Which channel SMC1/SMC2 + CYG_WORD int_num; // Interrupt number + cyg_uint32 *brg; // Which baud rate generator + struct smc_uart_pram *pram; // Parameter RAM pointer + struct smc_regs *ctl; // SMC control registers + struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use + struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor + int txsize, rxsize; // Length of individual buffers + cyg_interrupt serial_interrupt; + cyg_handle_t serial_interrupt_handle; + bool tx_enabled; +} quicc_smc_serial_info; + +static bool quicc_smc_serial_init(struct cyg_devtab_entry *tab); +static bool quicc_smc_serial_putc(serial_channel *chan, unsigned char c); +static Cyg_ErrNo quicc_smc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name); +static unsigned char quicc_smc_serial_getc(serial_channel *chan); +static bool quicc_smc_serial_set_config(serial_channel *chan, cyg_serial_info_t *config); +static void quicc_smc_serial_start_xmit(serial_channel *chan); +static void quicc_smc_serial_stop_xmit(serial_channel *chan); + +static cyg_uint32 quicc_smc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data); +static void quicc_smc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data); + +static SERIAL_FUNS(quicc_smc_serial_funs, + quicc_smc_serial_putc, + quicc_smc_serial_getc, + quicc_smc_serial_set_config, + quicc_smc_serial_start_xmit, + quicc_smc_serial_stop_xmit + ); + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 +static quicc_smc_serial_info quicc_smc_serial_info1 = { + 0x90, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SMC1 // interrupt +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_smc_serial_channel1, + quicc_smc_serial_funs, + quicc_smc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf1[0], sizeof(quicc_smc_serial_out_buf1), + &quicc_smc_serial_in_buf1[0], sizeof(quicc_smc_serial_in_buf1) + ); +#else +static SERIAL_CHANNEL(quicc_smc_serial_channel1, + quicc_smc_serial_funs, + quicc_smc_serial_info1, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif + +static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE]; +static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE]; + +DEVTAB_ENTRY(quicc_smc_serial_io1, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME, + 0, // Does not depend on a lower level interface + &serial_devio, + quicc_smc_serial_init, + quicc_smc_serial_lookup, // Serial driver may need initializing + &quicc_smc_serial_channel1 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 +static quicc_smc_serial_info quicc_smc_serial_info2 = { + 0xB0, // Channel indicator + CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP // interrupt +}; +#if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE > 0 +static unsigned char quicc_smc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE]; +static unsigned char quicc_smc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE]; + +static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_smc_serial_channel2, + quicc_smc_serial_funs, + quicc_smc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT, + &quicc_smc_serial_out_buf2[0], sizeof(quicc_smc_serial_out_buf2), + &quicc_smc_serial_in_buf2[0], sizeof(quicc_smc_serial_in_buf2) + ); +#else +static SERIAL_CHANNEL(quicc_smc_serial_channel2, + quicc_smc_serial_funs, + quicc_smc_serial_info2, + CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD), + CYG_SERIAL_STOP_DEFAULT, + CYG_SERIAL_PARITY_DEFAULT, + CYG_SERIAL_WORD_LENGTH_DEFAULT, + CYG_SERIAL_FLAGS_DEFAULT + ); +#endif +static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE]; +static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE]; + +DEVTAB_ENTRY(quicc_smc_serial_io2, + CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME, + 0, // Does not depend on a lower level interface + &serial_devio, + quicc_smc_serial_init, + quicc_smc_serial_lookup, // Serial driver may need initializing + &quicc_smc_serial_channel2 + ); +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + +#ifdef CYGDBG_DIAG_BUF +extern int enable_diag_uart; +#endif // CYGDBG_DIAG_BUF + +// Internal function to actually configure the hardware to desired baud rate, etc. +static bool +quicc_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init) +{ + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + unsigned int baud_divisor = select_baud[new_config->baud]; + cyg_uint32 _lcr; + EPPC *eppc = eppc_base(); + if (baud_divisor == 0) return false; + // Disable channel during setup + smc_chan->ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode + // Disable port interrupts while changing hardware + _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] | + select_stop_bits[new_config->stop] | + select_parity[new_config->parity]; + // Stop transmitter while changing baud rate + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx; + // Set baud rate generator + *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1); +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + diag_printf("Set BAUD RATE[%x], %d = %x, tstate = %x\n", smc_chan->brg, baud_divisor, *smc_chan->brg, smc_chan->pram->tstate); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + + // Enable channel with new configuration + smc_chan->ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr; + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx; + if (new_config != &chan->config) { + chan->config = *new_config; + } + return true; +} + +// Function to set up internal tables for device. +static void +quicc_smc_serial_init_info(quicc_smc_serial_info *smc_chan, + struct smc_uart_pram *uart_pram, + struct smc_regs *ctl, + int TxBD, int TxNUM, int TxSIZE, + cyg_uint8 *TxBUF, + int RxBD, int RxNUM, int RxSIZE, + cyg_uint8 *RxBUF, + int portBmask, + int BRG, int SIpos) +{ + EPPC *eppc = eppc_base(); + struct cp_bufdesc *txbd, *rxbd; + cyg_uint32 simode = 0; + int i; + + // Disable channel during setup + ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode + smc_chan->pram = uart_pram; + smc_chan->ctl = ctl; + /* + * SDMA & LCD bus request level 5 + * (Section 16.10.2.1) + */ + eppc->dma_sdcr = 1; + switch (BRG) { + case 1: + smc_chan->brg = (cyg_uint32 *)&eppc->brgc1; + simode = 0; + break; + case 2: + smc_chan->brg = (cyg_uint32 *)&eppc->brgc2; + simode = 1; + break; + case 3: + smc_chan->brg = (cyg_uint32 *)&eppc->brgc3; + simode = 2; + break; + case 4: + smc_chan->brg = (cyg_uint32 *)&eppc->brgc4; + simode = 3; + break; + } + // NMSI mode, BRGn to SMCm (Section 16.12.5.2) + eppc->si_simode = (eppc->si_simode & ~(0xF<<SIpos)) | (simode<<SIpos); + /* + * Set up the PortB pins for UART operation. + * Set PAR and DIR to allow SMCTXDx and SMRXDx + * (Table 16-39) + */ + eppc->pip_pbpar |= portBmask; + eppc->pip_pbdir &= ~portBmask; + /* + * Reset Rx & Tx params + */ + eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx; + /* + * SDMA & LCD bus request level 5 + * (Section 16.10.2.1) + */ + eppc->dma_sdcr = 1; + /* + * Set Rx and Tx function code + * (Section 16.15.4.2) + */ + uart_pram->rfcr = 0x18; + uart_pram->tfcr = 0x18; + /* + * Set pointers to buffer descriptors. + * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13) + */ + uart_pram->rbase = RxBD; + uart_pram->tbase = TxBD; + /* tx and rx buffer descriptors */ + txbd = (struct cp_bufdesc *)((char *)eppc + TxBD); + rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD); + smc_chan->txbd = txbd; + smc_chan->tbase = txbd; + smc_chan->txsize = TxSIZE; + smc_chan->rxbd = rxbd; + smc_chan->rbase = rxbd; + smc_chan->rxsize = RxSIZE; + /* max receive buffer length */ + uart_pram->mrblr = RxSIZE; + /* set max_idle feature - generate interrupt after 4 chars idle period */ + uart_pram->max_idl = 4; + /* no last brk char received */ + uart_pram->brkln = 0; + /* no break condition occurred */ + uart_pram->brkec = 0; + /* 1 break char sent on top XMIT */ + uart_pram->brkcr = 1; + /* setup RX buffer descriptors */ + for (i = 0; i < RxNUM; i++) { + rxbd->length = 0; + rxbd->buffer = RxBUF; + rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int; + if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + RxBUF += RxSIZE; + rxbd++; + } + /* setup TX buffer descriptors */ + for (i = 0; i < TxNUM; i++) { + txbd->length = 0; + txbd->buffer = TxBUF; + txbd->ctrl = 0; + if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer + TxBUF += TxSIZE; + txbd++; + } + /* + * Clear any previous events. Enable interrupts. + * (Section 16.15.7.14 and 16.15.7.15) + */ + ctl->smc_smce = 0xFF; + ctl->smc_smcm = QUICC_SMCE_BSY|QUICC_SMCE_TX|QUICC_SMCE_RX; +} + +// Function to initialize the device. Called at bootstrap time. +static bool +quicc_smc_serial_init(struct cyg_devtab_entry *tab) +{ + serial_channel *chan = (serial_channel *)tab->priv; + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + volatile EPPC *eppc = (volatile EPPC *)eppc_base(); + int TxBD, RxBD; + static int first_init = 1; + int cache_state; + HAL_DCACHE_IS_ENABLED(cache_state); + HAL_DCACHE_SYNC(); + HAL_DCACHE_DISABLE(); +#ifdef CYGDBG_IO_INIT + diag_printf("QUICC_SMC SERIAL init - dev: %x.%d\n", smc_chan->channel, smc_chan->int_num); +#endif + if (first_init) { + // Set up tables since many fields are dynamic [computed at runtime] + first_init = 0; + eppc->cp_cr = QUICC_SMC_CMD_Reset | QUICC_SMC_CMD_Go; // Totally reset CP + while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ; + TxBD = 0x2800; // Note: this should be configurable +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1 + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*8; + quicc_smc_serial_init_info(&quicc_smc_serial_info1, + &eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM + &eppc->smc_regs[0], // Control registers + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE, + &quicc_smc1_txbuf[0][0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE, + &quicc_smc1_rxbuf[0][0], + 0xC0, // PortB mask + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG, + 12 // SI mask position + ); + TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8; +#endif +#ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2 + RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*8; + quicc_smc_serial_init_info(&quicc_smc_serial_info2, + &eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM + &eppc->smc_regs[1], // Control registers + TxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE, + &quicc_smc2_txbuf[0][0], + RxBD, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM, + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE, + &quicc_smc2_rxbuf[0][0], + 0xC00, // PortB mask + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG, + 28 // SI mask position + ); +#endif + } + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + if (chan->out_cbuf.len != 0) { + cyg_drv_interrupt_create(smc_chan->int_num, + 99, // Priority - unused + (cyg_addrword_t)chan, // Data item passed to interrupt handler + quicc_smc_serial_ISR, + quicc_smc_serial_DSR, + &smc_chan->serial_interrupt_handle, + &smc_chan->serial_interrupt); + cyg_drv_interrupt_attach(smc_chan->serial_interrupt_handle); + cyg_drv_interrupt_mask(smc_chan->int_num); + smc_chan->tx_enabled = false; + } + quicc_smc_serial_config_port(chan, &chan->config, true); + if (cache_state) + HAL_DCACHE_ENABLE(); + return true; +} + +// This routine is called when the device is "looked" up (i.e. attached) +static Cyg_ErrNo +quicc_smc_serial_lookup(struct cyg_devtab_entry **tab, + struct cyg_devtab_entry *sub_tab, + const char *name) +{ + serial_channel *chan = (serial_channel *)(*tab)->priv; + (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices + return ENOERR; +} + +// Force the current transmit buffer to be sent +static void +quicc_smc_serial_flush(quicc_smc_serial_info *smc_chan) +{ + struct cp_bufdesc *txbd = smc_chan->txbd; + if ((txbd->length > 0) && ((txbd->ctrl & QUICC_BD_CTL_Ready) == 0)) { + txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int; // Signal buffer ready + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + smc_chan->txbd = txbd; + } +} + +// Send a character to the device output buffer. +// Return 'true' if character is sent to device +static bool +quicc_smc_serial_putc(serial_channel *chan, unsigned char c) +{ + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *txbd, *txfirst; + EPPC *eppc = eppc_base(); + bool res; + cyg_drv_dsr_lock(); // Avoid race condition testing pointers + txbd = (struct cp_bufdesc *)((char *)eppc + smc_chan->pram->tbptr); + txfirst = txbd; + // Scan for a non-busy buffer + while (txbd->ctrl & QUICC_BD_CTL_Ready) { + // This buffer is busy, move to next one + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + } else { + txbd++; + } + if (txbd == txfirst) break; // Went all the way around + } + smc_chan->txbd = txbd; + if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0) { + // Transmit buffer is not full/busy + txbd->buffer[txbd->length++] = c; + if (txbd->length == smc_chan->txsize) { + // This buffer is now full, tell SMC to start processing it + quicc_smc_serial_flush(smc_chan); + } + res = true; + } else { + // No space + res = false; + } + cyg_drv_dsr_unlock(); + return res; +} + +// Fetch a character from the device input buffer, waiting if necessary +static unsigned char +quicc_smc_serial_getc(serial_channel *chan) +{ + unsigned char c; + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + while ((rxbd->ctrl & QUICC_BD_CTL_Ready) != 0) ; + c = rxbd->buffer[0]; + rxbd->length = smc_chan->rxsize; + rxbd->ctrl |= QUICC_BD_CTL_Ready; + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + return c; +} + +// Set up the device characteristics; baud rate, etc. +static bool +quicc_smc_serial_set_config(serial_channel *chan, cyg_serial_info_t *config) +{ + bool res = quicc_smc_serial_config_port(chan, config, false); + // FIXME - The documentation says that you can't change the baud rate + // again until at least two BRG input clocks have occurred. + return res; +} + +// Enable the transmitter (interrupt) on the device +static void +quicc_smc_serial_start_xmit(serial_channel *chan) +{ + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + struct cp_bufdesc *txbd = smc_chan->txbd; + if (smc_chan->txbd->length == 0) { + // See if there is anything to put in this buffer, just to get it going + cyg_drv_dsr_lock(); + (chan->callbacks->xmt_char)(chan); + cyg_drv_dsr_unlock(); + } + if (smc_chan->txbd->length != 0) { + // Make sure it gets started + quicc_smc_serial_flush(smc_chan); + } + smc_chan->tx_enabled = true; + cyg_drv_interrupt_unmask(smc_chan->int_num); +} + +// Disable the transmitter on the device +static void +quicc_smc_serial_stop_xmit(serial_channel *chan) +{ + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + // If anything is in the last buffer, need to get it started + if (smc_chan->txbd->length != 0) { + quicc_smc_serial_flush(smc_chan); + // Note: interrupt will get masked after this buffer finishes + } else { + cyg_drv_interrupt_mask(smc_chan->int_num); + } + smc_chan->tx_enabled = false; +} + +// Serial I/O - low level interrupt handler (ISR) +static cyg_uint32 +quicc_smc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + cyg_drv_interrupt_mask(smc_chan->int_num); + return CYG_ISR_CALL_DSR; // Cause DSR to be run +} + +// Serial I/O - high level interrupt handler (DSR) +static void +quicc_smc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) +{ + serial_channel *chan = (serial_channel *)data; + quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv; + volatile struct smc_regs *ctl = smc_chan->ctl; + volatile struct cp_bufdesc *txbd; + volatile struct cp_bufdesc *rxbd = smc_chan->rxbd; + struct cp_bufdesc *rxlast; + int i, cache_state; + int _time, _stime; + externC cyg_tick_count_t cyg_current_time(void); +#ifdef CYGDBG_DIAG_BUF + cyg_drv_isr_lock(); + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR start - CE: %x, time: %x.%x\n", ctl->smc_smce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + if (ctl->smc_smce & QUICC_SMCE_TX) { +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + txbd = smc_chan->tbase; + for (i = 0; i < CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM; i++, txbd++) { + diag_printf("Tx BD: %x, length: %d, ctl: %x\n", txbd, txbd->length, txbd->ctrl); + } + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + // Transmit interrupt + ctl->smc_smce = QUICC_SMCE_TX; // Reset interrupt state; + txbd = smc_chan->tbase; // First buffer + while (true) { + if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) { +#ifdef XX_CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("TX Done - Tx: %x, length: %d, time: %x.%x\n", txbd, txbd->length, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + txbd->length = 0; + txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset interrupt bit + } + if (txbd->ctrl & QUICC_BD_CTL_Wrap) { + txbd = smc_chan->tbase; + break; + } else { + txbd++; + } + } + (chan->callbacks->xmt_char)(chan); + } + while (ctl->smc_smce & QUICC_SMCE_RX) { + // Receive interrupt + ctl->smc_smce = QUICC_SMCE_RX; // Reset interrupt state; + rxlast = (char *)eppc_base() + smc_chan->pram->rbptr; +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("Scan RX - rxbd: %x, rbptr: %x, time: %x.%x\n", rxbd, rxlast, _stime, _time); +#endif // CYGDBG_DIAG_BUF + while (rxbd != rxlast) { + if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) { +#ifdef CYGDBG_DIAG_BUF + diag_printf("rxbuf: %x, flags: %x, length: %d\n", rxbd, rxbd->ctrl, rxbd->length); + dump_buf(rxbd->buffer, rxbd->length); +#endif // CYGDBG_DIAG_BUF + for (i = 0; i < rxbd->length; i++) { + (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]); + } + // Note: the MBX860 does not seem to snoop/invalidate the data cache properly! + HAL_DCACHE_IS_ENABLED(cache_state); + if (cache_state) { + HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data + } + rxbd->length = 0; + rxbd->ctrl |= QUICC_BD_CTL_Ready; + } + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) { + rxbd = smc_chan->rbase; + } else { + rxbd++; + } + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + smc_chan->rxbd = (struct cp_bufdesc *)rxbd; + } + if (ctl->smc_smce & QUICC_SMCE_BSY) { +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + diag_printf("RX BUSY interrupt\n"); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + ctl->smc_smce = QUICC_SMCE_BSY; // Reset interrupt state; + } +#ifdef CYGDBG_DIAG_BUF + enable_diag_uart = 0; + HAL_CLOCK_READ(&_time); + _stime = (int)cyg_current_time(); + diag_printf("DSR done - CE: %x, time: %x.%x\n", ctl->smc_smce, _stime, _time); + enable_diag_uart = 1; +#endif // CYGDBG_DIAG_BUF + cyg_drv_interrupt_acknowledge(smc_chan->int_num); + cyg_drv_interrupt_unmask(smc_chan->int_num); +#ifdef CYGDBG_DIAG_BUF + cyg_drv_isr_unlock(); +#endif // CYGDBG_DIAG_BUF +} + +void +show_rxbd(int dump_all) +{ +#ifdef CYGDBG_DIAG_BUF + EPPC *eppc = eppc_base(); + struct smc_uart_pram *pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u; + struct cp_bufdesc *rxbd = (struct cp_bufdesc *)((char *)eppc+pram->rbase); + int _enable = enable_diag_uart; + enable_diag_uart = 0; +#if 1 + diag_printf("SMC Mask: %x, Events: %x, Rbase: %x, Rbptr: %x\n", + eppc->smc_regs[0].smc_smcm, eppc->smc_regs[0].smc_smce, + pram->rbase, pram->rbptr); + while (true) { + diag_printf("Rx BD: %x, ctl: %x, length: %d\n", rxbd, rxbd->ctrl, rxbd->length); + if (rxbd->ctrl & QUICC_BD_CTL_Wrap) break; + rxbd++; + } +#endif + enable_diag_uart = _enable; + if (dump_all) dump_diag_buf(); +#endif // CYGDBG_DIAG_BUF +} + +void +dump_buf_with_offset(unsigned char *p, + int s, + unsigned char *base) +{ + int i, c; + if ((unsigned int)s > (unsigned int)p) { + s = (unsigned int)s - (unsigned int)p; + } + while (s > 0) { + if (base) { + diag_printf("%08X: ", (int)p - (int)base); + } else { + diag_printf("%08X: ", p); + } + for (i = 0; i < 16; i++) { + if (i < s) { + diag_printf("%02X", p[i] & 0xFF); + } else { + diag_printf(" "); + } + if ((i % 2) == 1) diag_printf(" "); + if ((i % 8) == 7) diag_printf(" "); + } + diag_printf(" |"); + for (i = 0; i < 16; i++) { + if (i < s) { + c = p[i] & 0xFF; + if ((c < 0x20) || (c >= 0x7F)) c = '.'; + } else { + c = ' '; + } + diag_printf("%c", c); + } + diag_printf("|\n"); + s -= 16; + p += 16; + } +} + +void +dump_buf(unsigned char *p, int s) +{ + dump_buf_with_offset(p, s, 0); +} +#endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC +
new file mode 100644 --- /dev/null +++ b/packages/io/serial/current/src/powerpc/quicc_smc_serial.h @@ -0,0 +1,101 @@ +#ifndef CYGONCE_POWERPC_QUICC_SMC_SERIAL_H +#define CYGONCE_POWERPC_QUICC_SMC_SERIAL_H + +// ==================================================================== +// +// quicc_smc_serial.h +// +// Device I/O - Description of PowerPC QUICC/SMC serial hardware +// +// ==================================================================== +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Cygnus eCos Public License +// Version 1.0 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://sourceware.cygnus.com/ecos +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Cygnus Operating System, released +// September 30, 1998. +// +// The Initial Developer of the Original Code is Cygnus. Portions created +// by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +// ==================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 1999-06-21 +// Purpose: Internal interfaces for serial I/O drivers +// Description: +// +//####DESCRIPTIONEND#### +// +// ==================================================================== + +// Description of serial ports using QUICC/SMC + +#include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions + +static unsigned int select_word_length[] = { + QUICC_SMCMR_CLEN(5), // 5 bits / word (char) + QUICC_SMCMR_CLEN(6), + QUICC_SMCMR_CLEN(7), + QUICC_SMCMR_CLEN(8) +}; + +static unsigned int select_stop_bits[] = { + 0, + QUICC_SMCMR_SB(1), // 1 stop bit + QUICC_SMCMR_SB(1), // 1.5 stop bit + QUICC_SMCMR_SB(2) // 2 stop bits +}; + +static unsigned int select_parity[] = { + QUICC_SMCMR_PE(0), // No parity + QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(1), // Even parity + QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(0), // Odd parity + 0, // Mark parity + 0, // Space parity +}; + +// Baud rate values, based on board clock + +static cyg_int32 select_baud[] = { + 0, // Unused + 50, // 50 + 75, // 75 + 110, // 110 + 0, // 134.5 + 150, // 150 + 200, // 200 + 300, // 300 + 600, // 600 + 1200, // 1200 + 1800, // 1800 + 2400, // 2400 + 3600, // 3600 + 4800, // 4800 + 7200, // 7200 + 9600, // 9600 + 14400, // 14400 + 19200, // 19200 + 38400, // 38400 + 57600, // 57600 + 115200, // 115200 + 0, // 230400 +}; + +#define UART_BITRATE(n) (((CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED*1000000)/16)/n) +#define UART_SLOW_BITRATE(n) ((CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED*1000000)/n)) + +#endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
--- a/packages/io/serial/current/tests/PKGconf.mak +++ b/packages/io/serial/current/tests/PKGconf.mak @@ -34,8 +34,10 @@ include ../../../../pkgconf/system.mak TESTS := ifndef CYGPKG_HAL_I386_LINUX +ifdef CYGPKG_KERNEL TESTS += serial1 serial2 serial3 serial4 serial5 tty1 tty2 endif +endif include $(COMPONENT_REPOSITORY)/pkgconf/makrules.tst
--- a/packages/io/serial/current/tests/ser_test_protocol.inl +++ b/packages/io/serial/current/tests/ser_test_protocol.inl @@ -74,6 +74,15 @@ # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY2_DEV # endif #endif +#if defined(CYGPKG_HAL_POWERPC_MBX) \ + && defined(CYGPKG_HAL_QUICC) \ + && defined(CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC) \ + && defined(CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1) +# define TEST_SER_DEV CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME +# if defined(CYGPKG_IO_SERIAL_TTY_TTY1) +# define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV +# endif +#endif #if defined(CYGPKG_HAL_ARM_PID) \ && defined(CYGPKG_IO_SERIAL_ARM_PID) \ && defined(CYGPKG_IO_SERIAL_ARM_PID_SERIAL0) @@ -90,6 +99,14 @@ # define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV # endif #endif +#if defined(CYGPKG_HAL_ARM_CL7211) \ + && defined(CYGPKG_IO_SERIAL_ARM_CL7211) \ + && defined(CYGPKG_IO_SERIAL_ARM_CL7211_SERIAL1) +# define TEST_SER_DEV CYGDAT_IO_SERIAL_ARM_CL7211_SERIAL1_NAME +# if defined(CYGPKG_IO_SERIAL_TTY_TTY1) +# define TEST_TTY_DEV CYGDAT_IO_SERIAL_TTY_TTY1_DEV +# endif +#endif #if defined(CYGPKG_HAL_MIPS_TX39_JMR3904) \ && defined(CYGPKG_IO_SERIAL_TX39_JMR3904) \ && defined(CYGPKG_IO_SERIAL_TX39_JMR3904_SERIAL0) @@ -245,6 +262,7 @@ cyg_ser_cfg_t test_configs[] = { !defined(CYGPKG_HAL_ARM_PID) && \ !defined(CYGPKG_HAL_ARM_AEB) && \ !defined(CYGPKG_HAL_MN10300_STDEVAL1) && \ + !defined(CYGPKG_HAL_ARM_CL7211) && \ !defined(CYGPKG_HAL_SPARCLITE_SLEB) { CYGNUM_SERIAL_BAUD_115200, CYGNUM_SERIAL_WORD_LENGTH_8, CYGNUM_SERIAL_STOP_1, CYGNUM_SERIAL_PARITY_NONE },
--- a/packages/io/serial/current/tests/serial1.c +++ b/packages/io/serial/current/tests/serial1.c @@ -42,18 +42,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -110,7 +111,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)serial_test, // entry 0, // @@ -122,20 +122,23 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - serial_test(); -#endif } - -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } +#endif // N_A_MSG -#endif // EOF serial1.c
--- a/packages/io/serial/current/tests/serial2.c +++ b/packages/io/serial/current/tests/serial2.c @@ -44,16 +44,16 @@ #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -84,7 +84,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)serial_test, // entry 0, // @@ -96,19 +95,23 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - serial_test(); -#endif } -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } +#endif // N_A_MSG -#endif // EOF serial2.c
--- a/packages/io/serial/current/tests/serial3.c +++ b/packages/io/serial/current/tests/serial3.c @@ -44,18 +44,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -120,7 +121,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)serial_test, // entry 0, // @@ -132,19 +132,22 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - serial_test(); -#endif } -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } - -#endif +#endif // N_A_MSG // EOF serial3.c
--- a/packages/io/serial/current/tests/serial4.c +++ b/packages/io/serial/current/tests/serial4.c @@ -47,18 +47,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -99,7 +100,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)serial_test, // entry 0, // @@ -111,19 +111,23 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - serial_test(); -#endif } -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } +#endif // N_A_MSG -#endif // EOF serial4.c
--- a/packages/io/serial/current/tests/serial5.c +++ b/packages/io/serial/current/tests/serial5.c @@ -43,18 +43,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -104,7 +105,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)serial_test, // entry 0, // @@ -116,19 +116,22 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - serial_test(); -#endif } -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } - -#endif +#endif // N_A_MSG // EOF serial5.c
--- a/packages/io/serial/current/tests/tty1.c +++ b/packages/io/serial/current/tests/tty1.c @@ -42,18 +42,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -119,7 +120,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)tty_test, // entry 0, // @@ -131,20 +131,22 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - tty_test(); -#endif } - -#else // ifdef CYGPKG_IO_SERIAL +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } - -#endif +#endif // N_A_MSG // EOF tty1.c
--- a/packages/io/serial/current/tests/tty2.c +++ b/packages/io/serial/current/tests/tty2.c @@ -42,18 +42,19 @@ #include <cyg/infra/testcase.h> // test macros #include <cyg/infra/cyg_ass.h> // assertion macros +// Package requirements #if defined(CYGPKG_IO_SERIAL) && defined(CYGPKG_KERNEL) -#ifdef CYGPKG_KERNEL #include <pkgconf/kernel.h> -#ifdef CYGFUN_KERNEL_API_C + +// Package option requirements +#if defined(CYGFUN_KERNEL_API_C) + #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL #include <cyg/kernel/kapi.h> unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL]; cyg_thread thread_data; cyg_handle_t thread_handle; -#endif -#endif #include "ser_test_protocol.inl" @@ -84,7 +85,6 @@ void cyg_start(void) { CYG_TEST_INIT(); -#ifdef CYGFUN_KERNEL_API_C cyg_thread_create(10, // Priority - just a number (cyg_thread_entry_t*)tty_test, // entry 0, // @@ -96,19 +96,23 @@ cyg_start(void) ); cyg_thread_resume(thread_handle); cyg_scheduler_start(); -#else - tty_test(); -#endif } -#else // ifdef CYGPKG_IO_SERIAL + +#else // CYGFUN_KERNEL_API_C +#define N_A_MSG "Needs kernel C API" +#endif +#else // CYGPKG_IO_SERIAL && CYGPKG_KERNEL +#define N_A_MSG "Needs IO/serial and Kernel" +#endif + +#ifdef N_A_MSG void -cyg_start(void) +cyg_start( void ) { CYG_TEST_INIT(); - CYG_TEST_NA("Requires serial device driver and kernel"); + CYG_TEST_NA( N_A_MSG); } - -#endif +#endif // N_A_MSG // EOF tty2.c
--- a/packages/packages +++ b/packages/packages @@ -144,6 +144,12 @@ package CYGPKG_HAL_ARM_AEB { hardware } +package CYGPKG_HAL_ARM_CL7211 { + alias { "Cirrus Logic CL7211 evaulation board support" hal_arm_cl7211 arm_cl7211_hal } + directory hal/arm/cl7211 + include_dir cyg/hal + hardware +} @@ -224,6 +230,18 @@ package CYGPKG_HAL_POWERPC_FADS { hardware } +package CYGPKG_HAL_POWERPC_MBX { + alias { "PowerPC Motorola MBX860/821 board support" hal_powerpc_mbx powerpc_mbx_hal } + directory hal/powerpc/mbx + include_dir cyg/hal + hardware +} +package CYGPKG_HAL_QUICC { + alias { "PowerPC MBX860/821 QUICC support" hal_quicc quicc_hal quicc } + directory hal/powerpc/quicc + include_dir cyg/hal/quicc + hardware +} package CYGPKG_HAL_POWERPC_SIM { alias { "PowerPC simulator support" hal_powerpc_sim powerpc_sim_hal } directory hal/powerpc/sim
--- a/packages/targets +++ b/packages/targets @@ -169,6 +169,14 @@ target powerpc { CYGPKG_HAL_POWERPC_FADS } } + platform mbx { + alias { "MBX8xx board" } + startup { ram rom } + packages { + CYGPKG_HAL_POWERPC_MBX + CYGPKG_HAL_QUICC + } + } platform sim { alias { "Simulator" } startup { ram } @@ -240,6 +248,40 @@ target arm { LDLANGFLAGS "-Wl,--gc-sections -Wl,-static" } } + platform cl7111 { + alias { "Cirrus Logic Eval Board (CL7111)" } + startup { ram rom stubs } + base_platform cl7211 + packages { + CYGPKG_HAL_ARM_CL7211 + } + cflags { + ARCHFLAGS "-mcpu=arm710c -D__CL7111" + ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" + CXXERRFLAGS "-Woverloaded-virtual" + DBGFLAGS "-g -O2" + LANGFLAGS "-ffunction-sections -fdata-sections" + CXXLANGFLAGS "-fno-rtti -fno-exceptions -fvtable-gc -finit-priority" + LDLANGFLAGS "-Wl,--gc-sections -Wl,-static" + } + } +# FIXME: ARCHFLAGS "-mcpu=arm720" + platform cl7211 { + alias { "Cirrus Logic Eval Board (CL7211)" } + startup { ram rom stubs } + packages { + CYGPKG_HAL_ARM_CL7211 + } + cflags { + ARCHFLAGS "-mcpu=arm7tdmi -D__CL7211" + ERRFLAGS "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef" + CXXERRFLAGS "-Woverloaded-virtual" + DBGFLAGS "-g -O2" + LANGFLAGS "-ffunction-sections -fdata-sections" + CXXLANGFLAGS "-fno-rtti -fno-exceptions -fvtable-gc -finit-priority" + LDLANGFLAGS "-Wl,--gc-sections -Wl,-static" + } + } } target sparclite {