Mercurial > ecos-v3_0-branch
changeset 99:97d9d85b42c0 ecos-sw-2000-06-07
Merge from eCos master repository on 2000-06-07-14:25:36-BST
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--- a/host/tools/ecostest/common/eCosTestDownloadFilter.cpp +++ b/host/tools/ecostest/common/eCosTestDownloadFilter.cpp @@ -53,7 +53,7 @@ #include "eCosStd.h" #include "eCosTrace.h" -#define DL_FILTER_VER "$Id: eCosTestDownloadFilter.cpp,v 1.12 2000/06/06 08:39:36 jlarmour Exp $" +#define DL_FILTER_VER "$Id: eCosTestDownloadFilter.cpp,v 1.13 2000/06/07 14:10:34 jlarmour Exp $" #include "eCosTestDownloadFilter.h" CeCosTestDownloadFilter::CeCosTestDownloadFilter():
--- a/host/tools/ecostest/common/eCosTestMonitorFilter.cpp +++ b/host/tools/ecostest/common/eCosTestMonitorFilter.cpp @@ -45,7 +45,7 @@ #include "eCosStd.h" -#define SER_FILTER_VER "$Id: eCosTestMonitorFilter.cpp,v 1.11 2000/06/06 08:39:36 jlarmour Exp $" +#define SER_FILTER_VER "$Id: eCosTestMonitorFilter.cpp,v 1.12 2000/06/07 14:10:34 jlarmour Exp $" #include "eCosTestMonitorFilter.h" CeCosTestMonitorFilter::CeCosTestMonitorFilter():
--- a/host/tools/ecostest/common/eCosTestSerialFilter.cpp +++ b/host/tools/ecostest/common/eCosTestSerialFilter.cpp @@ -51,7 +51,7 @@ #include "eCosStd.h" -#define SER_FILTER_VER "$Id: eCosTestSerialFilter.cpp,v 1.12 2000/06/06 08:39:36 jlarmour Exp $" +#define SER_FILTER_VER "$Id: eCosTestSerialFilter.cpp,v 1.13 2000/06/07 14:10:34 jlarmour Exp $" #include "eCosTestSerialFilter.h" #include "eCosThreadUtils.h"
--- a/packages/NEWS +++ b/packages/NEWS @@ -1,3 +1,4 @@ +* Hitachi SH7709A variant support added * NEC V85x architecture support added * NEC Cosmo CEB-V850/SA1 evaluation board platform HAL added * Serial device drivers added for systems based on NEC V850 SA1 (70F3017)
--- a/packages/devs/eth/arm/ebsa285/current/ChangeLog +++ b/packages/devs/eth/arm/ebsa285/current/ChangeLog @@ -1,3 +1,8 @@ +2000-06-06 Hugo Tyson <hmt@cygnus.co.uk> + + * cdl/ebsa285_eth_drivers.cdl (define_proc): Add #define of + CYGDAT_DEVS_ETH_DESCRIPTION in the config file for information. + 2000-05-12 Hugo Tyson <hmt@cygnus.co.uk> * tests/test_net_realtime.h (tnr_print_activity): New routine to
--- a/packages/devs/eth/arm/ebsa285/current/cdl/ebsa285_eth_drivers.cdl +++ b/packages/devs/eth/arm/ebsa285/current/cdl/ebsa285_eth_drivers.cdl @@ -61,6 +61,8 @@ cdl_package CYGPKG_DEVS_ETH_ARM_EBSA285 define_proc { puts $::cdl_header \ "#define CYGTST_DEVS_ETH_TEST_NET_REALTIME <cyg/devs/eth/tests/test_net_realtime.h>" + puts $::cdl_header \ + "#define CYGDAT_DEVS_ETH_DESCRIPTION \"Intel EtherPro 10/100+ for EBSA285 (i82559/PCI)\"" puts $::cdl_system_header \ "#define CYGBLD_DEVS_ETH_DEVICE_H <pkgconf/devs_eth_arm_ebsa285.h>" }
--- a/packages/hal/mips/tx39/current/ChangeLog +++ b/packages/hal/mips/tx39/current/ChangeLog @@ -1,3 +1,9 @@ +2000-06-06 Jesper Skov <jskov@redhat.com> + + * include/var_intr.h (HAL_INTERRUPT_ACKNOWLEDGE, + HAL_INTERRUPT_CONFIGURE): Change the right bits. + (Haruki Kashiwaya) + 2000-04-06 Jonathan Larmour <jlarmour@redhat.co.uk> * src/mips_tx39.ld: Define __CTOR_LIST__, __CTOR_END__, __DTOR_LIST__,
--- a/packages/hal/mips/tx39/current/include/var_intr.h +++ b/packages/hal/mips/tx39/current/include/var_intr.h @@ -136,9 +136,19 @@ externC volatile CYG_BYTE hal_interrupt_ if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ { \ - cyg_uint32 _val_ = _vector_ + 1; \ - if( _val_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _val_ = 0; \ - HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _val_); \ + cyg_uint32 _v_ = _vector_ + 1; \ + cyg_uint8 _reg_; \ + \ + /* adjust vector to bit offset in CConR */ \ + if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \ + \ + /* get CConR */ \ + HAL_READ_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_ ); \ + \ + /* clear old value and set new */ \ + _reg_ &= ~(7 << 5); \ + _reg_ |= _v_ << 5; \ + HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_); \ } \ } @@ -147,10 +157,25 @@ externC volatile CYG_BYTE hal_interrupt_ if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \ _vector_ == CYGNUM_HAL_INTERRUPT_0 ) \ { \ + cyg_uint32 _v_ = _vector_ + 1; \ cyg_uint32 _val_ = 0; \ + cyg_uint16 _reg_; \ + \ + /* adjust vector to bit offset in CConR */ \ + if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \ + _v_ <<= 1; \ + \ + /* set bits according to requirements */ \ if( _up_ ) _val_ |= 1; \ if( !(_level_) ) _val_ |= 2; \ - HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _val_ ); \ + \ + /* get CConR */ \ + HAL_READ_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \ + \ + /* clear old value and set new */ \ + _reg_ &= ~(3 << _v_); \ + _reg_ |= _val_ << _v_; \ + HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \ } \ }
--- a/packages/hal/sh/arch/current/ChangeLog +++ b/packages/hal/sh/arch/current/ChangeLog @@ -1,8 +1,19 @@ +2000-06-06 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: INTEVT2 is not defined on all variants. Protect + accordingly. (Haruki Kashiwaya) + 2000-05-08 Jesper Skov <jskov@redhat.com> * cdl/hal_sh.cdl: Make sure CPU variant definition ends up in system.h +2000-05-01 Jesper Skov <jskov@redhat.com> + + * include/mod_7709a.h: + * include/sh_regs.h: + Add PFC/C definitions. + 2000-04-26 Jesper Skov <jskov@redhat.com> * src/hal_mk_defs.c: Added some caching data. @@ -17,6 +28,13 @@ 2000-04-25 Jesper Skov <jskov@redhat.c * include/hal_cache.h (HAL_UCACHE_WRITE_MODE): Also wiggle the WT bit. It has opposite polarity of the CB bit. +2000-04-25 Jesper Skov <jskov@redhat.com> + + * src/vectors.S: Init IPRC-E. Force IRQ mode. + * include/hal_intr.h: Added IRQ0-IRQ3 entries. Added simple + interrupt configuration and acknowledge. + * include/sh_regs.h: Added more interrupt control definitions. + 2000-04-12 Jesper Skov <jskov@redhat.com> * src/vectors.S: Entry code rewritten to allow ROMRAM startups. @@ -31,24 +49,67 @@ 2000-04-12 Jesper Skov <jskov@redhat.c 2000-04-10 Jesper Skov <jskov@redhat.com> + * src/vectors.S: Get interrupt event code from the proper register. + Removed some platform specific debug code. Let cyg_hal_gdb_isr + deal with C-c issues. + + * include/sh_regs.h: Moved module registers to + 0xa0000000-0xc0000000 which is also non-cachable. The reason is + that EVENT2 can only be accessed at 0xa4000000. + + * include/sh3_scif.inl: Read back SR before clearing it (or the + clear don't have an effect). + * include/hal_intr.h: Mask/unmask functions handle entire ISR range now. +2000-04-07 Jesper Skov <jskov@redhat.com> + + * include/sh3_scif.inl: Status register is 16 bit wide, not 8. + + * include/sh_regs.h: Access all module registers in the space + 0xe0000000-0xffffffff since caching is disabled here. + 2000-04-06 Jesper Skov <jskov@redhat.com> * src/sh.ld (_hal_vsr_table): Get address from platform CDL. +2000-04-04 Jesper Skov <jskov@redhat.com> + + * include/sh3_scif.inl: Should be able to work with FIFO enabled. + * include/sh_regs.h: Fixed RCOUNT/TCOUNT and added some comments. + +2000-04-03 Jesper Skov <jskov@redhat.com> + + * include/sh3_scif.inl: Can drive either IRDA or SCIF module. + + * include/sh_regs.h: + * include/mod_7709a.h: + Added IRDA definitions (mostly a copy of SCIF definitions). + 2000-03-31 Jesper Skov <jskov@redhat.com> * include/sh_regs.h: Added bit definitions for BSC. + * include/sh3_scif.inl: Added. + * include/hal_intr.h: Added hack to work around macro + problem. Need to rewrite macro as inline function, but need to + investigate a optimization problem first. * include/sh_regs.h: Replaced hardcoded baud rate constants with a macro which calculates the proper values based on baud rate and CPU clock speed. + * include/sh_regs.h: + * include/hal_intr.h (HAL_INTERRUPT_SET_LEVEL): + Level handling for 7709a added. + * src/vectors.S: ISR mask tables enabled per CPU variant, not target. +2000-03-30 Jesper Skov <jskov@redhat.com> + + * include/hal_intr.h: Added 7709a interrupt definitions. + 2000-03-20 Jesper Skov <jskov@redhat.com> * include/sh_regs.h: Add definitions for RTC module. @@ -59,6 +120,7 @@ 2000-03-20 Jesper Skov <jskov@redhat.c 2000-03-16 Jesper Skov <jskov@redhat.com> + * include/mod_7709a.h: * include/mod_7708.h: * include/sh_regs.h: Adding new module definitions, conditionally included depending on
--- a/packages/hal/sh/arch/current/cdl/hal_sh.cdl +++ b/packages/hal/sh/arch/current/cdl/hal_sh.cdl @@ -107,6 +107,21 @@ cdl_package CYGPKG_HAL_SH { } } + cdl_option CYGPKG_HAL_SH_7709A { + display "SH 7709A microprocessor" + implements CYGINT_HAL_SH_VARIANT + default_value 0 + no_define + define -file=system.h CYGPKG_HAL_SH_7709A + description " + The SH3 7709A microprocessor. This is an embedded part that in + addition to the SH3 processor core has built in peripherals + such as memory controllers, DMA controllers, A/D and D/A + converters, serial ports and timers/counters." + define_proc { + puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H <cyg/hal/mod_7709a.h>" + } + } cdl_option CYGHWR_HAL_SH_BIGENDIAN { display "Use big-endian mode"
--- a/packages/hal/sh/arch/current/include/hal_intr.h +++ b/packages/hal/sh/arch/current/include/hal_intr.h @@ -130,6 +130,45 @@ #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_REF_ROVI +//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME +#define CYGNUM_HAL_INTERRUPT_RESERVED_5C0 32 +#define CYGNUM_HAL_INTERRUPT_HUDI_HUDI 33 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 34 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 35 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 36 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 37 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 38 +#define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 39 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6C0 40 +#define CYGNUM_HAL_INTERRUPT_RESERVED_6E0 41 +#define CYGNUM_HAL_INTERRUPT_PINT_PINT07 42 +#define CYGNUM_HAL_INTERRUPT_PINT_PINT8F 43 +#define CYGNUM_HAL_INTERRUPT_RESERVED_740 44 +#define CYGNUM_HAL_INTERRUPT_RESERVED_760 45 +#define CYGNUM_HAL_INTERRUPT_RESERVED_780 46 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7A0 47 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7C0 48 +#define CYGNUM_HAL_INTERRUPT_RESERVED_7E0 59 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI0 50 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI1 51 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI2 52 +#define CYGNUM_HAL_INTERRUPT_DMAC_DEI3 53 +#define CYGNUM_HAL_INTERRUPT_IRDA_ERI1 54 +#define CYGNUM_HAL_INTERRUPT_IRDA_RXI1 55 +#define CYGNUM_HAL_INTERRUPT_IRDA_BRI1 56 +#define CYGNUM_HAL_INTERRUPT_IRDA_TXI1 57 +#define CYGNUM_HAL_INTERRUPT_SCIF_ERI2 58 +#define CYGNUM_HAL_INTERRUPT_SCIF_RXI2 69 +#define CYGNUM_HAL_INTERRUPT_SCIF_BRI2 60 +#define CYGNUM_HAL_INTERRUPT_SCIF_TXI2 61 +#define CYGNUM_HAL_INTERRUPT_ADC_ADI 62 + +#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME + +#undef CYGNUM_HAL_ISR_MAX +#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_ADC_ADI + +#endif // CYGARC_SH_MOD_INTC_V2 // CYGNUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S. #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI @@ -441,6 +480,93 @@ externC cyg_uint8 cyg_hal_ILVL_table[]; HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX); \ break; \ \ + /* IPRC */ \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \ + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \ + iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRC_IRQ0_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \ + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \ + iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRC_IRQ1_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \ + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \ + iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRC_IRQ2_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \ + HAL_READ_UINT16(CYGARC_REG_IPRC, iprX); \ + iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRC_IRQ3_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX); \ + break; \ + \ + /* IPRD */ \ + case CYGNUM_HAL_INTERRUPT_PINT_PINT07: \ + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \ + iprX &= ~CYGARC_REG_IPRD_PINT07_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRD_PINT07_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_PINT_PINT8F: \ + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \ + iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRD_PINT8F_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \ + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \ + iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRD_IRQ5_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \ + HAL_READ_UINT16(CYGARC_REG_IPRD, iprX); \ + iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRD_IRQ4_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX); \ + break; \ + \ + /* IPRE */ \ + case CYGNUM_HAL_INTERRUPT_DMAC_DEI0: \ + case CYGNUM_HAL_INTERRUPT_DMAC_DEI1: \ + case CYGNUM_HAL_INTERRUPT_DMAC_DEI2: \ + case CYGNUM_HAL_INTERRUPT_DMAC_DEI3: \ + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \ + iprX &= ~CYGARC_REG_IPRE_DMAC_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRE_DMAC_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRDA_ERI1: \ + case CYGNUM_HAL_INTERRUPT_IRDA_RXI1: \ + case CYGNUM_HAL_INTERRUPT_IRDA_BRI1: \ + case CYGNUM_HAL_INTERRUPT_IRDA_TXI1: \ + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \ + iprX &= ~CYGARC_REG_IPRE_IRDA_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRE_IRDA_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_SCIF_ERI2: \ + case CYGNUM_HAL_INTERRUPT_SCIF_RXI2: \ + case CYGNUM_HAL_INTERRUPT_SCIF_BRI2: \ + case CYGNUM_HAL_INTERRUPT_SCIF_TXI2: \ + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \ + iprX &= ~CYGARC_REG_IPRE_SCIF_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRE_SCIF_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \ + break; \ + case CYGNUM_HAL_INTERRUPT_ADC_ADI: \ + HAL_READ_UINT16(CYGARC_REG_IPRE, iprX); \ + iprX &= ~CYGARC_REG_IPRE_ADC_MASK; \ + iprX |= (_level_)*CYGARC_REG_IPRE_ADC_PRI1; \ + HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX); \ + break; \ + \ case CYGNUM_HAL_INTERRUPT_RESERVED_1E0: \ case CYGNUM_HAL_INTERRUPT_RESERVED_3E0: \ /* Do nothing for these reserved vectors. */ \ @@ -490,11 +616,86 @@ externC cyg_uint8 cyg_hal_ILVL_table[]; } \ CYG_MACRO_END - -#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) +#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ + CYG_MACRO_START \ + if ( (_vector_) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 \ + && (_vector_) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { \ + \ + cyg_uint8 irr0; \ + \ + HAL_READ_UINT8(CYGARC_REG_IRR0, irr0); \ + switch ( _vector_ ) { \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ0; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ1; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ2; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ3; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ4; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \ + irr0 &= ~CYGARC_REG_IRR0_IRQ5; \ + break; \ + } \ + HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0); \ + } \ + CYG_MACRO_END -#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) - +// Note: The PINTs can be masked and configured individually, even +// though there are only two vectors. Maybe add some fake vectors just +// for masking/configuring? +#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ + CYG_MACRO_START \ + if ( (_vector_) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 \ + && (_vector_) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) { \ + \ + cyg_uint16 icr1, ss, mask; \ + ss = 0; \ + mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL; \ + if (_up_) ss |= CYGARC_REG_ICR1_SENSE_UP; \ + if (_level_) ss |= CYGARC_REG_ICR1_SENSE_LEVEL; \ + CYG_ASSERT(!(_up_ && _level_), "Cannot trigger on high level!"); \ + \ + switch( (_vector_) ) { \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift; \ + break; \ + case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0: \ + ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; \ + mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift; \ + break; \ + } \ + \ + HAL_READ_UINT16(CYGARC_REG_ICR1, icr1); \ + icr1 &= ~mask; \ + icr1 |= ss; \ + HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1); \ + } \ + CYG_MACRO_END //-------------------------------------------------------------------------- // Clock control
new file mode 100644 --- /dev/null +++ b/packages/hal/sh/arch/current/include/mod_7709a.h @@ -0,0 +1,76 @@ +#ifndef CYGONCE_HAL_MOD_77xx_H +#define CYGONCE_HAL_MOD_77xx_H + +//============================================================================= +// +// mod_7709a.h +// +// List modules available on CPU +// +//============================================================================= +//####COPYRIGHTBEGIN#### +// +// ------------------------------------------- +// The contents of this file are subject to the Red Hat eCos Public License +// Version 1.1 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://www.redhat.com/ +// +// Software distributed under the License is distributed on an "AS IS" +// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the +// License for the specific language governing rights and limitations under +// the License. +// +// The Original Code is eCos - Embedded Configurable Operating System, +// released September 30, 1998. +// +// The Initial Developer of the Original Code is Red Hat. +// Portions created by Red Hat are +// Copyright (C) 1998, 1999, 2000 Red Hat, Inc. +// All Rights Reserved. +// ------------------------------------------- +// +//####COPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): jskov +// Contributors:jskov +// Date: 2000-03-16 +// Purpose: Define modules (and versions) available on this CPU. +// Usage: Included from <cyg/hal/sh_regs.h> +// +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +//----------------------------------------------------------------------------- +// Modules provided by the CPU + +#define CYGARC_SH_MOD_BCN_V2 +#define CYGARC_SH_MOD_INTC_V2 +#define CYGARC_SH_MOD_IRDA +#define CYGARC_SH_MOD_SCIF +#define CYGARC_SH_MOD_PFC + +//----------------------------------------------------------------------------- +// Extra details for Cache Module (CAC) + +// Cache dimenions - one unified cache +#define CYGARC_SH_MOD_CAC_SIZE 16384 // Size of cache in bytes +#define CYGARC_SH_MOD_CAC_LINE_SIZE 16 // Size of a cache line +#define CYGARC_SH_MOD_CAC_WAYS 4 // Associativity of the cache + +// Cache addressing information +// way: bits 13 - 12 +// entry: bits 11 - 4 +#define CYGARC_SH_MOD_CAC_ADDRESS_BASE 0xf0000000 +#define CYGARC_SH_MOD_CAC_ADDRESS_TOP 0xf0004000 +#define CYGARC_SH_MOD_CAC_ADDRESS_STEP 0x00000010 +// U : bit 1 +// V : bit 0 +// Writing zero to both forces a flush of the line if it is dirty. +#define CYGARC_SH_MOD_CAC_ADDRESS_FLUSH 0x00000000 + +#endif // CYGONCE_HAL_MOD_77xx_H
--- a/packages/hal/sh/arch/current/include/sh_regs.h +++ b/packages/hal/sh/arch/current/include/sh_regs.h @@ -327,6 +327,19 @@ #define CYGARC_REG_IPRA 0xfffffee2 #define CYGARC_REG_IPRB 0xfffffee4 +//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these +# define CYGARC_REG_INTEVT2 0xa4000000 +# define CYGARC_REG_IRR0 0xa4000004 +# define CYGARC_REG_IRR1 0xa4000006 +# define CYGARC_REG_IRR2 0xa4000008 +# define CYGARC_REG_ICR0 CYGARC_REG_ICR +# define CYGARC_REG_ICR1 0xa4000010 +# define CYGARC_REG_ICR2 0xa4000012 +# define CYGARC_REG_INTER 0xa4000014 +# define CYGARC_REG_IPRC 0xa4000016 +# define CYGARC_REG_IPRD 0xa4000018 +# define CYGARC_REG_IPRE 0xa400001a +//#endif #define CYGARC_REG_IPRA_TMU0_MASK 0xf000 #define CYGARC_REG_IPRA_TMU0_PRI1 0x1000 @@ -344,6 +357,57 @@ #define CYGARC_REG_IPRB_SCI_MASK 0x00f0 #define CYGARC_REG_IPRB_SCI_PRI1 0x0010 +//#ifdef CYGARC_SH_MOD_INTC_V2 // FIXME: HAL_INTERRUPT_SET_LEVEL needs these +#define CYGARC_REG_IPRC_IRQ3_MASK 0xf000 +#define CYGARC_REG_IPRC_IRQ3_PRI1 0x1000 +#define CYGARC_REG_IPRC_IRQ2_MASK 0x0f00 +#define CYGARC_REG_IPRC_IRQ2_PRI1 0x0100 +#define CYGARC_REG_IPRC_IRQ1_MASK 0x00f0 +#define CYGARC_REG_IPRC_IRQ1_PRI1 0x0010 +#define CYGARC_REG_IPRC_IRQ0_MASK 0x000f +#define CYGARC_REG_IPRC_IRQ0_PRI1 0x0001 + +#define CYGARC_REG_IPRD_PINT07_MASK 0xf000 +#define CYGARC_REG_IPRD_PINT07_PRI1 0x1000 +#define CYGARC_REG_IPRD_PINT8F_MASK 0x0f00 +#define CYGARC_REG_IPRD_PINT8F_PRI1 0x0100 +#define CYGARC_REG_IPRD_IRQ5_MASK 0x00f0 +#define CYGARC_REG_IPRD_IRQ5_PRI1 0x0010 +#define CYGARC_REG_IPRD_IRQ4_MASK 0x000f +#define CYGARC_REG_IPRD_IRQ4_PRI1 0x0001 + +#define CYGARC_REG_IPRE_DMAC_MASK 0xf000 +#define CYGARC_REG_IPRE_DMAC_PRI1 0x1000 +#define CYGARC_REG_IPRE_IRDA_MASK 0x0f00 +#define CYGARC_REG_IPRE_IRDA_PRI1 0x0100 +#define CYGARC_REG_IPRE_SCIF_MASK 0x00f0 +#define CYGARC_REG_IPRE_SCIF_PRI1 0x0010 +#define CYGARC_REG_IPRE_ADC_MASK 0x000f +#define CYGARC_REG_IPRE_ADC_PRI1 0x0001 + +#define CYGARC_REG_ICR1_MAI 0x8000 +#define CYGARC_REG_ICR1_IRQLVL 0x4000 +#define CYGARC_REG_ICR1_BLMSK 0x2000 +#define CYGARC_REG_ICR1_IRLSEN 0x1000 +#define CYGARC_REG_ICR1_SENSE_IRQ5_shift 10 +#define CYGARC_REG_ICR1_SENSE_IRQ4_shift 8 +#define CYGARC_REG_ICR1_SENSE_IRQ3_shift 6 +#define CYGARC_REG_ICR1_SENSE_IRQ2_shift 4 +#define CYGARC_REG_ICR1_SENSE_IRQ1_shift 2 +#define CYGARC_REG_ICR1_SENSE_IRQ0_shift 0 +#define CYGARC_REG_ICR1_SENSE_LEVEL 0x2 +#define CYGARC_REG_ICR1_SENSE_UP 0x1 + +#define CYGARC_REG_IRR0_PINT07 0x80 +#define CYGARC_REG_IRR0_PINT8F 0x40 +#define CYGARC_REG_IRR0_IRQ5 0x20 +#define CYGARC_REG_IRR0_IRQ4 0x10 +#define CYGARC_REG_IRR0_IRQ3 0x08 +#define CYGARC_REG_IRR0_IRQ2 0x04 +#define CYGARC_REG_IRR0_IRQ1 0x02 +#define CYGARC_REG_IRR0_IRQ0 0x01 + +//#endif //++++++ Module RTC ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ @@ -447,6 +511,357 @@ (CYGHWR_HAL_SH_BOARD_SPEED*1000000/(32*(_b_))-1)) #define CYGARC_SCBRR_CKSx(_b_) 0 +//++++++ Module IRDA +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_IRDA + +//-------------------------------------------------------------------------- +// IrDA (infrared data association). Can also act as regular serial w FIFO + +#define CYGARC_REG_SCSMR1 0xa4000140 +#define CYGARC_REG_SCBRR1 0xa4000142 +#define CYGARC_REG_SCSCR1 0xa4000144 +#define CYGARC_REG_SCFTDR1 0xa4000146 +#define CYGARC_REG_SCSSR1 0xa4000148 +#define CYGARC_REG_SCFRDR1 0xa400014a +#define CYGARC_REG_SCFCR1 0xa400014c +#define CYGARC_REG_SCFDR1 0xa400014e + +// Serial Mode Register +#define CYGARC_REG_SCSMR1_IRMOD 0x80 // IrDA Mode +#define CYGARC_REG_SCSMR1_ICK_MASK 0x78 // IR pulse width +#define CYGARC_REG_SCSMR1_PSEL 0x04 // IR pulse selector(?) +#define CYGARC_REG_SCSMR1_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR1_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR1_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR1_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR1_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR1_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR1_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR1_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR1_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR1_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR1_PER_shift 12 +#define CYGARC_REG_SCSSR1_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR1_FER_shift 8 +#define CYGARC_REG_SCSSR1_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR1_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR1_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR1_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR1_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR1_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR1_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR1_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR1_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR1_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR1_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR1_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR1_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR1_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR1_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR1_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR1_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR1_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR1_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR1_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR1_LOOP 0x01 // loop back test + + +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR1_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR1_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR1_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR1_TCOUNT_shift 8 + +// Baud rate values calculated for peripheral clock = 15MHz (Pf = 15). +// n is CKS setting (0-3) +// N = (Pf/(64*2^(2n-1)*B))*10^6-1 +// E(%) = ((Pf*10^6/((N+1)*B*(64^(n-1)))-1)*100 +// So this macro is only valid when serial is configured for n=0: +// N = (Pf/(32*B))*10^6-1 +#define CYGARC_SCBRR1_N(_b_) \ + (((_b_) < 4800) ? 0 : \ + ((_b_) > 115200) ? 0 : \ + (CYGHWR_HAL_SH_BOARD_SPEED*1000000/(32*(_b_))-1)) +#define CYGARC_SCBRR1_CKSx(_b_) 0 + +#endif // CYGARC_SH_MOD_IRDA + +//++++++ Module SCIF +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_SCIF + +//-------------------------------------------------------------------------- +// Serial w FIFO registers + +#define CYGARC_REG_SCSMR2 0xa4000150 // Serial mode +#define CYGARC_REG_SCBRR2 0xa4000152 // Bit rate +#define CYGARC_REG_SCSCR2 0xa4000154 // Serial control +#define CYGARC_REG_SCFTDR2 0xa4000156 // Transmit FIFO data +#define CYGARC_REG_SCSSR2 0xa4000158 // Serial status +#define CYGARC_REG_SCFRDR2 0xa400015a // Receive data FIFO +#define CYGARC_REG_SCFCR2 0xa400015c // FIFO control register +#define CYGARC_REG_SCFDR2 0xa400015e // FIFO data count set + +// Serial Mode Register +#define CYGARC_REG_SCSMR2_CHR 0x40 // character length (7 if set) +#define CYGARC_REG_SCSMR2_PE 0x20 // parity enable +#define CYGARC_REG_SCSMR2_OE 0x10 // parity mode +#define CYGARC_REG_SCSMR2_STOP 0x08 // stop bit length +#define CYGARC_REG_SCSMR2_CKS1 0x02 // clock select 1 +#define CYGARC_REG_SCSMR2_CKS0 0x01 // clock select 0 +#define CYGARC_REG_SCSMR2_CKSx_MASK 0x03 // mask + +// Serial Control Register +#define CYGARC_REG_SCSCR2_TIE 0x80 // transmit interrupt enable +#define CYGARC_REG_SCSCR2_RIE 0x40 // receive interrupt enable +#define CYGARC_REG_SCSCR2_TE 0x20 // transmit enable +#define CYGARC_REG_SCSCR2_RE 0x10 // receive enable +#define CYGARC_REG_SCSCR2_CKE1 0x02 // clock enable 1 +#define CYGARC_REG_SCSCR2_CKE0 0x01 // clock enable 0 + +// Serial Status Register +#define CYGARC_REG_SCSSR2_PER_MASK 0xf000 // number of parity errors +#define CYGARC_REG_SCSSR2_PER_shift 12 +#define CYGARC_REG_SCSSR2_FER_MASK 0x0f00 // number of framing errors +#define CYGARC_REG_SCSSR2_FER_shift 8 +#define CYGARC_REG_SCSSR2_ER 0x0080 // receive error +#define CYGARC_REG_SCSSR2_TEND 0x0040 // transmit end +#define CYGARC_REG_SCSSR2_TDFE 0x0020 // transmit fifo data empty +#define CYGARC_REG_SCSSR2_BRK 0x0010 // break detection +#define CYGARC_REG_SCSSR2_FER 0x0008 // framing error +#define CYGARC_REG_SCSSR2_PER 0x0004 // parity error +#define CYGARC_REG_SCSSR2_RDF 0x0002 // receive fifo data full +#define CYGARC_REG_SCSSR2_DR 0x0001 // receive data ready + +// When clearing the status register, always write the value: +// CYGARC_REG_SCSSR2_CLEARMASK & ~bit +// to prevent other bits than the one of interest to be cleared. +#define CYGARC_REG_SCSSR2_CLEARMASK 0xf3 + +// Serial FIFO Control Register +#define CYGARC_REG_SCFCR2_RTRG_MASK 0xc0 // receive fifo data trigger +#define CYGARC_REG_SCFCR2_RTRG_1 0x00 // trigger on 1 char +#define CYGARC_REG_SCFCR2_RTRG_4 0x40 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_RTRG_8 0x80 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_RTRG_14 0xc0 // trigger on 14 chars + +#define CYGARC_REG_SCFCR2_TTRG_MASK 0x30 // transmit fifo data trigger +#define CYGARC_REG_SCFCR2_TTRG_8 0x00 // trigger on 8 chars +#define CYGARC_REG_SCFCR2_TTRG_4 0x10 // trigger on 4 chars +#define CYGARC_REG_SCFCR2_TTRG_2 0x20 // trigger on 2 chars +#define CYGARC_REG_SCFCR2_TTRG_1 0x30 // trigger on 1 char + +#define CYGARC_REG_SCFCR2_MCE 0x08 // modem control enable +#define CYGARC_REG_SCFCR2_TFRST 0x04 // transmit fifo reset +#define CYGARC_REG_SCFCR2_RFRST 0x02 // receive fifo reset +#define CYGARC_REG_SCFCR2_LOOP 0x01 // loop back test +// Serial FIFO Data Count Set Register +#define CYGARC_REG_SCFDR2_RCOUNT_MASK 0x001f // number of chars in r fifo +#define CYGARC_REG_SCFDR2_RCOUNT_shift 0 +#define CYGARC_REG_SCFDR2_TCOUNT_MASK 0x1f00 // number of chars in t fifo +#define CYGARC_REG_SCFDR2_TCOUNT_shift 8 + +// Baud rate values calculated for peripheral clock = 15MHz (Pf = 15). +// n is CKS setting (0-3) +// N = (Pf/(64*2^(2n-1)*B))*10^6-1 +// E(%) = ((Pf*10^6/((N+1)*B*(64^(n-1)))-1)*100 +// So this macro is only valid when serial is configured for n=0: +// N = (Pf/(32*B))*10^6-1 +#define CYGARC_SCBRR2_N(_b_) \ + (((_b_) < 4800) ? 0 : \ + ((_b_) > 115200) ? 0 : \ + (CYGHWR_HAL_SH_BOARD_SPEED*1000000/(32*(_b_))-1)) +#define CYGARC_SCBRR2_CKSx(_b_) 0 + + +#endif // CYGARC_SH_MOD_SCIF + +//++++++ Module DMAC +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_DMAC + +//-------------------------------------------------------------------------- +// DMA Controller registers + +#define CYGARC_REG_SAR0 0xa4000020 +#define CYGARC_REG_DAR0 0xa4000024 +#define CYGARC_REG_DMATCR0 0xa4000028 +#define CYGARC_REG_CHCR0 0xa400002c +#define CYGARC_REG_SAR1 0xa4000030 +#define CYGARC_REG_DAR1 0xa4000034 +#define CYGARC_REG_DMATCR1 0xa4000038 +#define CYGARC_REG_CHCR1 0xa400003c +#define CYGARC_REG_SAR2 0xa4000040 +#define CYGARC_REG_DAR2 0xa4000044 +#define CYGARC_REG_DMATCR2 0xa4000048 +#define CYGARC_REG_CHCR2 0xa400004c +#define CYGARC_REG_SAR3 0xa4000050 +#define CYGARC_REG_DAR3 0xa4000054 +#define CYGARC_REG_DMATCR3 0xa4000058 +#define CYGARC_REG_CHCR3 0xa400005c +#define CYGARC_REG_DMAOR 0xa4000060 + +// DMA Channel Control Register 0 +#define CYGARC_REG_CHCR0_RL 0x00040000 // request check level +#define CYGARC_REG_CHCR0_AM 0x00020000 // acknowledge mode +#define CYGARC_REG_CHCR0_AL 0x00010000 // acknowledge level +#define CYGARC_REG_CHCR0_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR0_DM0 0x00004000 +#define CYGARC_REG_CHCR0_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR0_SM2 0x00001000 +#define CYGARC_REG_CHCR0_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR0_RS2 0x00000400 +#define CYGARC_REG_CHCR0_RS1 0x00000200 +#define CYGARC_REG_CHCR0_RS0 0x00000100 +#define CYGARC_REG_CHCR0_DS 0x00000040 // DREQ select +#define CYGARC_REG_CHCR0_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR0_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR0_TS0 0x00000008 +#define CYGARC_REG_CHCR0_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR0_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR0_DE 0x00000001 // DMAC enable + +// DMA Channel Control Register 1 +#define CYGARC_REG_CHCR1_RL 0x00040000 // request check level +#define CYGARC_REG_CHCR1_AM 0x00020000 // acknowledge mode +#define CYGARC_REG_CHCR1_AL 0x00010000 // acknowledge level +#define CYGARC_REG_CHCR1_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR1_DM0 0x00004000 +#define CYGARC_REG_CHCR1_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR1_SM2 0x00001000 +#define CYGARC_REG_CHCR1_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR1_RS2 0x00000400 +#define CYGARC_REG_CHCR1_RS1 0x00000200 +#define CYGARC_REG_CHCR1_RS0 0x00000100 +#define CYGARC_REG_CHCR1_DS 0x00000040 // DREQ select +#define CYGARC_REG_CHCR1_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR1_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR1_TS0 0x00000008 +#define CYGARC_REG_CHCR1_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR1_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR1_DE 0x00000001 // DMAC enable + +// DMA Channel Control Register 2 +#define CYGARC_REG_CHCR2_RO 0x00080000 // source address reload +#define CYGARC_REG_CHCR2_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR2_DM0 0x00004000 +#define CYGARC_REG_CHCR2_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR2_SM2 0x00001000 +#define CYGARC_REG_CHCR2_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR2_RS2 0x00000400 +#define CYGARC_REG_CHCR2_RS1 0x00000200 +#define CYGARC_REG_CHCR2_RS0 0x00000100 +#define CYGARC_REG_CHCR2_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR2_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR2_TS0 0x00000008 +#define CYGARC_REG_CHCR2_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR2_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR2_DE 0x00000001 // DMAC enable + +// DMA Channel Control Register 3 +#define CYGARC_REG_CHCR3_DI 0x00100000 // direct/indirect selection +#define CYGARC_REG_CHCR3_DM1 0x00008000 // destination address mode +#define CYGARC_REG_CHCR3_DM0 0x00004000 +#define CYGARC_REG_CHCR3_SM1 0x00002000 // source address mode +#define CYGARC_REG_CHCR3_SM2 0x00001000 +#define CYGARC_REG_CHCR3_RS3 0x00000800 // resource select +#define CYGARC_REG_CHCR3_RS2 0x00000400 +#define CYGARC_REG_CHCR3_RS1 0x00000200 +#define CYGARC_REG_CHCR3_RS0 0x00000100 +#define CYGARC_REG_CHCR3_TM 0x00000020 // transmit mode +#define CYGARC_REG_CHCR3_TS1 0x00000010 // transmit size +#define CYGARC_REG_CHCR3_TS0 0x00000008 +#define CYGARC_REG_CHCR3_IE 0x00000004 // interrupt enable +#define CYGARC_REG_CHCR3_TE 0x00000002 // transfer end +#define CYGARC_REG_CHCR3_DE 0x00000001 // DMAC enable + +// DMA Operation Register +#define CYGARC_REG_DMAOR_PR1 0x0200 // priority level +#define CYGARC_REG_DMAOR_PR0 0x0100 +#define CYGARC_REG_DMAOR_AE 0x0004 // address error flag +#define CYGARC_REG_DMAOR_NMIF 0x0002 // NMI flag +#define CYGARC_REG_DMAOR_DME 0x0001 // DMA master enable + + +#endif // CYGARC_SH_MOD_DMAC + +//++++++ Module PFC +++++++++++++++++++++++++++++++++++++++++++++++++++++++ +#ifdef CYGARC_SH_MOD_PFC + +#define CYGARC_REG_PACR 0xa4000100 // port A control +#define CYGARC_REG_PBCR 0xa4000102 // port B control +#define CYGARC_REG_PCCR 0xa4000104 // port C control +#define CYGARC_REG_PDCR 0xa4000106 // port D control +#define CYGARC_REG_PECR 0xa4000108 // port E control +#define CYGARC_REG_PFCR 0xa400010a // port F control +#define CYGARC_REG_PGCR 0xa400010c // port G control +#define CYGARC_REG_PHCR 0xa400010e // port H control +#define CYGARC_REG_PJCR 0xa4000110 // port J control +#define CYGARC_REG_PKCR 0xa4000112 // port K control +#define CYGARC_REG_PLCR 0xa4000114 // port L control +#define CYGARC_REG_SCPCR 0xa4000116 // SC port control + +#define CYGARC_REG_PADR 0xa4000120 // port A data +#define CYGARC_REG_PBDR 0xa4000122 // port B data +#define CYGARC_REG_PCDR 0xa4000124 // port C data +#define CYGARC_REG_PDDR 0xa4000126 // port D data +#define CYGARC_REG_PEDR 0xa4000128 // port E data +#define CYGARC_REG_PFDR 0xa400012a // port F data +#define CYGARC_REG_PGDR 0xa400012c // port G data +#define CYGARC_REG_PHDR 0xa400012e // port H data +#define CYGARC_REG_PJDR 0xa4000130 // port J data +#define CYGARC_REG_PKDR 0xa4000132 // port K data +#define CYGARC_REG_PLDR 0xa4000134 // port L data +#define CYGARC_REG_SCPDR 0xa4000136 // SC port data + + +// Port C +#define CYGARC_REG_PCCR_PC7_MASK 0xc000 +#define CYGARC_REG_PCCR_PC7_shift 14 +#define CYGARC_REG_PCCR_PC6_MASK 0x3000 +#define CYGARC_REG_PCCR_PC6_shift 12 +#define CYGARC_REG_PCCR_PC5_MASK 0x0c00 +#define CYGARC_REG_PCCR_PC5_shift 10 +#define CYGARC_REG_PCCR_PC4_MASK 0x0300 +#define CYGARC_REG_PCCR_PC4_shift 8 +#define CYGARC_REG_PCCR_PC3_MASK 0x00c0 +#define CYGARC_REG_PCCR_PC3_shift 6 +#define CYGARC_REG_PCCR_PC2_MASK 0x0030 +#define CYGARC_REG_PCCR_PC2_shift 4 +#define CYGARC_REG_PCCR_PC1_MASK 0x000c +#define CYGARC_REG_PCCR_PC1_shift 2 +#define CYGARC_REG_PCCR_PC0_MASK 0x0003 +#define CYGARC_REG_PCCR_PC0_shift 0 + +#define CYGARC_REG_PCCR_MD_OTHER 0x0 +#define CYGARC_REG_PCCR_MD_OUT 0x1 +#define CYGARC_REG_PCCR_MD_IN_ON 0x2 +#define CYGARC_REG_PCCR_MD_IN_OFF 0x3 + +#define CYGARC_REG_PCDR_PC7DT 0x80 +#define CYGARC_REG_PCDR_PC6DT 0x40 +#define CYGARC_REG_PCDR_PC5DT 0x20 +#define CYGARC_REG_PCDR_PC4DT 0x10 +#define CYGARC_REG_PCDR_PC3DT 0x08 +#define CYGARC_REG_PCDR_PC2DT 0x04 +#define CYGARC_REG_PCDR_PC1DT 0x02 +#define CYGARC_REG_PCDR_PC0DT 0x01 + + +#endif // CYGARC_SH_MOD_PFC + #endif // ifndef CYGONCE_HAL_SH_REGS_H
--- a/packages/hal/sh/arch/current/src/vectors.S +++ b/packages/hal/sh/arch/current/src/vectors.S @@ -120,6 +120,16 @@ mov.w r0,@r1 mov.l $CYGARC_REG_IPRB,r1 mov.w r0,@r1 +#ifdef CYGARC_SH_MOD_INTC_V2 + mov.l $CYGARC_REG_IPRC,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRD,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_IPRE,r1 + mov.w r0,@r1 + mov.l $CYGARC_REG_ICR1,r1 ! Set interrupt controller to IRQ mode + mov.w r0,@r1 +#endif # Initialize VBR if necessary #if !defined(CYG_HAL_STARTUP_RAM) || \ @@ -234,6 +244,17 @@ 1: mov.l @r0+,r3 .long CYGARC_REG_IPRA $CYGARC_REG_IPRB: .long CYGARC_REG_IPRB +#ifdef CYGARC_SH_MOD_INTC_V2 +$CYGARC_REG_IPRC: + .long CYGARC_REG_IPRC +$CYGARC_REG_IPRD: + .long CYGARC_REG_IPRD +$CYGARC_REG_IPRE: + .long CYGARC_REG_IPRE +$CYGARC_REG_ICR1: + .long CYGARC_REG_ICR1 +#endif + $__reset: .long __reset @@ -856,8 +877,10 @@ restore_state: .long CYG_SR $nCYG_SR_BANK1: .long CYG_SR_BANK1 +#ifdef CYGARC_SH_MOD_INTC_V2 $nCYGARC_REG_INTEVT2: .long CYGARC_REG_INTEVT2 +#endif $_hal_interrupt_handlers: .long _hal_interrupt_handlers $_hal_interrupt_data:
--- a/packages/hal/sh/cq7708/current/ChangeLog +++ b/packages/hal/sh/cq7708/current/ChangeLog @@ -1,3 +1,8 @@ +2000-06-06 Jesper Skov <jskov@redhat.com> + + * cdl/hal_sh_sh7708_cq7708.cdl: Added CYGHWR_HAL_SH_BOARD_SPEED + (from Haruki Kashiwaya). + 2000-06-05 John Dallaway <jld@redhat.com> * cdl/hal_sh_sh7708_cq7708.cdl:
--- a/packages/hal/sh/cq7708/current/cdl/hal_sh_sh7708_cq7708.cdl +++ b/packages/hal/sh/cq7708/current/cdl/hal_sh_sh7708_cq7708.cdl @@ -79,6 +79,14 @@ cdl_package CYGPKG_HAL_SH_SH7708_CQ7708 equivalent technology." } + cdl_option CYGHWR_HAL_SH_BOARD_SPEED { + display "Development board clock speed (MHz)" + flavor data + calculated 15 + description " + The CQ/7708 board uses a 15MHz crystal." + } + # Real-time clock/counter specifics cdl_component CYGNUM_HAL_RTC_CONSTANTS { display "Real-time clock constants." @@ -102,7 +110,7 @@ cdl_package CYGPKG_HAL_SH_SH7708_CQ7708 cdl_option CYGNUM_HAL_RTC_PERIOD { display "Real-time clock period" flavor data - calculated 37500 + calculated { CYGHWR_HAL_SH_BOARD_SPEED*1000000/CYGNUM_HAL_RTC_DENOMINATOR/4 } } }
--- a/packages/kernel/current/tests/kcache1.c +++ b/packages/kernel/current/tests/kcache1.c @@ -323,7 +323,7 @@ static void entry0( cyg_addrword_t data // slow on the simulator, even with reduced loop counts. if (cyg_test_is_simulator) CYG_TEST_PASS_FINISH("End of test"); - + cyg_test_is_simulator = 1; #endif #ifdef HAL_ICACHE_INVALIDATE_ALL
--- a/packages/net/tcpip/current/include/bootp.h +++ b/packages/net/tcpip/current/include/bootp.h @@ -80,7 +80,7 @@ SOFTWARE. /* * Bootstrap Protocol (BOOTP). RFC951 and RFC1395. * - * $Id: bootp.h,v 1.1 2000/06/06 08:39:39 jlarmour Exp $ + * $Id: bootp.h,v 1.2 2000/06/07 14:10:35 jlarmour Exp $ * * * This file specifies the "implementation-independent" BOOTP protocol
--- a/packages/net/tcpip/current/include/netinet/ip_auth.h +++ b/packages/net/tcpip/current/include/netinet/ip_auth.h @@ -61,7 +61,7 @@ * provided that this notice is preserved and due credit is given * to the original author and the contributors. * - * $Id: ip_auth.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_auth.h,v 1.2 2000/06/07 14:10:35 jlarmour Exp $ * */
--- a/packages/net/tcpip/current/include/netinet/ip_fil.h +++ b/packages/net/tcpip/current/include/netinet/ip_fil.h @@ -62,7 +62,7 @@ * to the original author and the contributors. * * @(#)ip_fil.h 1.35 6/5/96 - * $Id: ip_fil.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_fil.h,v 1.2 2000/06/07 14:10:35 jlarmour Exp $ */ #ifndef _NETINET_IP_FIL_H__
--- a/packages/net/tcpip/current/include/netinet/ip_fil_compat.h +++ b/packages/net/tcpip/current/include/netinet/ip_fil_compat.h @@ -62,7 +62,7 @@ * to the original author and the contributors. * * @(#)ip_compat.h 1.8 1/14/96 - * $Id: ip_fil_compat.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_fil_compat.h,v 1.2 2000/06/07 14:10:35 jlarmour Exp $ */ #ifndef _NETINET_IP_COMPAT_H__
--- a/packages/net/tcpip/current/include/netinet/ip_frag.h +++ b/packages/net/tcpip/current/include/netinet/ip_frag.h @@ -62,7 +62,7 @@ * to the original author and the contributors. * * @(#)ip_frag.h 1.5 3/24/96 - * $Id: ip_frag.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_frag.h,v 1.2 2000/06/07 14:10:36 jlarmour Exp $ */ #ifndef _NETINET_IP_FRAG_H__
--- a/packages/net/tcpip/current/include/netinet/ip_nat.h +++ b/packages/net/tcpip/current/include/netinet/ip_nat.h @@ -62,7 +62,7 @@ * to the original author and the contributors. * * @(#)ip_nat.h 1.5 2/4/96 - * $Id: ip_nat.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_nat.h,v 1.2 2000/06/07 14:10:36 jlarmour Exp $ */ #ifndef _NETINET_IP_NAT_H__
--- a/packages/net/tcpip/current/include/netinet/ip_proxy.h +++ b/packages/net/tcpip/current/include/netinet/ip_proxy.h @@ -61,7 +61,7 @@ * provided that this notice is preserved and due credit is given * to the original author and the contributors. * - * $Id: ip_proxy.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_proxy.h,v 1.2 2000/06/07 14:10:36 jlarmour Exp $ */ #ifndef _NETINET_IP_PROXY_H__
--- a/packages/net/tcpip/current/include/netinet/ip_state.h +++ b/packages/net/tcpip/current/include/netinet/ip_state.h @@ -62,7 +62,7 @@ * to the original author and the contributors. * * @(#)ip_state.h 1.3 1/12/96 (C) 1995 Darren Reed - * $Id: ip_state.h,v 1.1 2000/06/06 08:39:40 jlarmour Exp $ + * $Id: ip_state.h,v 1.2 2000/06/07 14:10:36 jlarmour Exp $ */ #ifndef _NETINET_IP_STATE_H__