--- a/packages/hal/arm/at91/var/current/ChangeLog
+++ b/packages/hal/arm/at91/var/current/ChangeLog
@@ -1,3 +1,7 @@
+2006-02-25  Andrew Lunn  <andrew.lunn@ascom.ch>
+
+	* include/var_io.h: Added the USB device registers.
+
 2006-02-19  Andrew Lunn  <andrew.lunn@ascom.ch>
            Oliver Munz  <munz@speag.ch>
 

--- a/packages/hal/arm/at91/var/current/include/var_io.h
+++ b/packages/hal/arm/at91/var/current/include/var_io.h
@@ -229,7 +229,7 @@
 #define AT91_PIO_PSR_RTS0     0x00000080 // USART 0 Ready To Send
 #define AT91_PIO_PSR_CTS0     0x00000100 // USART 0 Clear To Send
 #define AT91_PIO_PSR_DRXD     0x00000200 // Debug UART Receive
-#define AT91_PIO_PSR_DTXD     0x00000400 // Debug UAET Transmit
+#define AT91_PIO_PSR_DTXD     0x00000400 // Debug UART Transmit
 #define AT91_PIO_PSR_NPCS0    0x00000800 // SPI Chip Select 0
 #define AT91_PIO_PSR_MISO     0x00001000 // SPI Input
 #define AT91_PIO_PSR_MOIS     0x00002000 // SPI Output
@@ -1179,6 +1179,72 @@
 #endif
 
 //=============================================================================
+// Real Time Timer Controller
+
+#if defined(CYGHWR_HAL_ARM_AT91SAM7S)
+
+#ifndef AT91_UDP
+#define AT91_UDP 0xFFFB0000
+#endif
+
+#define AT91_UDP_FRM_NUM    0x00  // Frame Number
+#define AT91_UDP_FRM_ERR     (1 << 16) // Frame Error
+#define AT91_UDP_FRM_OK      (1 << 17) // Frame OK
+#define AT91_UDP_GLB_STATE  0x04  // Global State
+#define AT91_UDP_GLB_FADDEN  (1 <<  0) // Function Address Enable
+#define AT91_UDP_GLB_CONFG   (1 <<  1) // Configured
+#define AT91_UDP_GLB_ESR     (1 <<  2) // Enable Send Resume
+#define AT91_UDP_GLB_RSMINPR (1 <<  3) // A Resume has been seen
+#define AT91_UDP_GLB_RMWUPE  (1 <<  4) // Remote Wake Up Enable
+#define AT91_UDP_FADDR      0x08  // Function Address
+#define AT91_UDP_FADDR_FEN   (1 <<  8) // Function Enable
+#define AT91_UDP_IER        0x10  // Interrupt Enable
+#define AT91_UDP_EPINT0      (1 <<  0) // Endpoint 0 Interrupt
+#define AT91_UDP_EPINT1      (1 <<  1) // Endpoint 1 Interrupt
+#define AT91_UDP_EPINT2      (1 <<  2) // Endpoint 2 Interrupt
+#define AT91_UDP_EPINT3      (1 <<  3) // Endpoint 3 Interrupt
+#define AT91_UDP_EPINT4      (1 <<  4) // Endpoint 4 Interrupt
+#define AT91_UDP_EPINT5      (1 <<  5) // Endpoint 5 Interrupt
+#define AT91_UDP_EPINT6      (1 <<  6) // Endpoint 6 Interrupt
+#define AT91_UDP_EPINT7      (1 <<  7) // Endpoint 7 Interrupt
+#define AT91_UDP_RXSUSP      (1 <<  8) // USB Suspend Interrupt
+#define AT91_UDP_RXRSM       (1 <<  9) // USB Resume Interrupt
+#define AT91_UDP_EXTRSM      (1 << 10) // USB External Resume Interrupt
+#define AT91_UDP_SOFINT      (1 << 11) // USB start of frame Interrupt
+#define AT91_UDP_ENDBUSRES   (1 << 12) // USB End of Bus Reset Interrupt
+#define AT91_UDP_WAKEUP      (1 << 13) // USB Resume Interrupt
+#define AT91_UDP_IDR        0x14  // Interrupt Disable
+#define AT91_UDP_IMR        0x18  // Interrupt Mask
+#define AT91_UDP_ISR        0x1C  // Interrupt Status
+#define AT91_UDP_ICR        0x20  // Interrupt Clear
+#define AT91_UDP_RST_EP     0x28  // Reset Endpoint
+#define AT91_UDP_CSR        0x30  // Endpoint Control and Status
+#define AT91_UDP_CSR_TXCOMP      (1 <<  0) // Generates an IN packet
+#define AT91_UDP_CSR_RX_DATA_BK0 (1 <<  1) // Receive Data Bank 0
+#define AT91_UDP_CSR_RXSETUP     (1 <<  2) // Sends a STALL to the host
+#define AT91_UDP_CSR_ISOERROR    (1 <<  3) // Isochronous error
+#define AT91_UDP_CSR_TXPKTRDY    (1 <<  4) // Transmit Packet Ready
+#define AT91_UDP_CSR_FORCESTALL  (1 <<  5) // Force Stall
+#define AT91_UDP_CSR_RX_DATA_BK1 (1 <<  6) // Receive Data Bank 1
+#define AT91_UDP_CSR_DIR         (1 <<  7) // Transfer Direction
+#define AT91_UDP_CSR_DIR_OUT     (0 <<  7) // Transfer Direction OUT
+#define AT91_UDP_CSR_DIR_IN      (1 <<  7) // Transfer Direction IN
+#define AT91_UDP_CSR_EPTYPE_CTRL     (0 << 9) // Control
+#define AT91_UDP_CSR_EPTYPE_ISO_OUT  (1 << 9) // Isochronous OUT
+#define AT91_UDP_CSR_EPTYPE_BULK_OUT (2 << 9) // Bulk OUT
+#define AT91_UDP_CSR_EPTYPE_INT_OUT  (3 << 9) // Interrupt OUT
+#define AT91_UDP_CSR_EPTYPE_ISO_IN   (5 << 9) // Isochronous IN
+#define AT91_UDP_CSR_EPTYPE_BULK_IN  (6 << 9) // Bulk IN
+#define AT91_UDP_CSR_EPTYPE_INT_IN   (6 << 9) // Interrupt IN
+#define AT91_UDP_CSR_DTGLE       (1 << 11) // Data Toggle
+#define AT91_UDP_CSR_EPEDS       (1 << 15) // Endpoint Enable Disable
+#define AT91_UDP_FDR        0x50  // Endpoint FIFO Data
+#define AT91_UDP_TXVC       0x74  // Transceiver Control
+#define AT91_UDP_TXVC_TXVDIS     (1 <<  8) // Disable Transceiver
+#define AT91_UDP_TXVC_PUON       (1 <<  9) // Pull-up ON
+#endif
+
+//=============================================================================
 // FIQ interrupt vector which is shared by all HAL varients.
 
 #define CYGNUM_HAL_INTERRUPT_FIQ 0

--- a/packages/hal/arm/at91/var/current/src/timer_tc.c
+++ b/packages/hal/arm/at91/var/current/src/timer_tc.c
@@ -129,7 +129,13 @@ void hal_delay_us(cyg_int32 usecs)
     ticks = (((cyg_uint64)usecs) * 
              ((cyg_uint64)CYGNUM_HAL_ARM_AT91_CLOCK_SPEED))/32000000LL;
     
-    CYG_ASSERT(ticks < (1 << 16), "Timer overflow");
+    //    CYG_ASSERT(ticks < (1 << 16), "Timer overflow");
+    
+    if (ticks > (1 << 16))
+      ticks = (1 << 16) - 1;
+    
+    if (ticks == 0)
+      return;
     
     // Disable counter
     HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);