Mercurial > ecos-v3_0-branch
changeset 1901:d5547d5dab7a
* src/xsengine_misc.c:
* misc/redboot_ROM.ecm:
* misc/redboot_RAM.ecm:
* include/pkgconf/mlt_arm_xscale_xsengine_rom.mlt:
* include/pkgconf/mlt_arm_xscale_xsengine_rom.ldi:
* include/pkgconf/mlt_arm_xscale_xsengine_rom.h:
* include/pkgconf/mlt_arm_xscale_xsengine_ram.mlt:
* include/pkgconf/mlt_arm_xscale_xsengine_ram.ldi:
* include/pkgconf/mlt_arm_xscale_xsengine_ram.h:
* include/xsengine.h:
* include/plf_io.h:
* include/hal_platform_setup.h:
* cdl/hal_arm_xscale_xsengine.cdl:
New package - support for Exys XSEngine (Xscale PXA255) platform.
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new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/ChangeLog @@ -0,0 +1,49 @@ +2005-02-23 Kurt Stremerch <kurt.stremerch@exys.be> + + * src/xsengine_misc.c: + * misc/redboot_ROM.ecm: + * misc/redboot_RAM.ecm: + * include/pkgconf/mlt_arm_xscale_xsengine_rom.mlt: + * include/pkgconf/mlt_arm_xscale_xsengine_rom.ldi: + * include/pkgconf/mlt_arm_xscale_xsengine_rom.h: + * include/pkgconf/mlt_arm_xscale_xsengine_ram.mlt: + * include/pkgconf/mlt_arm_xscale_xsengine_ram.ldi: + * include/pkgconf/mlt_arm_xscale_xsengine_ram.h: + * include/xsengine.h: + * include/plf_io.h: + * include/hal_platform_setup.h: + * cdl/hal_arm_xscale_xsengine.cdl: + New package - support for Exys XSEngine (Xscale PXA255) platform. + +//=========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2005 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/cdl/hal_arm_xscale_xsengine.cdl @@ -0,0 +1,353 @@ +# ==================================================================== +# +# hal_arm_xscale_xsengine.cdl +# +# Exys XSEngine platform HAL package configuration data +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## Copyright (C) 2005 eCosCentric Ltd. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### +# ==================================================================== +######DESCRIPTIONBEGIN#### +# +# Author(s): msalter +# Contributors: hmt, gary thomas +# Date: 2001-12-03 +# +#####DESCRIPTIONEND#### +# ==================================================================== + +cdl_package CYGPKG_HAL_ARM_XSCALE_XSENGINE { + display "Exys XSEngine" + parent CYGPKG_HAL_ARM_XSCALE + hardware + include_dir cyg/hal + define_header hal_arm_xscale_xsengine.h + description " + This HAL platform package provides + support for the Exys XSEngine CPU board." + + compile xsengine_misc.c + + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT + implements CYGHWR_HAL_ARM_PXA2X0_FFUART + implements CYGHWR_HAL_ARM_PXA2X0_BTUART + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_arm_xscale_pxa2x0.h>" + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_xscale_xsengine.h>" + puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale PXA255\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Exys XSEngine\"" + puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 532" + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"RAM"} + legal_values {"RAM" "ROM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targeting the xsengine eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'RAM' when building programs to load into RAM using onboard + debug software such as Angel or eCos GDB stubs. Select 'ROM' + when building a stand-alone application which will be put + into ROM." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 ; + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 ; + description " + This option selects the baud rate used for the diagnostic port. + Note: this should match the value chosen for the GDB port if the + diagnostic and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 2 + description " + FFUART and BTUART are the serial ports on the board." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The XSEngine has two serial ports." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Diagnostic serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The XSEngine has only two serial ports." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -mapcs-frame -fno-builtin" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ + } + } + } + + cdl_component CYGPKG_HAL_ARM_XSCALE_XSENGINE_OPTIONS { + display "Exys XSEngine build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_XSCALE_XSENGINE_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale XSEngine HAL. These flags are used + in addition to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_XSCALE_XSENGINE_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the XScale XSEngine HAL. These flags are + removed from the set of global flags if present." + } + + cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { + display "Number of breakpoints supported by the HAL." + flavor data + default_value 32 + description " + This option determines the number of breakpoints + supported by the HAL." + } + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { CYG_HAL_STARTUP == "RAM" ? "arm_xscale_xsengine_ram" : \ + "arm_xscale_xsengine_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { CYG_HAL_STARTUP == "RAM" ? \ + "<pkgconf/mlt_arm_xscale_xsengine_ram.ldi>" : \ + "<pkgconf/mlt_arm_xscale_xsengine_rom.ldi>" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { CYG_HAL_STARTUP == "RAM" ? \ + "<pkgconf/mlt_arm_xscale_xsengine_ram.h>" : \ + "<pkgconf/mlt_arm_xscale_xsengine_rom.h>" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM"} + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + # compile -library=libextras.a redboot_cmds.c + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + # compile -library=libextras.a redboot_cmds.c + + make -priority 325 { + <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + } + } + } + +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/hal_platform_setup.h @@ -0,0 +1,354 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +/*============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2005 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================*/ +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Kurt Stremerch +// Contributors: Gary Thomas +// Date: 2003-02-23 +// +//####DESCRIPTIONEND#### + +#include <pkgconf/system.h> // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include <cyg/hal/hal_pxa2x0.h> // Variant specific hardware definitions +#include <cyg/hal/hal_mmu.h> // MMU definitions +#include <cyg/hal/hal_mm.h> // more MMU definitions +#include <cyg/hal/xsengine.h> // Platform specific hardware definitions +#include <cyg/hal/hal_spd.h> + +#define MDCNFG_VALUE 0x000009C9 +#define MDMRS_VALUE 0x00220022 +#define MDREFR_VALUE_1 0x00018018 +#define MDREFR_VALUE_2 0x00000000 +#define MDREFR_VALUE_3 0x00000000 + +#define GPCR0_VALUE 0xFFFFFFFF +#define GPCR1_VALUE 0xFFFFFFFF +#define GPCR2_VALUE 0xFFFFFFFF + +#define GPSR0_VALUE 0x0000A000 +#define GPSR1_VALUE 0x00020000 +#define GPSR2_VALUE 0x0000C000 + +#define GPDR0_VALUE 0x0000A000 +#define GPDR1_VALUE 0x00022A80 +#define GPDR2_VALUE 0x0000C000 + +#define GAFR0_L_VALUE 0x80000000 +#define GAFR0_U_VALUE 0x00000010 +#define GAFR1_L_VALUE 0x09988050 +#define GAFR1_U_VALUE 0x00000008 +#define GAFR2_L_VALUE 0xA0000000 +#define GAFR2_U_VALUE 0x00000000 + +#define PSSR_VALUE 0x20 +#define MSC0_VALUE_NONBURST 0x25F425F0 +#define MSC0_VALUE_BURST 0x25F425F0 + +#define MDCNFG_DE0 0x00000001 +#define MDCNFG_DE1 0x00000002 +#define MDCNFG_DE2 0x00010000 +#define MDCNFG_DE3 0x00020000 + +#undef XSDEBUG + +#if defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU +#define CYGSEM_HAL_ROM_RESET_USES_JUMP + +// This macro represents the initial startup code for the platform + .macro _platform_setup1 + // This is where we wind up immediately after reset. At this point, we + // are executing from the boot address (0x00000000), not the eventual + // flash address. Do some basic setup using position independent code + // then switch to real flash address + +// FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME +// This is a quick and dirty workaround to an apparent gas/ld +// bug. The computed UNMAPPED_PTR(reset_vector) is off by 0x20. + .rept 0x20/4 + nop + .endr +// FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME + +#if defined(XSDEBUG) + ldr r0,=PXA2X0_GPDR1 /* GPIO as output */ + ldr r1,=0x80 + str r1,[r0] + ldr r0,=PXA2X0_GAFR1_L /* GPIO as decated BTUART */ + ldr r1,=0x0088000 + str r1,[r0] + ldr r0,=PXA2X0_FFLCR /* 8bit char + DLAB(Divisor access) */ + ldr r1,=0x83 + str r1,[r0] + ldr r0,=PXA2X0_FFDLL /* Divisor to 115200 */ + ldr r1,=8 + str r1,[r0] + ldr r0,=PXA2X0_FFLCR /* DLAB off */ + ldr r1,=0x3 + str r1,[r0] + ldr r0,=PXA2X0_FFIER /* enable UART */ + ldr r1,=0x40 + str r1,[r0] + ldr r0,=PXA2X0_FFTHR /* send char A */ + ldr r1,=0x41 + str r1,[r0] +#endif + + // Disable interrupts, by setting the Interrupt Mask Registers to all 0's + ldr r1,=PXA2X0_ICMR + mov r0,#0 + str r0,[r1] + + // disable MMU + mov r0, #0x0 + mcr p15, 0, r0, c1, c0, 0 + + // flush TLB + mov r0, #0x0 + mcr p15, 0, r0, c8, c7, 0 // Flush TLB + + // flush I&D caches and BTB + mov r0, #0x0 + mcr p15, 0, r0, c7, c7, 0 // Flush caches + + CPWAIT r0 + + // Enables access to coprocessor 0 (The only extra coprocessor on the PXA250) + ldr r0, =0x00000001 + mcr p15, 0, r0, c15, c1, 0 + + // Disable the IRQ's and FIQ's in the program status register and + // enable supervisor mode + ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) + msr cpsr, r0 + + // Set TURBO mode + + ldr r2, =0x00000321 + ldr r1, =PXA2X0_CCCR + str r2,[r1] + + ldr r1, =0x00000003 + mcr p14, 0, r1, c6, c0, 0 + + // Set-up memory according to Eyxs specs + // Set Refresh Values + ldr r1,=PXA2X0_MDREFR + ldr r2,=MDREFR_VALUE_1 + str r2,[r1] + + //fetch platform value SDRAM + ldr r1,=PXA2X0_MDCNFG + ldr r2,=MDCNFG_VALUE + + bic r2,r2,#(MDCNFG_DE0|MDCNFG_DE1) + bic r2,r2,#(MDCNFG_DE2|MDCNFG_DE3) + + str r2,[r1] + + // pause for 200 uSecs + ldr r3, =PXA2X0_OSCR + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + ldr r2,=PXA2X0_RAM_BANK0_BASE + str r2,[r2] + str r2,[r2] + str r2,[r2] + str r2,[r2] + str r2,[r2] + str r2,[r2] + str r2,[r2] + str r2,[r2] + + ldr r1,=PXA2X0_MDCNFG + ldr r2,=MDCNFG_VALUE + str r2,[r1] + + ldr r1,=PXA2X0_MDMRS + ldr r2,=MDMRS_VALUE + str r2,[r1] + +#if defined(XSDEBUG) + ldr r0,=PXA2X0_FFTHR /* send char B */ + ldr r1,=0x42 + str r1,[r0] +#endif + + // Set Static memory registers + ldr r1,=PXA2X0_MSC0 + ldr r2,=MSC0_VALUE_NONBURST + str r2,[r1] + + // Setup GPIO clear registers + ldr r1, =PXA2X0_GPCR0 + ldr r2, =(GPCR0_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPCR1 + ldr r2, =(GPCR1_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPCR2 + ldr r2, =(GPCR2_VALUE) + str r2, [r1] + + // Setup GPIO set registers + ldr r1, =PXA2X0_GPSR0 + ldr r2, =(GPSR0_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPSR1 + ldr r2, =(GPSR1_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPSR2 + ldr r2, =(GPSR2_VALUE) + str r2, [r1] + + // Setup GPIO direction registers + ldr r1, =PXA2X0_GPDR0 + ldr r2, =(GPDR0_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPDR1 + ldr r2, =(GPDR1_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GPDR2 + ldr r2, =(GPDR2_VALUE) + str r2, [r1] + + // Setup GPIO alternate function registers + ldr r1, =PXA2X0_GAFR0_L + ldr r2, =(GAFR0_L_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GAFR0_U + ldr r2, =(GAFR0_U_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GAFR1_L + ldr r2, =(GAFR1_L_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GAFR1_U + ldr r2, =(GAFR1_U_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GAFR2_L + ldr r2, =(GAFR2_L_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_GAFR2_U + ldr r2, =(GAFR2_U_VALUE) + str r2, [r1] + + ldr r1, =PXA2X0_PSSR + ldr r2, =(PSSR_VALUE) + str r2, [r1] + + // Enable the Icache + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + +#if defined(XSDEBUG) + ldr r0,=PXA2X0_FFTHR /* send char C */ + ldr r1,=0x43 + str r1,[r0] +#endif + + // Set up a stack [for calling C code] + ldr r1,=__startup_stack + ldr r2,=PXA2X0_RAM_BANK0_BASE + orr sp,r1,r2 + + // Create MMU tables + bl hal_mmu_init + +#if defined(XSDEBUG) + ldr r0,=PXA2X0_FFTHR /* send char D */ + ldr r1,=0x44 + str r1,[r0] +#endif + + // Enable MMU + ldr r2,=10f + ldr r1,=MMU_Control_Init|MMU_Control_M + mcr MMU_CP,0,r1,MMU_Control,c0 + mov pc, r2 + nop + nop + nop + +10: +#if defined(XSDEBUG) + ldr r0,=PXA2X0_FFTHR /* send char E */ + ldr r1,=0x45 + str r1,[r0] +#endif + + .endm + +#else // defined(CYG_HAL_STARTUP_ROM) +#define PLATFORM_SETUP1 +#endif + +#define PLATFORM_VECTORS _platform_vectors + .macro _platform_vectors + .globl hal_pcsr_cfg_retry + hal_pcsr_cfg_retry: .long 0 // Boot-time value of PCSR Retry bit. + .endm + +/*---------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_ram.h @@ -0,0 +1,18 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x0) +#define CYGMEM_REGION_ram_SIZE (0x4000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x3F00000 - (size_t) CYG_LABEL_NAME (__heap1)) +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_ram.ldi @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 05:56:24 2000 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x0, LENGTH = 0x4000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_rom_vectors (ram, 0x40000, LMA_EQ_VMA) + SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_ram.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 4000000 0 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section rom_vectors 0 1 0 1 1 1 1 1 40000 40000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 data data ! +section data 0 4 0 1 0 1 0 1 bss bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_rom.h @@ -0,0 +1,20 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#ifndef __ASSEMBLER__ +#include <cyg/infra/cyg_type.h> +#include <stddef.h> + +#endif +#define CYGMEM_REGION_ram (0x00000000) +#define CYGMEM_REGION_ram_SIZE (0x04000000) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +#define CYGMEM_REGION_rom (0x50000000) +#define CYGMEM_REGION_rom_SIZE (0x01000000) +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (0x4000000 - (size_t) CYG_LABEL_NAME (__heap1))
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_rom.ldi @@ -0,0 +1,29 @@ +// eCos memory layout - Tue Jul 02 10:03:04 2002 + +// This is a generated file - do not edit + +#include <cyg/infra/cyg_type.inc> + +MEMORY +{ + ram : ORIGIN = 0x00000000, LENGTH = 0x04000000 + rom : ORIGIN = 0x50000000, LENGTH = 0x01000000 +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, 0x50000000, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_mmu_tables (rom, ALIGN (0x4000), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA) + SECTION_data (ram, 0x8000, FOLLOWING (.mmu_tables)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +}
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/pkgconf/mlt_arm_xscale_xsengine_rom.mlt @@ -0,0 +1,15 @@ +version 0 +region ram 0 2000000 0 ! +region rom 50000000 40000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 50000000 50000000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 1 0 1 mmu_tables mmu_tables ! +section mmu_tables 0 4000 0 1 0 0 0 1 data !
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/plf_io.h @@ -0,0 +1,55 @@ +#ifndef CYGONCE_PLF_IO_H +#define CYGONCE_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific IO support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2005 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Kurt Stremerch +// Contributors: +// Date: 2005-02-23 +// Purpose: XSEngine IO support macros +// Description: +// Usage: #include <cyg/hal/plf_io.h> +// +//####DESCRIPTIONEND#### +// +//============================================================================= + +#endif // CYGONCE_PLF_IO_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/include/xsengine.h @@ -0,0 +1,62 @@ +#ifndef CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H +#define CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H + +//============================================================================= +// +// xsengine.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2005 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include <pkgconf/system.h> +#include CYGHWR_MEMORY_LAYOUT_H +#include <pkgconf/hal_arm_xscale_xsengine.h> +#include <cyg/hal/hal_pxa2x0.h> // Applications Processor defines + +#define SDRAM_PHYS_BASE 0xa0000000 +#define SDRAM_BASE 0x00000000 +#define SDRAM_SIZE 0x04000000 // 64 MB +#define SDRAM_MAX 0x10000000 + +#define XSENGINE_FLASH_ADDR 0x50000000 + +// These must match setup in the page table in hal_platform_extras.h +#define SDRAM_UNCACHED_BASE 0xc0000000 +#undef DCACHE_FLUSH_AREA +#define DCACHE_FLUSH_AREA 0xe0000000 +// ------------------------------------------------------------------------ + +#endif // CYGONCE_HAL_ARM_XSCALE_XSENGINE_XSENGINE_H
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/misc/redboot_RAM.ecm @@ -0,0 +1,125 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware XSEngine ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_PXA2X0 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_XSENGINE current ; + package -hardware CYGPKG_DEVS_FLASH_XSENGINE current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -hardware CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value RAM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0xA0008000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL064M { + inferred_value 1 +}; +
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/misc/redboot_ROM.ecm @@ -0,0 +1,123 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "" ; + hardware XSEngine ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_CORE current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_PXA2X0 current ; + package -hardware CYGPKG_HAL_ARM_XSCALE_XSENGINE current ; + package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ; + package -hardware CYGPKG_DEVS_FLASH_XSENGINE current ; + package -hardware CYGPKG_DEVS_ETH_SMSC_LAN91CXX current ; + package -hardware CYGPKG_DEVS_ETH_ARM_XSCALE_XSENGINE current ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package CYGPKG_IO_FLASH current ; + package CYGPKG_IO_ETH_DRIVERS current ; + package CYGPKG_COMPRESS_ZLIB current ; +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROM +}; + +cdl_option CYGBLD_BUILD_GDB_STUBS { + user_value 0 +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { + inferred_value 0 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + inferred_value 0 0 +}; + +cdl_option CYGPKG_HAL_GDB_FILEIO { + user_value 1 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x40000 +}; + +cdl_component CYGSEM_REDBOOT_FLASH_CONFIG { + user_value 1 +}; + +cdl_option CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG { + user_value 1 +}; + +cdl_component CYGSEM_REDBOOT_BSP_SYSCALLS { + inferred_value 1 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0xA0008000 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 <cyg/libc/string/bsdstring.h> +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 <cyg/libc/string/string.h> +}; + +cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL064M { + inferred_value 1 +};
new file mode 100644 --- /dev/null +++ b/packages/hal/arm/xscale/xsengine/current/src/xsengine_misc.c @@ -0,0 +1,119 @@ +//============================================================================= +// +// xsengine_misc.c +// +// Miscellaneous platform support for xsengine +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2005 eCosCentric Ltd. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Knud Woehler <knud.woehler@microplex.de> +// Date: 2003-01-06 +// +//####DESCRIPTIONEND#### + +#include <pkgconf/hal.h> +#include <pkgconf/system.h> +#include CYGBLD_HAL_PLATFORM_H + +#include <cyg/infra/cyg_type.h> // base types +#include <cyg/infra/cyg_trac.h> // tracing macros +#include <cyg/infra/cyg_ass.h> // assertion macros +#include <cyg/hal/hal_io.h> // IO macros +#include <cyg/hal/hal_arch.h> // Register state info +#include <cyg/hal/hal_diag.h> +#include <cyg/hal/hal_intr.h> // Interrupt names +#include <cyg/hal/hal_cache.h> +#include <cyg/hal/hal_pxa2x0.h> +#include <cyg/hal/xsengine.h> // Platform specifics +#include <cyg/infra/diag.h> // diag_printf +#include <cyg/hal/hal_mm.h> + +#include <string.h> // memset + +void +hal_mmu_init(void) +{ + // Set up the translation tables at offset 0x4000 + unsigned long ttb_base = PXA2X0_RAM_BANK0_BASE + 0x4000; + unsigned long i; + + // Set the TTB register + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + // Set the Domain Access Control Register + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + // First clear all TT entries - ie Set them to Faulting + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ +#define _CACHED ARM_CACHEABLE +#define _UNCACHED ARM_UNCACHEABLE +#define _BUF ARM_BUFFERABLE +#define _NOBUF ARM_UNBUFFERABLE +#define _RWRW ARM_ACCESS_PERM_RW_RW + X_ARM_MMU_SECTION(0x000, 0x500, 32, _UNCACHED, _NOBUF, _RWRW); /* Boot flash ROMspace */ + X_ARM_MMU_SECTION(0x040, 0x600, 32, _UNCACHED, _NOBUF, _RWRW); /* LAN chip */ + X_ARM_MMU_SECTION(0x0C0, 0x700, 32, _UNCACHED, _NOBUF, _RWRW); /* FPGA chip */ + X_ARM_MMU_SECTION(0xA00, 0x000, 64, _CACHED, _BUF, _RWRW); /* SDRAM Bank 0 */ + X_ARM_MMU_SECTION(0xA00, 0xC00, 64, _UNCACHED, _BUF, _RWRW); /* SDRAM Bank 0 */ + X_ARM_MMU_SECTION(0xE00, 0xE00, 128, _CACHED, _BUF, _RWRW); /* Zeros (Cache Clean) Bank */ + X_ARM_MMU_SECTION(0x400, 0x400, 64, _UNCACHED, _NOBUF, _RWRW); /* Peripheral Registers */ + X_ARM_MMU_SECTION(0x440, 0x440, 64, _UNCACHED, _NOBUF, _RWRW); /* LCD Registers */ + X_ARM_MMU_SECTION(0x480, 0x480, 64, _UNCACHED, _NOBUF, _RWRW); /* Memory Ctl Registers */ +} + +// +// Platform specific initialization +// + +void +plf_hardware_init(void) +{ + // RAM startup only - rewrite relevent bits depending on config +#ifndef CYG_HAL_STARTUP_ROM + HAL_DCACHE_SYNC(); // Force data out + HAL_DCACHE_INVALIDATE_ALL(); // Flush TLBs: make new mmu state effective +#endif // ! CYG_HAL_STARTUP_ROM - RAM start only + + hal_if_init(); +} + +// ------------------------------------------------------------------------ +// EOF xsengine_misc.c