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annotate packages/hal/v85x/arch/current/src/vectors.S @ 112:02ea4320376c ecos-sw-2000-07-21

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Merge from eCos master repository on 2000-07-21-21:01:39-BST
author jlarmour
date Fri, 21 Jul 2000 21:34:11 +0000
parents 5a0cc6c243a9
children 77cec8369160
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1 // #========================================================================
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2 // #
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3 // # vectors.S
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4 // #
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5 // # NEC/V85x exception/interrupt vectors
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6 // #
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7 // #========================================================================
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8 // ####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 // ####COPYRIGHTEND####
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31 // #========================================================================
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32 // ######DESCRIPTIONBEGIN####
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33 // #
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34 // # Author(s): gthomas
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35 // # Contributors: gthomas
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36 // # Date: 2000-03-10
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37 // # Purpose: NEC/V85x exception vectors
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38 // # Description: This file defines the code placed into the exception
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39 // # vectors. It also contains the first level default VSRs
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40 // # that save and restore state for both exceptions and
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41 // # interrupts.
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42 // #
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43 // #####DESCRIPTIONEND####
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44 // #
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45 // #========================================================================
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46
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47 #include <pkgconf/hal.h>
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48 #include <pkgconf/hal_v85x.h>
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49 #ifdef CYGPKG_KERNEL // no CDL yet
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50 #include <pkgconf/kernel.h>
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51 #else
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52 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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53 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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54 #endif
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55 #include <cyg/hal/hal_platform_setup.h>
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56
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57 #include <cyg/hal/nec_offsets.inc>
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58
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59 // Two different macros in case we ever decide to differentiate
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60 // between exceptions and interrupts.
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61 .macro EXCEPTION
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62 .org reset_vector+(0x0010*VECTOR)
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63 addi -CYGARC_EXCEPTION_FRAME_SIZE,sp,sp
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64 st.w r1,CYGARC_REG_R1[sp]
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65 movea VECTOR,r0,r1
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66 .set VECTOR, VECTOR+1
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67 jr exception
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68 .endm
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69
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70 .macro INTERRUPT
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71 .org reset_vector+(0x0010*VECTOR)
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72 addi -CYGARC_EXCEPTION_FRAME_SIZE,sp,sp
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73 st.w r1,CYGARC_REG_R1[sp]
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74 movea VECTOR,r0,r1
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75 jr exception
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76 .set VECTOR, VECTOR+1
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77 .endm
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78
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79 .text
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80 .globl reset_vector
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81 reset_vector:
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82
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83 #ifdef CYG_HAL_STARTUP_ROM
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84 //
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85 // These are the hardware exception vectors.
105
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86 //
96
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87 __ROM_vsr:
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88 // 0x000
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89 jr start
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90
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91 .set VECTOR, 1
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92 .rept CYGNUM_HAL_EXCEPTION_COUNT-1
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93 EXCEPTION
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94 .endr
105
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95 .set VECTOR, 8
96
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96 .rept CYGNUM_HAL_ISR_COUNT
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97 INTERRUPT
105
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98 .endr
96
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99 #endif // CYG_HAL_STARTUP_ROM
105
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100
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101 .globl start
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102 start:
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103 // Perform hardware initialization
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104 PLATFORM_SETUP1
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105
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106 #ifdef CYG_HAL_STARTUP_ROM
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107 // Relocate [copy] data from ROM to RAM
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108 lea ___rom_data_start,r6
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109 lea ___ram_data_start,r7
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110 lea ___ram_data_end,r8
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111 1: ld.w 0[r6],r1
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112 st.w r1,0[r7]
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113 addi 4,r6,r6
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114 addi 4,r7,r7
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115 cmp r7,r8
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116 bne 1b
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117 #endif
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118 // Initialize stack
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119 lea __startup_stack,r1
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120 mov r1,sp
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121
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122 // Clear BSS
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123 lea ___bss_start,r6
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124 lea ___bss_end,r7
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125 1: st.w r0,0[r6]
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126 addi 4,r6,r6
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127 cmp r6,r7
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128 bne 1b
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129
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130 #ifdef CYG_HAL_STARTUP_ROM
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131 // Built initial trap VSR tables
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132 lea __vsr_table,r6
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133 lea __vsr_table_end,r9
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134 #if 0
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135 lea __ROM_vsr,r7
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136 mov r6,r8
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137 sub r7,r8
105
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138 lea 0x003FFFFF,r7
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139 and r7,r8
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140 lea 0x07800000,r7
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141 or r7,r8
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142 #else
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143 lea 0x00000794,r8 // jr 0x0100xx0
105
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144 #endif
96
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145 10: st.w r8,0[r6]
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146 addi 16,r6,r6
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147 cmp r6,r9
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148 bne 10b
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149 #else
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150 // Set up VSR pointers into this application/image
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151 lea _hal_vsr_table+(CYGNUM_HAL_EXCEPTION_COUNT*4),r6
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152 movea CYGNUM_HAL_ISR_COUNT,r0,r7
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153 lea do_interrupt,r8
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154 10: st.w r8,0[r6]
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155 addi 4,r6,r6
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156 addi -1,r7,r7
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157 bne 10b
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158 #endif
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159
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160 // Initialize hardware
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161 jarl _cyg_hal_hardware_init,r31
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162
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163 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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164 #ifndef CYG_HAL_STARTUP_ROM
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165 // Need to handle exceptions as well
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166 lea _hal_vsr_table,r6
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167 movea CYGNUM_HAL_EXCEPTION_COUNT,r0,r7
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168 lea do_exception,r8
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169 10: st.w r8,0[r6]
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170 addi 4,r6,r6
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171 addi -1,r7,r7
105
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172 bne 10b
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173 #endif
96
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174 jarl _initialize_stub,r31
101
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175 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // this _check_ should go away
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176 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
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177 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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178 .extern hal_ctrlc_isr_init
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179 jarl _hal_ctrlc_isr_init,r31
96
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180 #endif
101
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181 #endif
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182 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
96
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183
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184 // Run through static constructors
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185 jarl _cyg_hal_invoke_constructors,r31
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186
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187 // Ready to start the eCos kernel
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188 jarl _cyg_start,r31
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189
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190 // If we get here, something is _very_ wrong
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191 _start_hang:
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192 br _start_hang
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193
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194 #ifdef CYG_HAL_STARTUP_ROM
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195 // Handle exception
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196 exception:
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197 // save exception context
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198 st.w ep,CYGARC_REG_EP[sp]
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199 mov sp,ep
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200 st.w r1,CYGARC_REG_VECTOR[ep]
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201 addi CYGARC_EXCEPTION_FRAME_SIZE,ep,r1
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202 sst.w r2,CYGARC_REG_R2[ep]
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203 sst.w r1,CYGARC_REG_SP[ep]
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204 sst.w r4,CYGARC_REG_R4[ep]
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205 sst.w r5,CYGARC_REG_R5[ep]
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206 sst.w r6,CYGARC_REG_R6[ep]
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207 sst.w r7,CYGARC_REG_R7[ep]
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208 sst.w r8,CYGARC_REG_R8[ep]
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209 sst.w r9,CYGARC_REG_R9[ep]
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210 sst.w r10,CYGARC_REG_R10[ep]
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211 sst.w r11,CYGARC_REG_R11[ep]
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212 sst.w r12,CYGARC_REG_R12[ep]
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213 sst.w r13,CYGARC_REG_R13[ep]
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214 sst.w r14,CYGARC_REG_R14[ep]
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215 sst.w r15,CYGARC_REG_R15[ep]
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216 sst.w r16,CYGARC_REG_R16[ep]
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217 sst.w r17,CYGARC_REG_R17[ep]
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218 sst.w r18,CYGARC_REG_R18[ep]
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219 sst.w r19,CYGARC_REG_R19[ep]
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220 sst.w r20,CYGARC_REG_R20[ep]
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221 sst.w r21,CYGARC_REG_R21[ep]
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222 sst.w r22,CYGARC_REG_R22[ep]
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223 sst.w r23,CYGARC_REG_R23[ep]
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224 sst.w r24,CYGARC_REG_R24[ep]
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225 sst.w r25,CYGARC_REG_R25[ep]
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226 sst.w r26,CYGARC_REG_R26[ep]
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227 sst.w r27,CYGARC_REG_R27[ep]
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228 sst.w r28,CYGARC_REG_R28[ep]
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229 sst.w r29,CYGARC_REG_R29[ep]
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230 ld.w CYGARC_REG_VECTOR[ep],r8
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231 sst.w lp,CYGARC_REG_LP[ep]
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232 cmp CYGNUM_HAL_VECTOR_TRAP0,r8 // NMI?
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233 bge 05f
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234 stsr FEPC,r6 // saved state differs
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235 stsr FEPSW,r7
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236 br 20f
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237 05: stsr EIPC,r6
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238 cmp CYGNUM_HAL_VECTOR_ILLEGAL_OPCODE,r8 // Illegal opcode?
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239 bne 10f
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240 addi -4,r6,r6 // yes, adjust PC
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241 10: stsr EIPSW,r7
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242 20: st.w r6,CYGARC_REG_PC[ep]
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243 st.w r7,CYGARC_REG_PSW[ep]
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244 stsr ECR,r6
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245 st.w r6,CYGARC_REG_CAUSE[ep]
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246 // Reenable exception processing
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247 stsr PSW,r6
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248 andi ~(CYGARC_PSW_EP|CYGARC_PSW_NP),r6,r6
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249 ldsr r6,PSW
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250 shl 2,r8
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251 lea _hal_vsr_table,r1
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252 add r1,r8
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253 ld.w 0[r8],r1
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254 jmp [r1]
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255 #endif
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256
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257 do_exception:
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258 mov sp,r6
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259 jarl _exception_handler,r31
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260
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261 return_from_exception_or_interrupt:
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262 mov sp,ep
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263 ld.w CYGARC_REG_PSW[ep],r7
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264 sld.w CYGARC_REG_R1[ep],r1
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265 ld.w CYGARC_REG_PC[ep],r6
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266 sld.w CYGARC_REG_R2[ep],r2
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267 // disable interrupts while restoring context
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268 ld.w CYGARC_REG_VECTOR[ep],r4
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269 stsr PSW,r8
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270 cmp CYGNUM_HAL_VECTOR_TRAP0,r4
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271 bge 10f
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272 ori CYGARC_PSW_NP,r8,r8 // returning from NMI
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273 ori CYGARC_PSW_ID,r8,r8 // disable interrupt
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274 ldsr r8,PSW
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275 ldsr r7,FEPSW
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276 ldsr r6,FEPC
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277 br 30f
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278 10: cmp CYGNUM_HAL_ISR_MIN,r4 // exception or interrupt
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279 bge 20f
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280 ori CYGARC_PSW_EP,r8,r8 // returning from exception
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281 20: ori CYGARC_PSW_ID,r8,r8 // disable interrupt
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282 ldsr r8,PSW
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283 ldsr r7,EIPSW // Avoid pipline bubbles
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284 ldsr r6,EIPC
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285 30: sld.w CYGARC_REG_R4[ep],r4
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286 sld.w CYGARC_REG_R5[ep],r5
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287 sld.w CYGARC_REG_R6[ep],r6
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288 sld.w CYGARC_REG_R7[ep],r7
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289 sld.w CYGARC_REG_R8[ep],r8
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290 sld.w CYGARC_REG_R9[ep],r9
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291 sld.w CYGARC_REG_R10[ep],r10
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292 sld.w CYGARC_REG_R11[ep],r11
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293 sld.w CYGARC_REG_R12[ep],r12
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294 sld.w CYGARC_REG_R13[ep],r13
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295 sld.w CYGARC_REG_R14[ep],r14
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296 sld.w CYGARC_REG_R15[ep],r15
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297 sld.w CYGARC_REG_R16[ep],r16
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298 sld.w CYGARC_REG_R17[ep],r17
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299 sld.w CYGARC_REG_R18[ep],r18
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300 sld.w CYGARC_REG_R19[ep],r19
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301 sld.w CYGARC_REG_R20[ep],r20
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302 sld.w CYGARC_REG_R21[ep],r21
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303 sld.w CYGARC_REG_R22[ep],r22
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304 sld.w CYGARC_REG_R23[ep],r23
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305 sld.w CYGARC_REG_R24[ep],r24
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306 sld.w CYGARC_REG_R25[ep],r25
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307 sld.w CYGARC_REG_R26[ep],r26
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308 sld.w CYGARC_REG_R27[ep],r27
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309 sld.w CYGARC_REG_R28[ep],r28
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310 sld.w CYGARC_REG_R29[ep],r29
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311 sld.w CYGARC_REG_LP[ep],lp
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312 sld.w CYGARC_REG_SP[ep],sp
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313 sld.w CYGARC_REG_EP[ep],ep
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314 reti
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315
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316 // Handle interrupt - these are typically vectored into user code
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317 do_interrupt:
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318 mov sp,ep // save pointer to regs frame
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319
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320 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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321 // Switch to interrupt stack
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322 lea irq_level,r6 // current number of nested interrupts
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323 ld.w 0[r6],r7
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324 addi 1,r7,r8
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325 st.w r8,0[r6]
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326 cmp 0,r7 // if was zero, switch stacks
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327 bne 10f
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328 mov sp,r1 // save old stack pointer
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329 lea __interrupt_stack-4,r2
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330 mov r2,sp
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331 st.w r1,0[sp]
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332 10:
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333 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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334
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335 // The entire CPU state is now stashed on the stack,
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336 // increment the scheduler lock and handle the interrupt
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337
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338 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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339 .extern cyg_scheduler_sched_lock
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340 lea cyg_scheduler_sched_lock,r7
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341 ld.w 0[r7],r8
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342 addi 1,r8,r8
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343 st.w r8,0[r7]
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344 #endif
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345
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346 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
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347 defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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348 lea RAISE_INTR,r6 // arg0 = type = INTR,RAISE
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349 ld.w CYGARC_REG_VECTOR[ep],r7 // args = vector
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350 mov r0,r8 // arg2 = 0
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351 jarl _cyg_instrument,r31
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352 #endif
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353
101
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354 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // this _check_ should go away
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355 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
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356 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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357 // If we are supporting Ctrl-C interrupts from GDB, we must squirrel
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358 // away a pointer to the save interrupt state here so that we can
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359 // plant a breakpoint at some later time.
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360
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361 .extern _hal_saved_interrupt_state
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362 lea _hal_saved_interrupt_state,r8
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363 st.w ep,0[r8]
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364 #endif
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365 #endif
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366
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367 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
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368 mov r0,r8 // vector # (overloaded by kernel)
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369 #else
96
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370 ld.w CYGARC_REG_VECTOR[ep],r6 // vector #
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371 addi -CYGNUM_HAL_ISR_MIN,r6,r8
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372 shl 2,r8
101
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373 #endif
96
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374 lea _hal_interrupt_objects,r1
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375 add r8,r1
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376 ld.w 0[r1],r29 // save object handle
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377 lea _hal_interrupt_data,r1
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378 add r8,r1
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379 ld.w 0[r1],r7 // handler data
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380 lea _hal_interrupt_handlers,r1
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381 add r8,r1
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382 mov ep,r8 // pointer to saved registers
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383 ld.w 0[r1],r1 // handler routine
101
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384 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
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385 ld.w CYGARC_REG_VECTOR[ep],r6 // vector #
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386 #endif
96
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387 jarl call_via_r1,r31
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388
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389 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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390 // If we are returning from the last nested interrupt, move back
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391 // to the thread stack. interrupt_end() must be called on the
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392 // thread stack since it potentially causes a context switch.
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393 lea irq_level,r6
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394 ld.w 0[r6],r7
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395 addi -1,r7,r8
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396 st.w r8,0[r6]
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397 cmp 0,r8
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398 bne 10f
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399 ld.w 0[sp],sp // Restore non-interrupt stack at last interrupt
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400 10:
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401 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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402
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403 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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404 // The return value from the handler (in r10) will indicate whether a
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405 // DSR is to be posted. Pass this together with a pointer to the
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406 // interrupt object we have just used to the interrupt tidy up routine.
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407
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408 mov r10,r6 // interrupt handler return code
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409 mov r29,r7 // object handle
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410 mov ep,r8 // register frame
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411 jarl _interrupt_end,r31 // post any bottom layer handle
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412
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413 #endif
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414 br return_from_exception_or_interrupt
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415
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416 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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417 .globl _hal_interrupt_stack_call_pending_DSRs
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418 _hal_interrupt_stack_call_pending_DSRs:
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419 stsr PSW,r9
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420 di // disable interrupts while changing stack
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421 // Switch to interrupt stack
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422 lea irq_level,r6 // current number of nested interrupts
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423 mov 1,r7 // note: this can never be non-zero at this point
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424 st.w r7,0[r6]
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425 mov sp,r1 // save old stack pointer
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426 lea __interrupt_stack-(4*4),r8
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427 mov r8,sp
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428 st.w r1,0[sp]
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429 st.w r9,4[sp]
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430 st.w lp,8[sp]
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431 ei
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432 jarl _cyg_interrupt_call_pending_DSRs,lp
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433 di
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434 ld.w 8[sp],lp // restore state
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435 ld.w 4[sp],r6
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436 ld.w 0[sp],sp
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437 lea irq_level,r7
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438 st.w r0,0[r7]
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439 ldsr r6,PSW
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440 jmp [lp]
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441 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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442
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443 //
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444 // Indirect subroutine call, via R1
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445
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446 call_via_r1:
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447 jmp [r1]
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448
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449 //
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450 // Reset the board
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451 //
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452 .globl _hal_plf_reset_board
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453 _hal_plf_reset_board:
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454 di // Turn off interrupts
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455 jmp [r0] // Restart machine
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456
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457 #if !defined(CYGSEM_HAL_NEC_INLINE_INTERRUPT_FUNCTIONS)
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458 .globl _hal_disable_interrupts
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459 _hal_disable_interrupts:
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460 stsr PSW,r10
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461 di
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462 jmp [lp]
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463
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464 .globl _hal_enable_interrupts
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465 _hal_enable_interrupts:
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466 stsr PSW,r6
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467 ei
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468 jmp [lp]
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469
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470 .globl _hal_restore_interrupts
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471 _hal_restore_interrupts:
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472 ldsr r6,PSW
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473 jmp [lp]
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474 #endif
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475
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476 // -------------------------------------------------------------------------
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477 .data
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478 #ifdef CYG_HAL_STARTUP_ROM
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479 // Trap jump table - used by builtin ROM
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480 __vsr_table:
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481 .rept CYGNUM_HAL_VSR_COUNT
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482 .word 0,0,0,0
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483 .endr
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484 __vsr_table_end:
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485
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486 _hal_vsr_table:
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487 .rept CYGNUM_HAL_EXCEPTION_COUNT
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488 .word do_exception
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489 .endr
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490 .rept CYGNUM_HAL_ISR_COUNT
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491 .word do_interrupt
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492 .endr
101
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493
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494 #if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
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495 .balign 64
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496 _hal_virtual_vector_table:
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497 .rept CYGNUM_CALL_IF_TABLE_SIZE
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498 .word 0
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499 .endr
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500 #endif
96
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501 #endif
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502
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503 // Initial stack
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504 .rept 1024
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505 .byte 0
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506 .endr
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507 __startup_stack:
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508
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509 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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510 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
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511 #endif
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512 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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513 .balign 16
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514 .global _cyg_interrupt_stack_base
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515 _cyg_interrupt_stack_base:
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516 __interrupt_stack_base:
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517 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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518 .byte 0
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519 .endr
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520 .balign 16
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521 .global _cyg_interrupt_stack
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522 _cyg_interrupt_stack:
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523 __interrupt_stack:
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524 irq_level:
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525 .long 0
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526 #endif // CYG_HAL_STARTUP == ROM
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527
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528 // Interrupt vector tables.
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529 // These tables contain the isr, data and object pointers used to deliver
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530 // interrupts to user code.
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531
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532 .extern _hal_default_isr
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533
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534 .globl _hal_interrupt_handlers
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535 _hal_interrupt_handlers:
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536 .rept CYGNUM_HAL_ISR_COUNT
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537 .long _hal_default_isr
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538 .endr
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539
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540 .globl _hal_interrupt_data
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541 _hal_interrupt_data:
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542 .rept CYGNUM_HAL_ISR_COUNT
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543 .long 0
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544 .endr
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545
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546 .globl _hal_interrupt_objects
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547 _hal_interrupt_objects:
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548 .rept CYGNUM_HAL_ISR_COUNT
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549 .long 0
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550 .endr