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annotate packages/devs/serial/sh/sci/current/src/sh_sci_serial.c @ 128:0c2b7be0d798 ecos-sw-2000-10-12

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Merge from eCos master repository on 2000-10-12-08:46:24-BST
author jlarmour
date Thu, 12 Oct 2000 20:31:43 +0000
parents 0ec04793409a
children e2d866e32dac
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1 //==========================================================================
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2 //
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3 // io/serial/sh/sh_sci_serial.c
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4 //
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5 // SH Serial SCI I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:gthomas, jskov
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36 // Date: 1999-05-24
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37 // Purpose: SH Serial I/O module (interrupt driven version)
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38 // Description:
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39 //
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40 // Note: Since interrupt sources from the same SCI channel share the same
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41 // interrupt level, there is no risk of races when altering the
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42 // channel's control register from ISRs and DSRs. However, when
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43 // altering the control register from user-level code, interrupts
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44 // must be disabled while the register is being accessed.
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45 //
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46 // FIXME: Receiving in polled mode prevents duplex transfers from working for
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47 // some reason.
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48 //####DESCRIPTIONEND####
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49 //==========================================================================
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50
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51 #include <pkgconf/io_serial.h>
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52 #include <pkgconf/io.h>
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53
128
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54 // FIXME: This is necessary since the SCIF driver may be overriding
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55 // CYGDAT_IO_SERIAL_DEVICE_HEADER. Need a better way to include two
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56 // different drivers.
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57 #include <pkgconf/io_serial_sh_sci.h>
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58
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59 #include <cyg/io/io.h>
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60 #include <cyg/hal/hal_intr.h>
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61 #include <cyg/io/devtab.h>
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62 #include <cyg/infra/diag.h>
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63 #include <cyg/io/serial.h>
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64
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65 #include <cyg/hal/sh_regs.h>
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66
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67 // Only compile driver if an inline file with driver details was selected.
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68 #ifdef CYGDAT_IO_SERIAL_SH_SCI_INL
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69
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70 // Controller base (only one supported at the moment)
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71 #define SH_SERIAL_SCI_BASE 0xfffffe80
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72
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73 // The SCI controller register layout on the SH3/7708.
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74 #define SCI_SCSMR 0 // serial mode register
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75 #define SCI_SCBRR 2 // bit rate register
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76 #define SCI_SCSCR 4 // serial control register
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77 #define SCI_SCTDR 6 // transmit data register
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78 #define SCI_SCSSR 8 // serial status register
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79 #define SCI_SCRDR 10 // receive data register
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80 #define SCI_SCSPTR -4 // serial port register
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81
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82 static short select_word_length[] = {
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83 -1,
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84 -1,
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85 CYGARC_REG_SCSMR_CHR, // 7 bits
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86 0 // 8 bits
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87 };
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88
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89 static short select_stop_bits[] = {
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90 -1,
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91 0, // 1 stop bit
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92 -1,
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93 CYGARC_REG_SCSMR_STOP // 2 stop bits
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94 };
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95
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96 static short select_parity[] = {
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97 0, // No parity
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98 CYGARC_REG_SCSMR_PE, // Even parity
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99 CYGARC_REG_SCSMR_PE|CYGARC_REG_SCSMR_OE, // Odd parity
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100 -1,
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101 -1
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102 };
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103
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104 static unsigned short select_baud[] = {
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105 0, // Unused
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106 CYGARC_SCBRR_CKSx(50)<<8 | CYGARC_SCBRR_N(50),
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107 CYGARC_SCBRR_CKSx(75)<<8 | CYGARC_SCBRR_N(75),
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108 CYGARC_SCBRR_CKSx(110)<<8 | CYGARC_SCBRR_N(110),
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109 CYGARC_SCBRR_CKSx(134)<<8 | CYGARC_SCBRR_N(134),
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110 CYGARC_SCBRR_CKSx(150)<<8 | CYGARC_SCBRR_N(150),
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111 CYGARC_SCBRR_CKSx(200)<<8 | CYGARC_SCBRR_N(200),
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112 CYGARC_SCBRR_CKSx(300)<<8 | CYGARC_SCBRR_N(300),
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113 CYGARC_SCBRR_CKSx(600)<<8 | CYGARC_SCBRR_N(600),
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114 CYGARC_SCBRR_CKSx(1200)<<8 | CYGARC_SCBRR_N(1200),
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115 CYGARC_SCBRR_CKSx(1800)<<8 | CYGARC_SCBRR_N(1800),
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116 CYGARC_SCBRR_CKSx(2400)<<8 | CYGARC_SCBRR_N(2400),
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117 CYGARC_SCBRR_CKSx(3600)<<8 | CYGARC_SCBRR_N(3600),
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118 CYGARC_SCBRR_CKSx(4800)<<8 | CYGARC_SCBRR_N(4800),
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119 CYGARC_SCBRR_CKSx(7200)<<8 | CYGARC_SCBRR_N(7200),
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120 CYGARC_SCBRR_CKSx(9600)<<8 | CYGARC_SCBRR_N(9600),
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121 CYGARC_SCBRR_CKSx(14400)<<8 | CYGARC_SCBRR_N(14400),
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122 CYGARC_SCBRR_CKSx(19200)<<8 | CYGARC_SCBRR_N(19200),
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123 CYGARC_SCBRR_CKSx(38400)<<8 | CYGARC_SCBRR_N(38400),
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124 CYGARC_SCBRR_CKSx(57600)<<8 | CYGARC_SCBRR_N(57600),
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125 CYGARC_SCBRR_CKSx(115200)<<8 | CYGARC_SCBRR_N(115200),
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126 CYGARC_SCBRR_CKSx(230400)<<8 | CYGARC_SCBRR_N(230400)
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127 };
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128
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129
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130 typedef struct sh_sci_info {
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131 CYG_ADDRWORD data; // Pointer to data register
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132
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133 CYG_WORD er_int_num, // Error interrupt number
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134 rx_int_num, // Receive interrupt number
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135 tx_int_num; // Transmit interrupt number
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136
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137 CYG_ADDRWORD ctrl_base; // Base address of SCI controller
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138
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139 cyg_interrupt serial_er_interrupt,
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140 serial_rx_interrupt,
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141 serial_tx_interrupt;
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142 cyg_handle_t serial_er_interrupt_handle,
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143 serial_rx_interrupt_handle,
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144 serial_tx_interrupt_handle;
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145
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146 bool tx_enabled;
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147 } sh_sci_info;
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148
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149 static bool sh_serial_init(struct cyg_devtab_entry *tab);
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150 static bool sh_serial_putc(serial_channel *chan, unsigned char c);
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151 static Cyg_ErrNo sh_serial_lookup(struct cyg_devtab_entry **tab,
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152 struct cyg_devtab_entry *sub_tab,
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153 const char *name);
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154 static unsigned char sh_serial_getc(serial_channel *chan);
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155 static Cyg_ErrNo sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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156 const void *xbuf, cyg_uint32 *len);
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157 static void sh_serial_start_xmit(serial_channel *chan);
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158 static void sh_serial_stop_xmit(serial_channel *chan);
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159
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160 static cyg_uint32 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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161 static void sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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162 cyg_addrword_t data);
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163 static cyg_uint32 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data);
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164 static void sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count,
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165 cyg_addrword_t data);
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166 static cyg_uint32 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data);
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167 static void sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count,
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168 cyg_addrword_t data);
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169
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170 static SERIAL_FUNS(sh_serial_funs,
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171 sh_serial_putc,
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172 sh_serial_getc,
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173 sh_serial_set_config,
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174 sh_serial_start_xmit,
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175 sh_serial_stop_xmit
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176 );
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177
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178 #include CYGDAT_IO_SERIAL_SH_SCI_INL
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179
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180 // Internal function to actually configure the hardware to desired baud rate,
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181 // etc.
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182 static bool
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183 sh_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config,
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184 bool init)
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185 {
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186 cyg_uint16 baud_divisor = select_baud[new_config->baud];
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187 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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188 cyg_uint8 _scr, _smr;
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189
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190 // Check configuration request
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191 if ((-1 == select_word_length[(new_config->word_length -
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192 CYGNUM_SERIAL_WORD_LENGTH_5)])
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193 || -1 == select_stop_bits[new_config->stop]
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194 || -1 == select_parity[new_config->parity]
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195 || baud_divisor == 0)
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196 return false;
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197
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198 // Disable SCI interrupts while changing hardware
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199 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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200 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, 0);
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201
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202 // Set databits, stopbits and parity.
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203 _smr = select_word_length[(new_config->word_length -
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204 CYGNUM_SERIAL_WORD_LENGTH_5)] |
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205 select_stop_bits[new_config->stop] |
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206 select_parity[new_config->parity];
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207 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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208
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209 // Set baud rate.
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210 _smr &= ~CYGARC_REG_SCSMR_CKSx_MASK;
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211 _smr |= baud_divisor >> 8;
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212 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSMR, _smr);
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213 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCBRR, baud_divisor & 0xff);
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214
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215 // Clear the status register.
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216 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, 0);
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217
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218 if (init) {
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219 // Always enable transmitter and receiver.
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220 _scr = CYGARC_REG_SCSCR_TE | CYGARC_REG_SCSCR_RE;
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221
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222 if (chan->out_cbuf.len != 0)
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223 _scr |= CYGARC_REG_SCSCR_TIE; // enable tx interrupts
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224
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225 if (chan->in_cbuf.len != 0)
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226 _scr |= CYGARC_REG_SCSCR_RIE; // enable rx interrupts
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227 }
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228
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229 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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230
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231 if (new_config != &chan->config) {
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232 chan->config = *new_config;
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233 }
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234 return true;
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235 }
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236
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237 // Function to initialize the device. Called at bootstrap time.
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238 static bool
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239 sh_serial_init(struct cyg_devtab_entry *tab)
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240 {
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241 serial_channel *chan = (serial_channel *)tab->priv;
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242 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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243 #ifdef CYGDBG_IO_INIT
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244 diag_printf("SH SERIAL init - dev: %x.%d\n",
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245 sh_chan->data, sh_chan->rx_int_num);
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246 #endif
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247 // Really only required for interrupt driven devices
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248 (chan->callbacks->serial_init)(chan);
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249
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250 if (chan->out_cbuf.len != 0) {
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251 cyg_drv_interrupt_create(sh_chan->tx_int_num,
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252 3,
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253 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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254 sh_serial_tx_ISR,
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255 sh_serial_tx_DSR,
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256 &sh_chan->serial_tx_interrupt_handle,
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257 &sh_chan->serial_tx_interrupt);
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258 cyg_drv_interrupt_attach(sh_chan->serial_tx_interrupt_handle);
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259 cyg_drv_interrupt_unmask(sh_chan->tx_int_num);
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260 sh_chan->tx_enabled = false;
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261 }
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262 if (chan->in_cbuf.len != 0) {
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263 // Receive interrupt
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264 cyg_drv_interrupt_create(sh_chan->rx_int_num,
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265 3,
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266 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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267 sh_serial_rx_ISR,
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268 sh_serial_rx_DSR,
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269 &sh_chan->serial_rx_interrupt_handle,
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270 &sh_chan->serial_rx_interrupt);
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271 cyg_drv_interrupt_attach(sh_chan->serial_rx_interrupt_handle);
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272 // Receive error interrupt
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273 cyg_drv_interrupt_create(sh_chan->er_int_num,
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274 3,
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275 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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276 sh_serial_er_ISR,
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277 sh_serial_er_DSR,
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278 &sh_chan->serial_er_interrupt_handle,
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279 &sh_chan->serial_er_interrupt);
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280 cyg_drv_interrupt_attach(sh_chan->serial_er_interrupt_handle);
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281 // This unmasks both interrupt sources.
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282 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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283 }
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284 sh_serial_config_port(chan, &chan->config, true);
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285 return true;
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286 }
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287
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288 // This routine is called when the device is "looked" up (i.e. attached)
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289 static Cyg_ErrNo
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290 sh_serial_lookup(struct cyg_devtab_entry **tab,
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291 struct cyg_devtab_entry *sub_tab,
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292 const char *name)
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293 {
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294 serial_channel *chan = (serial_channel *)(*tab)->priv;
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295
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296 // Really only required for interrupt driven devices
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297 (chan->callbacks->serial_init)(chan);
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298 return ENOERR;
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299 }
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300
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301 // Send a character to the device output buffer.
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302 // Return 'true' if character is sent to device
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303 static bool
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304 sh_serial_putc(serial_channel *chan, unsigned char c)
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305 {
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306 cyg_uint8 _ssr;
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307 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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308
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309 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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310 if (_ssr & CYGARC_REG_SCSSR_TDRE) {
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311 // Transmit buffer is empty
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312 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCTDR, c);
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313 // Clear empty flag.
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314 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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315 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_TDRE);
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316 return true;
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317 } else {
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318 // No space
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319 return false;
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320 }
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321 }
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322
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323 // Fetch a character from the device input buffer, waiting if necessary
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324 static unsigned char
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325 sh_serial_getc(serial_channel *chan)
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326 {
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327 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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328 unsigned char c;
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329 cyg_uint8 _ssr;
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330
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331 do {
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332 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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333 } while ((_ssr & CYGARC_REG_SCSSR_RDRF) == 0);
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334
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335 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, c);
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336
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337 // Clear buffer full flag.
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338 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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339 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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340
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341 return c;
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342 }
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343
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344 // Set up the device characteristics; baud rate, etc.
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345 static Cyg_ErrNo
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346 sh_serial_set_config(serial_channel *chan, cyg_uint32 key,
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347 const void *xbuf, cyg_uint32 *len)
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348 {
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349 switch (key) {
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350 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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351 {
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352 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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353 if ( *len < sizeof(cyg_serial_info_t) ) {
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354 return -EINVAL;
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355 }
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356 *len = sizeof(cyg_serial_info_t);
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357 if ( true != sh_serial_config_port(chan, config, false) )
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358 return -EINVAL;
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359 }
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360 break;
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361 default:
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362 return -EINVAL;
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363 }
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364 return ENOERR;
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365 }
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366
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367 // Enable the transmitter on the device
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368 static void
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369 sh_serial_start_xmit(serial_channel *chan)
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370 {
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371 cyg_uint8 _scr;
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372 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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373
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374 sh_chan->tx_enabled = true;
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375
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376 // Mask the interrupts (all sources of the unit) while changing
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377 // the CR since a rx interrupt in the middle of this would result
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378 // in a bad CR state.
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379 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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380
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381 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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382 _scr |= CYGARC_REG_SCSCR_TIE; // Enable xmit interrupt
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383 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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384
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385 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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386 }
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387
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388 // Disable the transmitter on the device
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389 static void
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390 sh_serial_stop_xmit(serial_channel *chan)
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391 {
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392 cyg_uint8 _scr;
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393 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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394
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395 sh_chan->tx_enabled = false;
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396
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397 // Mask the interrupts (all sources of the unit) while changing
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398 // the CR since a rx interrupt in the middle of this would result
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399 // in a bad CR state.
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400 cyg_drv_interrupt_mask(sh_chan->rx_int_num);
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401
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402 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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403 _scr &= ~CYGARC_REG_SCSCR_TIE; // Disable xmit interrupt
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404 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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405
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406 cyg_drv_interrupt_unmask(sh_chan->rx_int_num);
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407 }
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408
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409 // Serial I/O - low level tx interrupt handler (ISR)
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410 static cyg_uint32
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411 sh_serial_tx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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412 {
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413 serial_channel *chan = (serial_channel *)data;
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414 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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415 cyg_uint8 _scr;
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416
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417 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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418 _scr &= ~CYGARC_REG_SCSCR_TIE; // mask out tx interrupts
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419 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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420
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421 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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422 }
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423
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424 // Serial I/O - high level tx interrupt handler (DSR)
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425 static void
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426 sh_serial_tx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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427 {
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428 serial_channel *chan = (serial_channel *)data;
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429 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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430
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431 (chan->callbacks->xmt_char)(chan);
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432
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433 if (sh_chan->tx_enabled) {
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434 cyg_uint8 _scr;
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435
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436 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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437 _scr |= CYGARC_REG_SCSCR_TIE; // unmask tx interrupts
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438 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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439 }
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440 }
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441
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442 // Serial I/O - low level RX interrupt handler (ISR)
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443 static cyg_uint32
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444 sh_serial_rx_ISR(cyg_vector_t vector, cyg_addrword_t data)
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445 {
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446 serial_channel *chan = (serial_channel *)data;
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447 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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448 cyg_uint8 _scr;
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449
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450 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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451 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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452 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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453 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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454 }
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455
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456 // Serial I/O - high level rx interrupt handler (DSR)
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457 static void
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458 sh_serial_rx_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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459 {
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460 serial_channel *chan = (serial_channel *)data;
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461 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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462 cyg_uint8 _ssr, _scr;
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463
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464 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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465 if (_ssr & CYGARC_REG_SCSSR_RDRF) {
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466 cyg_uint8 _c;
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467 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCRDR, _c);
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468 // Clear buffer full flag.
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469 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR,
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470 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
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471
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472 (chan->callbacks->rcv_char)(chan, _c);
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473 }
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474
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475 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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476 _scr |= CYGARC_REG_SCSCR_RIE; // unmask rx interrupts
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477 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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478 }
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479
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480 static volatile int sh_serial_error_orer = 0;
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481 static volatile int sh_serial_error_fer = 0;
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482 static volatile int sh_serial_error_per = 0;
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483
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484 // Serial I/O - low level error interrupt handler (ISR)
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485 static cyg_uint32
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486 sh_serial_er_ISR(cyg_vector_t vector, cyg_addrword_t data)
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487 {
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488 serial_channel *chan = (serial_channel *)data;
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489 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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490 cyg_uint8 _scr;
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491
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492 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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493 _scr &= ~CYGARC_REG_SCSCR_RIE; // mask rx interrupts
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494 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSCR, _scr);
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495 return CYG_ISR_CALL_DSR; // Cause DSR to be run
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496 }
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497
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498 // Serial I/O - high level error interrupt handler (DSR)
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499 static void
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500 sh_serial_er_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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501 {
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502 serial_channel *chan = (serial_channel *)data;
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503 sh_sci_info *sh_chan = (sh_sci_info *)chan->dev_priv;
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504 cyg_uint8 _ssr, _ssr2;
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505
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506 HAL_READ_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr);
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507 _ssr2 = CYGARC_REG_SCSSR_CLEARMASK;
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508
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509 if (_ssr & CYGARC_REG_SCSSR_ORER) {
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510 _ssr2 &= ~CYGARC_REG_SCSSR_ORER;
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511 sh_serial_error_orer++;
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512 }
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513 if (_ssr & CYGARC_REG_SCSSR_FER) {
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514 _ssr2 &= ~CYGARC_REG_SCSSR_FER;
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515 sh_serial_error_fer++;
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516 }
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517 if (_ssr & CYGARC_REG_SCSSR_PER) {
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518 _ssr2 &= ~CYGARC_REG_SCSSR_PER;
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519 sh_serial_error_per++;
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520 }
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521 HAL_WRITE_UINT8(sh_chan->ctrl_base+SCI_SCSSR, _ssr2);
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522 }
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523
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524 #endif // ifdef CYGDAT_IO_SERIAL_SH_SCI_INL