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annotate packages/kernel/current/tests/kcache2.c @ 3250:283b2c38b413

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Fix compiler warnings. [ Bugzilla 1001865 ]
author vae
date Sat, 15 Jun 2013 20:25:20 +0000
parents cb5a35f3fda4
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*=================================================================
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2 //
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3 // kcache2.c
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4 //
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5 // Cache feature/timing tests
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6 //
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7 //==========================================================================
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8 // ####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later
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16 // version.
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17 //
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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21 // for more details.
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22 //
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23 // You should have received a copy of the GNU General Public License
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24 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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26 //
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27 // As a special exception, if other files instantiate templates or use
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28 // macros or inline functions from this file, or you compile this file
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29 // and link it with other works to produce a work based on this file,
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30 // this file does not by itself cause the resulting work to be covered by
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31 // the GNU General Public License. However the source code for this file
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32 // must still be made available in accordance with section (3) of the GNU
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33 // General Public License v2.
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34 //
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35 // This exception does not invalidate any other reasons why a work based
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36 // on this file might be covered by the GNU General Public License.
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37 // -------------------------------------------
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38 // ####ECOSGPLCOPYRIGHTEND####
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39 //==========================================================================
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40 //#####DESCRIPTIONBEGIN####
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41 //
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42 // Author(s): jskov, based on kcache1.c by dsm
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43 // Contributors: jskov, gthomas
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44 // Date: 1998-12-10
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45 // Description: Tests some of the more exotic cache macros.
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46 //####DESCRIPTIONEND####
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47 */
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48
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49 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
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50
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51 #include <cyg/kernel/kapi.h>
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52
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53 #include <cyg/infra/testcase.h>
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54
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55 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
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56 #ifdef CYGFUN_KERNEL_API_C
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57
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58 #include <cyg/infra/diag.h>
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59 #include <cyg/hal/hal_cache.h>
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60 #include CYGHWR_MEMORY_LAYOUT_H
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61
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62 // -------------------------------------------------------------------------
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63
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64 #define NTHREADS 1
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65 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
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66
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67 // The following are defaults for loop variables. Note they will be overriden
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68 // on simulator targets, where detected - there is no point testing a cache
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69 // which doesn't exist :-).
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70
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71 #define TEST_DZERO_LOOPS 5000 // default number of loops for test_dzero()
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72 #define TIME_ILOCK_LOOPS 10000 // default number of loops for time_ilock()
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73 #define TIME_DLOCK_LOOPS 10000 // default number of loops for time_dlock()
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74
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75 // Define this to enable a simple, but hopefully useful, data cache
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76 // test. It may help discover if the cache support has been defined
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77 // properly (in terms of size and shape)
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78 #ifdef HAL_DCACHE_LINE_SIZE
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79 #define _TEST_DCACHE_OPERATION
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80 #endif
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81
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82 static cyg_handle_t thread[NTHREADS];
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83
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84 static cyg_thread thread_obj[NTHREADS];
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85 static char stack[NTHREADS][STACKSIZE];
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86
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87 #if (CYGMEM_REGION_ram_SIZE <= (128*1024))
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88 # define MAXSIZE (1<<16)
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89 #else
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90 # define MAXSIZE (1<<18)
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91 #endif
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92
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93 volatile char m[MAXSIZE];
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94
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95 // -------------------------------------------------------------------------
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96 // Test of data cache zero.
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97 // o Timing comparison with instructions doing the same amount of work.
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98 // o Check that area cleared with the DCACHE_ZERO macro contains zeros.
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99 #ifdef HAL_DCACHE_ZERO
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100 static void test_dzero(void)
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101 {
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102 register cyg_uint32 k, i;
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103 cyg_tick_count_t count0, count1;
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104 cyg_ucount32 t;
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105 volatile cyg_uint32* aligned_p;
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106 volatile cyg_uint32* p;
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107 register CYG_INTERRUPT_STATE oldints;
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108 cyg_ucount32 test_dzero_loops = TEST_DZERO_LOOPS;
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109
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110 CYG_TEST_INFO("Data cache zero");
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111
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112 if (cyg_test_is_simulator)
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113 test_dzero_loops=10;
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114
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115 aligned_p = (volatile cyg_uint32*)
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116 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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117 & ~(HAL_DCACHE_LINE_SIZE-1));
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118
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119 // Time with conventional instructions.
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120 HAL_DISABLE_INTERRUPTS(oldints);
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121 HAL_DCACHE_SYNC();
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122 HAL_DCACHE_DISABLE();
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123 HAL_DCACHE_SYNC();
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124 HAL_DCACHE_INVALIDATE_ALL();
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125 HAL_DCACHE_ENABLE();
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126 HAL_RESTORE_INTERRUPTS(oldints);
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127 count0 = cyg_current_time();
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128 for (k = 0; k < test_dzero_loops; k++) {
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129 p = aligned_p;
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130 for (i = 0; i < HAL_DCACHE_SETS; i++) {
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131 #if (16 == HAL_DCACHE_LINE_SIZE)
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132 *p++ = 0;
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133 *p++ = 0;
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134 *p++ = 0;
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135 *p++ = 0;
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136 #elif (32 == HAL_DCACHE_LINE_SIZE)
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137 *p++ = 0;
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138 *p++ = 0;
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139 *p++ = 0;
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140 *p++ = 0;
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141 *p++ = 0;
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142 *p++ = 0;
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143 *p++ = 0;
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144 *p++ = 0;
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145 #else
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146 #error "Not defined for this cache line size."
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147 #endif
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148 }
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149
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150 HAL_DISABLE_INTERRUPTS(oldints);
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151 HAL_DCACHE_SYNC();
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152 HAL_DCACHE_DISABLE();
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153 HAL_DCACHE_SYNC();
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154 HAL_DCACHE_INVALIDATE_ALL();
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155 HAL_DCACHE_ENABLE();
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156 HAL_RESTORE_INTERRUPTS(oldints);
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157 }
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158 count1 = cyg_current_time();
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159 t = count1 - count0;
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160 diag_printf("time with instructions: %d\n", t);
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161
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162 // Initialize the area with non-zero so we can check whether
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163 // the macro cleared the area properly.
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164 p = aligned_p;
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165 for (i = 0;
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166 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32);
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167 i++) {
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168 *p++ = 0xdeadbeef;
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169 }
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170
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171 // Time with DCACHE_ZERO.
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172 HAL_DISABLE_INTERRUPTS(oldints);
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173 HAL_DCACHE_SYNC();
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174 HAL_DCACHE_DISABLE();
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175 HAL_DCACHE_SYNC();
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176 HAL_DCACHE_INVALIDATE_ALL();
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177 HAL_DCACHE_ENABLE();
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178 HAL_RESTORE_INTERRUPTS(oldints);
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179 count0 = cyg_current_time();
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180 for (k = 0; k < test_dzero_loops; k++) {
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181 HAL_DCACHE_ZERO(aligned_p, HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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182
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183 HAL_DISABLE_INTERRUPTS(oldints);
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184 HAL_DCACHE_SYNC();
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185 HAL_DCACHE_DISABLE();
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186 HAL_DCACHE_SYNC();
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187 HAL_DCACHE_INVALIDATE_ALL();
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188 HAL_DCACHE_ENABLE();
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189 HAL_RESTORE_INTERRUPTS(oldints);
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190 }
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191 count1 = cyg_current_time();
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192 t = count1 - count0;
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193 diag_printf("time with HAL_DCACHE_ZERO: %d\n", t);
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194
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195 // Verify that the area was actually cleared.
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196 {
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197 cyg_uint32 d;
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198
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199 d = 0;
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200 p = aligned_p;
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201 for (i = 0;
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202 i < HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE/sizeof(cyg_uint32);
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203 i++) {
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204 d |= *p++;
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205 }
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206
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207 CYG_TEST_CHECK(0 == d, "region not properly cleared");
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208 }
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209
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210 }
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211 #endif
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212
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213 // -------------------------------------------------------------------------
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214 // Test of data cache write hint.
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215 // Just check that the macro compiles.
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216 #ifdef HAL_DCACHE_WRITE_HINT
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217 static void test_dwrite_hint(void)
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218 {
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219 register cyg_uint32 k;
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220 register CYG_INTERRUPT_STATE oldints;
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221
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222 CYG_TEST_INFO("Data cache write hint");
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223
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224 HAL_DISABLE_INTERRUPTS(oldints);
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225 HAL_DCACHE_SYNC();
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226 HAL_DCACHE_DISABLE();
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227 HAL_DCACHE_SYNC();
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228 HAL_DCACHE_INVALIDATE_ALL();
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229 HAL_DCACHE_ENABLE();
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230 HAL_RESTORE_INTERRUPTS(oldints);
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231
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232 HAL_DCACHE_WRITE_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE);
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233 for (k = 0; k < 20; k++);
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234 m[HAL_DCACHE_LINE_SIZE*2] = 42;
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235 }
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236 #endif
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237
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238 // -------------------------------------------------------------------------
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239 // Test of data cache read hint.
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240 // Just check that the macro compiles.
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241 #ifdef HAL_DCACHE_READ_HINT
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242 static void test_dread_hint(void)
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243 {
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244 register char c;
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245 register cyg_uint32 k;
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246 register CYG_INTERRUPT_STATE oldints;
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247
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248 CYG_TEST_INFO("Data cache read hint");
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249
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250 HAL_DISABLE_INTERRUPTS(oldints);
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251 HAL_DCACHE_SYNC();
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252 HAL_DCACHE_DISABLE();
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253 HAL_DCACHE_SYNC();
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254 HAL_DCACHE_INVALIDATE_ALL();
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255 HAL_DCACHE_ENABLE();
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256 HAL_RESTORE_INTERRUPTS(oldints);
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257
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258 HAL_DCACHE_READ_HINT(&m[HAL_DCACHE_LINE_SIZE*2], 2*HAL_DCACHE_LINE_SIZE);
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259 for (k = 0; k < 20; k++);
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260 c = m[HAL_DCACHE_LINE_SIZE*2];
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261 }
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262 #endif
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263
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264 // -------------------------------------------------------------------------
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265 // Test of data cache line store
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266 // o No semantic requirement.
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267 // o Check that flushed data is written to memory.
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268 // o Simple invocation check of macro.
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269 #ifdef HAL_DCACHE_STORE
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270 static void test_dstore(void)
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271 {
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272 volatile cyg_uint8* aligned_p;
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273 cyg_int32 i;
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274 register CYG_INTERRUPT_STATE oldints;
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275
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276 CYG_TEST_INFO("Data cache store region");
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277
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278 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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279 m[i] = 0;
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280
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281 HAL_DISABLE_INTERRUPTS(oldints);
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282 HAL_DCACHE_SYNC();
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283 HAL_DCACHE_DISABLE();
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284 HAL_DCACHE_SYNC();
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285 HAL_DCACHE_INVALIDATE_ALL();
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286 HAL_DCACHE_ENABLE();
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287
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288 aligned_p = (volatile cyg_uint8*)
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289 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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290 & ~(HAL_DCACHE_LINE_SIZE-1));
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291
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292 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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293
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294 HAL_DCACHE_STORE(aligned_p, HAL_DCACHE_LINE_SIZE);
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295
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296 CYG_TEST_CHECK(42 == aligned_p[0],
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297 "memory didn't contain flushed data");
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298
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299 HAL_DCACHE_INVALIDATE_ALL(); // Discard...
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300
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301 CYG_TEST_CHECK(42 == aligned_p[0],
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302 "memory didn't contain flushed data after invalidate all");
208
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303
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304 HAL_RESTORE_INTERRUPTS(oldints);
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305 }
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306 #endif
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307
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308 // -------------------------------------------------------------------------
143
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309 // Test of data cache total flush (sync).
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310 // o No semantic requirement.
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311 // o Check that flushed data is written to memory.
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312 // o Simple invocation check of macro.
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313 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
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314
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315 #ifdef _TEST_DCACHE_OPERATION
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316 static void
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317 test_dcache_operation(void)
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318 {
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319 long *lp = (long *)m;
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320 int i, errs;
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321 cyg_uint32 oldints;
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322
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323 CYG_TEST_INFO("Data cache basic");
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324
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325 HAL_DISABLE_INTERRUPTS(oldints);
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326 HAL_DCACHE_SYNC();
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327 HAL_DCACHE_DISABLE();
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328 HAL_DCACHE_SYNC();
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329 // Fill test buffer
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330 for (i = 0; i < sizeof(m)/sizeof(*lp); i++) {
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331 lp[i] = i;
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332 }
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333 HAL_DCACHE_INVALIDATE_ALL();
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334 HAL_DCACHE_ENABLE();
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335 // Now push data through the cache
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336 // Note: 256 seems like a reasonable offset. It may be useful to actually
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337 // compute this (and the size of the test region) based on cache geometry
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338 for (i = 256; i < 256+HAL_DCACHE_SIZE/sizeof(*lp); i++) {
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339 lp[i] = 0xFF000000 + i;
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340 }
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341 // Now force cache clean and off
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342 HAL_DCACHE_SYNC();
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343 HAL_DCACHE_DISABLE();
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344 // Verify the data
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345 diag_printf("Verify data with cache off\n");
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346 errs = 0;
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347 for (i = 0; i < sizeof(m)/sizeof(*lp); i++) {
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348 if ((i >= 256) && (i < 256+HAL_DCACHE_SIZE/sizeof(*lp))) {
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349 if (lp[i] != (0xFF000000 + i)) {
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350 if (++errs < 16) {
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351 diag_printf("Data inside test range changed - was: %x, is %lx, index: %x\n",
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352 0xFF000000+i, lp[i], i);
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353 }
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354 }
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355 } else {
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356 if (lp[i] != i) {
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357 if (++errs < 16) {
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358 diag_printf("Data outside test range changed - was: %x, is %lx, index: %x\n",
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359 i, lp[i], i);
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360 }
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361 }
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362 }
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363 }
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364 CYG_TEST_CHECK(0 == errs, "dcache basic failed");
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365 #if 0 // Additional information
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366 diag_printf("%d total errors during compare\n", errs);
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367 diag_dump_buf(&lp[240], 128);
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368 #endif
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369 HAL_RESTORE_INTERRUPTS(oldints);
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370 }
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371 #endif
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372
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373 static void test_dsync(void)
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374 {
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375 volatile cyg_uint8* aligned_p;
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376 cyg_int32 i;
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377 register CYG_INTERRUPT_STATE oldints;
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378
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379 CYG_TEST_INFO("Data cache sync all");
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380
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381 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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382 m[i] = 0;
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383
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384 HAL_DISABLE_INTERRUPTS(oldints);
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385 HAL_DCACHE_SYNC();
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386 HAL_DCACHE_DISABLE();
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387 HAL_DCACHE_SYNC();
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388 HAL_DCACHE_INVALIDATE_ALL();
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389 HAL_DCACHE_ENABLE();
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390
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391 aligned_p = (volatile cyg_uint8*)
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392 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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393 & ~(HAL_DCACHE_LINE_SIZE-1));
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394
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395 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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396 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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397
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398 HAL_DCACHE_SYNC();
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399
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400 CYG_TEST_CHECK(42 == aligned_p[0],
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401 "memory didn't contain flushed data");
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402 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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403 "memory didn't contain flushed data next block");
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404
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405 HAL_DCACHE_INVALIDATE_ALL();
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406
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407 CYG_TEST_CHECK(42 == aligned_p[0],
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408 "memory didn't contain flushed data after invalidate");
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409 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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410 "memory didn't contain flushed data next block after invalidate");
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411
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412 HAL_RESTORE_INTERRUPTS(oldints);
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413
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414 HAL_ICACHE_INVALIDATE_ALL();
143
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415 HAL_DCACHE_DISABLE();
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416
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417 CYG_TEST_CHECK(42 == aligned_p[0],
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418 "memory didn't contain flushed data after disable");
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419 CYG_TEST_CHECK(43 == aligned_p[HAL_DCACHE_LINE_SIZE],
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420 "memory didn't contain flushed data next block after disable");
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421
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422 HAL_DCACHE_ENABLE();
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423 }
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424 #endif // HAL_DCACHE_LINE_SIZE
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425
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426 // -------------------------------------------------------------------------
2
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427 // Test of data cache line flush.
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428 // o Requires write-back cache.
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429 // o Check that flushed data is written to memory.
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430 // o Simple range check of macro.
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431 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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432 #ifdef HAL_DCACHE_FLUSH
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433 static void test_dflush(void)
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434 {
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435 volatile cyg_uint8* aligned_p;
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436 cyg_int32 i;
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437 register CYG_INTERRUPT_STATE oldints;
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438
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439 CYG_TEST_INFO("Data cache flush region");
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440
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441 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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442 m[i] = 0;
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443
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444 HAL_DISABLE_INTERRUPTS(oldints);
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445 HAL_DCACHE_SYNC();
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446 HAL_DCACHE_DISABLE();
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447 HAL_DCACHE_SYNC();
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448 HAL_DCACHE_INVALIDATE_ALL();
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449 HAL_DCACHE_ENABLE();
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450 HAL_RESTORE_INTERRUPTS(oldints);
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451
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452 aligned_p = (volatile cyg_uint8*)
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453 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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454 & ~(HAL_DCACHE_LINE_SIZE-1));
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455
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456 HAL_DISABLE_INTERRUPTS(oldints);
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457
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458 aligned_p[0] = 42 + aligned_p[1]; // Load causes cache to be used!
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459 aligned_p[HAL_DCACHE_LINE_SIZE] = 43 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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460
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461 HAL_DCACHE_FLUSH(aligned_p, HAL_DCACHE_LINE_SIZE);
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462
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463 HAL_DCACHE_DISABLE();
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464
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465 HAL_RESTORE_INTERRUPTS(oldints);
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466
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467 CYG_TEST_CHECK(42 == aligned_p[0],
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468 "memory didn't contain flushed data");
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469 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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470 "flushed beyond region");
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471
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472 HAL_DCACHE_ENABLE();
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473 }
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474 #endif
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475 #endif
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476
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477 // -------------------------------------------------------------------------
143
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478 // Test of data cache disable (which does NOT force contents out to RAM)
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479 // o Requires write-back cache [so NOT invoked unconditionally]
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480 // o Check that dirty data is not written to memory and is invalidated
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481 // in the cache.
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482 // o Simple invocation check of macro.
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483 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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484 static void test_ddisable(void)
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485 {
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486 volatile cyg_uint8* aligned_p;
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487 cyg_int32 i;
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488 register CYG_INTERRUPT_STATE oldints;
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489
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490 CYG_TEST_INFO("Data cache gross disable");
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491
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492 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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493 m[i] = 0;
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494
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495 HAL_DISABLE_INTERRUPTS(oldints);
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496 HAL_DCACHE_SYNC();
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497 HAL_DCACHE_DISABLE();
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498 HAL_DCACHE_SYNC();
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499 HAL_DCACHE_INVALIDATE_ALL();
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500 HAL_DCACHE_ENABLE();
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501 HAL_RESTORE_INTERRUPTS(oldints);
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502
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503 aligned_p = (volatile cyg_uint8*)
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504 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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505 & ~(HAL_DCACHE_LINE_SIZE-1));
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506
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507 HAL_DISABLE_INTERRUPTS(oldints);
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508
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509 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
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510 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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511
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512 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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513
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514 HAL_DCACHE_DISABLE();
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515
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516 HAL_RESTORE_INTERRUPTS(oldints);
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517
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518 CYG_TEST_CHECK(0 == aligned_p[0] &&
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519 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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520 "cache/memory contained invalidated data");
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521 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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522 "next block contained invalidated data");
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523
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524 HAL_DCACHE_ENABLE();
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525 }
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526 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
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527
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528 // -------------------------------------------------------------------------
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529 // Test of data cache total invalidate.
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530 // o Requires write-back cache.
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531 // o Check that invalidated data is not written to memory and is invalidated
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532 // in the cache.
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533 // o Simple invocation check of macro.
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534 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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535 #ifdef HAL_DCACHE_INVALIDATE_ALL
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536 static void test_dinvalidate_all(void)
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537 {
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538 volatile cyg_uint8* aligned_p;
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539 cyg_int32 i;
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540 register CYG_INTERRUPT_STATE oldints;
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541
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542 CYG_TEST_INFO("Data cache invalidate all");
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543
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544 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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545 m[i] = 0;
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546
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547 HAL_DISABLE_INTERRUPTS(oldints);
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548 HAL_DCACHE_SYNC();
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549 HAL_DCACHE_DISABLE();
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550 HAL_DCACHE_SYNC();
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551 HAL_DCACHE_INVALIDATE_ALL();
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552 HAL_DCACHE_ENABLE();
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553
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554 aligned_p = (volatile cyg_uint8*)
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555 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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556 & ~(HAL_DCACHE_LINE_SIZE-1));
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557
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558 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
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559 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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diff changeset
560
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561 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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562
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563 HAL_DCACHE_INVALIDATE_ALL();
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564
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565 HAL_RESTORE_INTERRUPTS(oldints);
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566
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567 CYG_TEST_CHECK(0 == aligned_p[0] &&
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568 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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569 "cache/memory contained invalidated data");
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570 CYG_TEST_CHECK(0 == aligned_p[HAL_DCACHE_LINE_SIZE],
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571 "next block contained invalidated data");
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572 }
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573 #endif
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574 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
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575
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576 // -------------------------------------------------------------------------
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577 // Test of data cache line invalidate.
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578 // o Requires write-back cache.
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579 // o Check that invalidated data is not written to memory and is invalidated
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580 // in the cache.
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581 // o Simple range check of macro.
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582 #ifdef HAL_DCACHE_QUERY_WRITE_MODE // only if we know this, can we test:
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583 #ifdef HAL_DCACHE_INVALIDATE
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584 static void test_dinvalidate(void)
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585 {
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586 volatile cyg_uint8* aligned_p;
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587 cyg_int32 i;
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588 register CYG_INTERRUPT_STATE oldints;
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589
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590 CYG_TEST_INFO("Data cache invalidate region");
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591
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592 for (i = 0; i < HAL_DCACHE_LINE_SIZE*16; i++)
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593 m[i] = 0;
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594
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595 HAL_DISABLE_INTERRUPTS(oldints);
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596 HAL_DCACHE_SYNC();
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597 HAL_DCACHE_DISABLE();
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598 HAL_DCACHE_SYNC();
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599 HAL_DCACHE_INVALIDATE_ALL();
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600 HAL_DCACHE_ENABLE();
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601 HAL_RESTORE_INTERRUPTS(oldints);
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602
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603 aligned_p = (volatile cyg_uint8*)
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604 (((unsigned long) &m[HAL_DCACHE_LINE_SIZE*2])
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605 & ~(HAL_DCACHE_LINE_SIZE-1));
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606
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607 HAL_DISABLE_INTERRUPTS(oldints);
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608
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609 aligned_p[0] = 43 + aligned_p[1]; // Load causes cache to be used!
2
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610 aligned_p[HAL_DCACHE_LINE_SIZE-1] = 43;
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611
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612 aligned_p[HAL_DCACHE_LINE_SIZE] = 42 + aligned_p[HAL_DCACHE_LINE_SIZE + 1];
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613
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614 HAL_DCACHE_INVALIDATE(aligned_p, HAL_DCACHE_LINE_SIZE);
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615
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616 HAL_RESTORE_INTERRUPTS(oldints);
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617
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618 CYG_TEST_CHECK(0 == aligned_p[0] &&
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619 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
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620 "cache/memory contained invalidated data");
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621 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
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622 "invalidated beyond range");
143
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623
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624 HAL_DCACHE_SYNC();
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625 HAL_DCACHE_DISABLE();
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626
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627 CYG_TEST_CHECK(0 == aligned_p[0] &&
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
628 0 == aligned_p[HAL_DCACHE_LINE_SIZE-1],
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
629 "cache/memory contained invalidated data after SYNC/DIS");
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
630 CYG_TEST_CHECK(42 == aligned_p[HAL_DCACHE_LINE_SIZE],
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
631 "invalidated beyond range after SYNC/DIS");
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
632
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
633 HAL_DCACHE_ENABLE();
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
634 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
635 #endif
143
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT
jlarmour
parents: 66
diff changeset
636 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
637
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
638 // -------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
639 // Test of instruction cache locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
640 // o Time difference between repeatedly executing a bunch of instructions
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
641 // with and without locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
642 #ifdef HAL_ICACHE_LOCK
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
643 static void iloop(unsigned long* start, unsigned long* end, int dummy)
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
644 {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
645 // dummy is just used to fool the compiler to not move the labels
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
646 // around. All callers should call with dummy=0;
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
647
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
648 register char c;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
649 register CYG_INTERRUPT_STATE oldints;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
650
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
651 if (1 == dummy) goto label_end;
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
652
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
653 label_start:
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
654 // Invalidating shouldn't affect locked lines.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
655 HAL_DISABLE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
656 HAL_ICACHE_DISABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
657 HAL_ICACHE_INVALIDATE_ALL();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
658 HAL_ICACHE_ENABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
659 HAL_RESTORE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
660
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
661 c = m[HAL_DCACHE_LINE_SIZE*0];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
662 c = m[HAL_DCACHE_LINE_SIZE*1];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
663 c = m[HAL_DCACHE_LINE_SIZE*2];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
664 c = m[HAL_DCACHE_LINE_SIZE*3];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
665 c = m[HAL_DCACHE_LINE_SIZE*4];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
666 c = m[HAL_DCACHE_LINE_SIZE*5];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
667 c = m[HAL_DCACHE_LINE_SIZE*6];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
668 c = m[HAL_DCACHE_LINE_SIZE*7];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
669 c = m[HAL_DCACHE_LINE_SIZE*8];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
670 c = m[HAL_DCACHE_LINE_SIZE*9];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
671 c = m[HAL_DCACHE_LINE_SIZE*10];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
672 c = m[HAL_DCACHE_LINE_SIZE*11];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
673 c = m[HAL_DCACHE_LINE_SIZE*12];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
674 c = m[HAL_DCACHE_LINE_SIZE*13];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
675 c = m[HAL_DCACHE_LINE_SIZE*14];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
676 c = m[HAL_DCACHE_LINE_SIZE*15];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
677 c = m[HAL_DCACHE_LINE_SIZE*16];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
678 c = m[HAL_DCACHE_LINE_SIZE*17];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
679 c = m[HAL_DCACHE_LINE_SIZE*18];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
680 c = m[HAL_DCACHE_LINE_SIZE*19];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
681 c = m[HAL_DCACHE_LINE_SIZE*20];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
682 c = m[HAL_DCACHE_LINE_SIZE*21];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
683 c = m[HAL_DCACHE_LINE_SIZE*22];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
684 c = m[HAL_DCACHE_LINE_SIZE*23];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
685 c = m[HAL_DCACHE_LINE_SIZE*24];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
686 c = m[HAL_DCACHE_LINE_SIZE*25];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
687 c = m[HAL_DCACHE_LINE_SIZE*26];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
688 c = m[HAL_DCACHE_LINE_SIZE*27];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
689 c = m[HAL_DCACHE_LINE_SIZE*28];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
690 c = m[HAL_DCACHE_LINE_SIZE*29];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
691 c = m[HAL_DCACHE_LINE_SIZE*30];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
692 c = m[HAL_DCACHE_LINE_SIZE*31];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
693 c = m[HAL_DCACHE_LINE_SIZE*32];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
694 c = m[HAL_DCACHE_LINE_SIZE*33];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
695 c = m[HAL_DCACHE_LINE_SIZE*34];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
696 c = m[HAL_DCACHE_LINE_SIZE*35];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
697 c = m[HAL_DCACHE_LINE_SIZE*36];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
698 c = m[HAL_DCACHE_LINE_SIZE*37];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
699 c = m[HAL_DCACHE_LINE_SIZE*38];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
700 c = m[HAL_DCACHE_LINE_SIZE*39];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
701 c = m[HAL_DCACHE_LINE_SIZE*40];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
702 c = m[HAL_DCACHE_LINE_SIZE*41];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
703 c = m[HAL_DCACHE_LINE_SIZE*42];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
704 c = m[HAL_DCACHE_LINE_SIZE*43];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
705 c = m[HAL_DCACHE_LINE_SIZE*44];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
706 c = m[HAL_DCACHE_LINE_SIZE*45];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
707 c = m[HAL_DCACHE_LINE_SIZE*46];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
708 c = m[HAL_DCACHE_LINE_SIZE*47];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
709 c = m[HAL_DCACHE_LINE_SIZE*48];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
710 c = m[HAL_DCACHE_LINE_SIZE*49];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
711 c = m[HAL_DCACHE_LINE_SIZE*50];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
712 c = m[HAL_DCACHE_LINE_SIZE*51];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
713 c = m[HAL_DCACHE_LINE_SIZE*52];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
714 c = m[HAL_DCACHE_LINE_SIZE*53];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
715 c = m[HAL_DCACHE_LINE_SIZE*54];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
716 c = m[HAL_DCACHE_LINE_SIZE*55];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
717 c = m[HAL_DCACHE_LINE_SIZE*56];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
718 c = m[HAL_DCACHE_LINE_SIZE*57];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
719 c = m[HAL_DCACHE_LINE_SIZE*58];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
720 c = m[HAL_DCACHE_LINE_SIZE*59];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
721 c = m[HAL_DCACHE_LINE_SIZE*60];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
722 c = m[HAL_DCACHE_LINE_SIZE*61];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
723 c = m[HAL_DCACHE_LINE_SIZE*62];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
724 c = m[HAL_DCACHE_LINE_SIZE*63];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
725
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
726 label_end:
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
727
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
728 *start = (unsigned long) &&label_start;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
729 *end = (unsigned long) &&label_end;
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
730
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
731 if (1 == dummy) goto label_start;
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
732 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
733
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
734 static void time_ilock(void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
735 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
736 register cyg_ucount32 k;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
737 cyg_tick_count_t count0, count1;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
738 cyg_ucount32 t;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
739 unsigned long start, end;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
740 register cyg_ucount32 time_ilock_loops = TIME_ILOCK_LOOPS;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
741
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
742 CYG_TEST_INFO("Instruction cache lock");
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
743
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
744 if (cyg_test_is_simulator)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
745 time_ilock_loops = 10;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
746
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
747 count0 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
748 for (k = 0; k < time_ilock_loops; k++) {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
749 iloop(&start, &end, 0);
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
750 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
751 count1 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
752 t = count1 - count0;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
753 diag_printf("time without lock: %d\n", t);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
754
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
755 HAL_ICACHE_LOCK(start, end-start);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
756
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
757 count0 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
758 for (k = 0; k < time_ilock_loops; k++) {
199
920b9b754b53 Merge from eCos master repository on 2001-12-15-12:00:33-GMT
jlarmour
parents: 195
diff changeset
759 iloop(&start, &end, 0);
2
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
760 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
761 count1 = cyg_current_time();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
762 t = count1 - count0;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
763 diag_printf("time with lock: %d\n", t);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
764
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
765 HAL_ICACHE_UNLOCK(start, end-start);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
766 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
767 #endif // ifdef HAL_ICACHE_LOCK
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
768
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
769 // -------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
770 // Test of data cache locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
771 // o Time difference between repeatedly accessing a memory region
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
772 // with and without locking.
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
773 #ifdef HAL_DCACHE_LOCK
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
774 static void dloop(void)
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
775 {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
776 register cyg_uint32 j;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
777 register char c;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
778 register CYG_INTERRUPT_STATE oldints;
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
779
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
780 HAL_DISABLE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
781 HAL_DCACHE_SYNC();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
782 HAL_DCACHE_DISABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
783 HAL_DCACHE_SYNC();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
784 HAL_DCACHE_INVALIDATE_ALL();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
785 HAL_DCACHE_ENABLE();
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
786 HAL_RESTORE_INTERRUPTS(oldints);
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
787 for (j = 0; j < HAL_DCACHE_SETS; j++) {
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
788 c = m[HAL_DCACHE_LINE_SIZE*j];
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
789 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
790 }
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
791
443894e2e912 Block commit of eCos version 1.2.1
jlarmour
parents:
diff changeset
792 static void time_dlock(void)
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793 {
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794 register cyg_ucount32 k;
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795 cyg_tick_count_t count0, count1;
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796 cyg_ucount32 t;
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797 register cyg_ucount32 time_dlock_loops = TIME_DLOCK_LOOPS;
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798
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799 CYG_TEST_INFO("Data cache lock");
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800
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801 if (cyg_test_is_simulator)
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802 time_dlock_loops = 10;
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803
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804 count0 = cyg_current_time();
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805 for (k = 0; k < time_dlock_loops; k++) {
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806 dloop();
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807 }
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808 count1 = cyg_current_time();
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809 t = count1 - count0;
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810 diag_printf("time without lock: %d\n", t);
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811
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812 HAL_DCACHE_LOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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813
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814 count0 = cyg_current_time();
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815 for (k = 0; k < time_dlock_loops; k++) {
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816 dloop();
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817 }
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818 count1 = cyg_current_time();
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819 t = count1 - count0;
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820 diag_printf("time with lock: %d\n", t);
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821
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822 HAL_DCACHE_UNLOCK(&m[0], HAL_DCACHE_SETS*HAL_DCACHE_LINE_SIZE);
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823 }
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824 #endif // ifdef HAL_DCACHE_LOCK
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825
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826 // -------------------------------------------------------------------------
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827 static void entry0( cyg_addrword_t data )
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828 {
143
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829 int numtests = 0;
24
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830 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
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831 int wmode;
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832 #endif
2
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833 #ifdef HAL_DCACHE_LOCK
143
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834 time_dlock(); numtests++;
2
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835 #endif
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836 #ifdef HAL_ICACHE_LOCK
143
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837 time_ilock(); numtests++;
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838 #endif
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839 #ifdef HAL_DCACHE_LINE_SIZE // So we can find our way around memory
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840 test_dsync(); numtests++;
2
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841 #endif
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842 #ifdef HAL_DCACHE_STORE
143
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843 test_dstore(); numtests++;
2
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844 #endif
583
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diff changeset
845 #ifdef _TEST_DCACHE_OPERATION
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846 test_dcache_operation(); numtests++;
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diff changeset
847 #endif
2
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848 #ifdef HAL_DCACHE_READ_HINT
143
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849 test_dread_hint(); numtests++;
2
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850 #endif
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851 #ifdef HAL_DCACHE_WRITE_HINT
143
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852 test_dwrite_hint(); numtests++;
2
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853 #endif
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854 #ifdef HAL_DCACHE_ZERO
143
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diff changeset
855 test_dzero(); numtests++;
2
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856 #endif
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857
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diff changeset
858 // The below tests only work on a copy-back cache.
24
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diff changeset
859 #ifdef HAL_DCACHE_QUERY_WRITE_MODE
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diff changeset
860 HAL_DCACHE_QUERY_WRITE_MODE( wmode );
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861
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862 if ( HAL_DCACHE_WRITEBACK_MODE == wmode ) {
143
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diff changeset
863 test_ddisable(); numtests++;
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diff changeset
864 #ifdef HAL_DCACHE_INVALIDATE
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diff changeset
865 test_dinvalidate_all(); numtests++;
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diff changeset
866 #endif
2
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867 #ifdef HAL_DCACHE_FLUSH
143
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diff changeset
868 test_dflush(); numtests++;
2
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diff changeset
869 #endif
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870 #ifdef HAL_DCACHE_INVALIDATE
143
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diff changeset
871 test_dinvalidate(); numtests++;
2
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diff changeset
872 #endif
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873 }
24
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diff changeset
874 #endif // def HAL_DCACHE_QUERY_WRITE_MODE
143
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875 if ( numtests ) {
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diff changeset
876 CYG_TEST_PASS_FINISH("End of test");
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877 }
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diff changeset
878 else {
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diff changeset
879 CYG_TEST_NA( "No applicable cache tests" );
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880 }
2
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881 }
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882
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diff changeset
883 // -------------------------------------------------------------------------
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diff changeset
884
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885 void kcache2_main( void )
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886 {
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887 CYG_TEST_INIT();
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diff changeset
888
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diff changeset
889 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache2",
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diff changeset
890 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
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diff changeset
891 cyg_thread_resume(thread[0]);
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diff changeset
892
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893 cyg_scheduler_start();
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diff changeset
894 }
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diff changeset
895
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896 // -------------------------------------------------------------------------
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diff changeset
897
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diff changeset
898 externC void
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diff changeset
899 cyg_start( void )
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900 {
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901 kcache2_main();
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902 }
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903
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904 // -------------------------------------------------------------------------
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diff changeset
905
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906 #else // def CYGFUN_KERNEL_API_C
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907 #define N_A_MSG "Kernel C API layer disabled"
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908 #endif // def CYGFUN_KERNEL_API_C
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909 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
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910 #define N_A_MSG "Kernel real-time clock disabled"
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911 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
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912
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913 #ifdef N_A_MSG
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914 externC void
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915 cyg_start( void )
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916 {
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917 CYG_TEST_INIT();
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918 CYG_TEST_NA( N_A_MSG );
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919 }
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920 #endif // N_A_MSG
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921
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922 // -------------------------------------------------------------------------
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923 /* EOF kcache2.c */