Mercurial > ecos
annotate packages/hal/powerpc/arch/current/src/hal_misc.c @ 34:29bc183297e1 ecos-sw-1999-09-02
Merge from eCos master repository on 1999-09-02-16:26:10-BST
| author | jlarmour |
|---|---|
| date | Thu, 02 Sep 1999 16:11:22 +0000 |
| parents | 5af43b635655 |
| children | e97d78785e2d |
| rev | line source |
|---|---|
| 2 | 1 //========================================================================== |
| 0 | 2 // |
| 3 // hal_misc.c | |
| 4 // | |
| 5 // HAL miscellaneous functions | |
| 6 // | |
| 2 | 7 //========================================================================== |
| 0 | 8 //####COPYRIGHTBEGIN#### |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 // by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. |
| 26 // All Rights Reserved. | |
| 0 | 27 // ------------------------------------------- |
| 28 // | |
| 29 //####COPYRIGHTEND#### | |
| 2 | 30 //========================================================================== |
| 0 | 31 //#####DESCRIPTIONBEGIN#### |
| 32 // | |
| 2 | 33 // Author(s): nickg, jskov |
| 34 // Contributors: nickg, jskov, | |
| 35 // jlarmour | |
| 36 // Date: 1999-02-20 | |
| 37 // Purpose: HAL miscellaneous functions | |
| 38 // Description: This file contains miscellaneous functions provided by the | |
| 39 // HAL. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 2 | 43 //=========================================================================== |
| 0 | 44 |
| 45 #include <pkgconf/hal.h> | |
| 46 | |
| 2 | 47 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
| 48 #include <cyg/hal/ppc_regs.h> // SPR definitions | |
| 49 | |
| 0 | 50 #include <cyg/infra/cyg_type.h> |
| 51 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 52 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 2 | 53 #include <cyg/infra/diag.h> // diag_printf |
| 0 | 54 |
| 55 #include <cyg/hal/hal_arch.h> // HAL header | |
| 2 | 56 #include <cyg/hal/hal_cache.h> // HAL cache |
| 57 #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ | |
| 58 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 59 # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions | |
| 60 #endif | |
| 0 | 61 |
| 62 //--------------------------------------------------------------------------- | |
| 2 | 63 // Functions used during initialization. |
| 0 | 64 |
| 2 | 65 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
| 66 cyg_bool cyg_hal_stop_constructors; | |
| 67 #endif | |
| 68 | |
| 69 typedef void (*pfunc) (void); | |
| 70 extern pfunc __CTOR_LIST__[]; | |
| 71 extern pfunc __CTOR_END__[]; | |
| 0 | 72 |
| 2 | 73 void |
| 74 cyg_hal_invoke_constructors (void) | |
| 75 { | |
| 76 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG | |
| 77 static pfunc *p = &__CTOR_END__[-1]; | |
| 78 | |
| 79 cyg_hal_stop_constructors = 0; | |
| 80 for (; p >= __CTOR_LIST__; p--) { | |
| 81 (*p) (); | |
| 82 if (cyg_hal_stop_constructors) { | |
| 83 p--; | |
| 84 break; | |
| 0 | 85 } |
| 86 } | |
| 2 | 87 #else |
| 88 pfunc *p; | |
| 89 | |
| 90 for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) | |
| 91 (*p) (); | |
| 92 #endif | |
| 0 | 93 } |
| 94 | |
| 95 // Override any __eabi the compiler might generate. We don't want | |
| 96 // constructors to be called twice. | |
| 97 void __eabi (void) {} | |
| 98 | |
| 99 //--------------------------------------------------------------------------- | |
| 100 // First level C exception handler. | |
| 101 | |
| 102 externC void __handle_exception (void); | |
| 103 | |
| 104 externC HAL_SavedRegisters *_hal_registers; | |
| 105 | |
| 2 | 106 void |
| 107 cyg_hal_exception_handler(HAL_SavedRegisters *regs) | |
| 0 | 108 { |
| 109 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 110 | |
| 111 // Set the pointer to the registers of the current exception | |
| 112 // context. At entry the GDB stub will expand the | |
| 113 // HAL_SavedRegisters structure into a (bigger) register array. | |
| 114 _hal_registers = regs; | |
| 115 | |
| 116 __handle_exception(); | |
| 117 | |
|
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118 #ifdef CYGPKG_HAL_QUICC |
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119 { |
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120 // This is unpleasant: it appears that if we interrupt the board |
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121 // using ^C coming in on the QUICC's SMC1, by planting a breakpoint |
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122 // at the interrupt return address, the decrementer interrupt is |
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123 // not taken when the bp exception returns AND WORSE no other |
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124 // interrupt is possible until the decrementer fires again. This |
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125 // does not apply to simple "incoming character" interrupts; it |
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126 // seems it has to be combined with an immediate trap on RTI for |
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127 // this to occur. |
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128 // |
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129 // The solution is to test for decrementer underflow after the |
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130 // (any) exception, and maybe reinitialize the decrementer. If the |
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131 // decrementer interrupt gets taken, that causes decrementer reinit |
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132 // too, and no harm is done. |
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133 |
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134 cyg_uint32 result; |
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135 asm volatile( |
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136 "mfdec %0;" |
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137 : "=r"(result) |
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138 ); |
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139 |
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140 if ( CYGNUM_HAL_RTC_PERIOD < result ) { |
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141 // then we missed a tick, but the exception masked it |
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142 // reset the decrementer here |
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143 asm volatile( |
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144 "mtdec %0;" |
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145 : : "r"(CYGNUM_HAL_RTC_PERIOD) |
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146 ); |
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147 } |
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148 } |
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149 #endif |
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150 |
| 2 | 151 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ |
| 152 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 153 int vector = regs->vector>>8; | |
| 0 | 154 |
| 155 // We should decode the vector and pass a more appropriate | |
| 156 // value as the second argument. For now we simply pass a | |
| 157 // pointer to the saved registers. We should also divert | |
| 158 // breakpoint and other debug vectors into the debug stubs. | |
| 159 | |
| 2 | 160 if (vector==CYGNUM_HAL_VECTOR_PROGRAM) { |
| 161 int srr1; | |
| 162 CYGARC_MFSPR(CYGARC_REG_SRR1, srr1); // get srr1 | |
| 163 | |
| 164 switch ((srr1 >> 17) & 0xf) { | |
| 165 case 1: | |
| 166 vector = CYGNUM_HAL_EXCEPTION_TRAP; | |
| 167 break; | |
| 168 case 2: | |
| 169 vector = CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION; | |
| 170 break; | |
| 171 case 4: | |
| 172 vector = CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION; | |
| 173 break; | |
| 174 case 8: | |
| 175 vector = CYGNUM_HAL_EXCEPTION_FPU; | |
| 176 break; | |
| 177 default: | |
| 178 CYG_FAIL("Unknown PROGRAM exception!!"); | |
| 179 } | |
| 180 } | |
| 181 cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs ); | |
| 0 | 182 |
| 183 #else | |
| 184 | |
| 185 CYG_FAIL("Exception!!!"); | |
| 186 | |
| 187 #endif | |
| 188 | |
| 189 return; | |
| 190 } | |
| 191 | |
| 192 //--------------------------------------------------------------------------- | |
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193 // Default ISRs |
| 0 | 194 |
| 2 | 195 externC cyg_uint32 |
| 196 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 0 | 197 { |
| 2 | 198 diag_printf("Interrupt: %d\n", vector); |
| 199 | |
| 0 | 200 CYG_FAIL("Spurious Interrupt!!!"); |
| 201 return 0; | |
| 202 } | |
| 203 | |
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204 // The decrementer default ISR has to do nothing. The reason is that |
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205 // decrementer interrupts cannot be disabled - if a kernel configuration |
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206 // does not use the RTC, but does use external interrupts, the decrementer |
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207 // underflow could cause a CYG_FAIL (as above) even though the user did |
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208 // not expect any decrementer interrupts to happen. |
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209 externC cyg_uint32 |
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210 hal_default_decrementer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
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211 { |
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212 return 0; |
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213 } |
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214 |
| 0 | 215 //--------------------------------------------------------------------------- |
| 216 // Idle thread action | |
| 217 | |
| 2 | 218 void |
| 219 hal_idle_thread_action( cyg_uint32 count ) | |
| 0 | 220 { |
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221 #if 0 |
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222 #ifdef CYG_HAL_POWERPC_MPC860 |
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223 register cyg_uint32 result; |
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224 |
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225 cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ; |
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226 cyg_uint32 *psimask = (cyg_uint32*)CYGARC_REG_IMM_SIMASK; |
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227 cyg_uint32 *psipend = (cyg_uint32*)CYGARC_REG_IMM_SIPEND; |
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228 cyg_uint16 *ptbscr = (cyg_uint16*)CYGARC_REG_IMM_TBSCR; |
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229 |
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230 asm volatile( |
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231 "mfdec %0;" |
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232 : "=r"(result) |
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233 ); |
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234 diag_printf( "Dec %08x, TBSCR %04x, vec %d: sivec %08x, simask %08x, sipend %08x\n", |
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235 result, (cyg_uint32)(*ptbscr), (*psivec)>>26, *psivec, *psimask, *psipend ); |
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236 #endif |
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237 #endif |
| 0 | 238 } |
| 239 | |
| 240 //--------------------------------------------------------------------------- | |
| 2 | 241 // Use MMU resources to map memory regions. |
| 242 // Takes and returns an int used to ID the MMU resource to use. This ID | |
| 243 // is increased as resources are used and should be used for subsequent | |
| 244 // invocations. | |
| 245 static int | |
| 246 hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, | |
| 247 cyg_int32 size, cyg_uint8 flags) | |
| 248 { | |
| 249 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 250 { | |
| 251 // Use BATs to map the memory. | |
| 252 cyg_uint32 ubat, lbat; | |
| 253 | |
| 254 ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; | |
| 255 lbat = (phys & LBAT_BRPNMASK); | |
| 256 if (flags & CYGARC_MEMDESC_CI) | |
| 257 lbat |= LBAT_I; | |
| 258 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 259 lbat |= LBAT_G; | |
| 260 | |
| 261 // There are 4 BATs, size is programmable. | |
| 262 while (id < 4 && size > 0) { | |
| 263 cyg_uint32 blk_size = 128*1024; | |
| 264 cyg_uint32 bl = 0; | |
| 265 while (blk_size < 256*1024*1024 && blk_size < size) { | |
| 266 blk_size *= 2; | |
| 267 bl = (bl << 1) | 1; | |
| 268 } | |
| 269 ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); | |
| 270 | |
| 271 switch (id) { | |
| 272 case 0: | |
| 273 CYGARC_MTSPR (IBAT0U, ubat); | |
| 274 CYGARC_MTSPR (IBAT0L, lbat); | |
| 275 CYGARC_MTSPR (DBAT0U, ubat); | |
| 276 CYGARC_MTSPR (DBAT0L, lbat); | |
| 277 break; | |
| 278 case 1: | |
| 279 CYGARC_MTSPR (IBAT1U, ubat); | |
| 280 CYGARC_MTSPR (IBAT1L, lbat); | |
| 281 CYGARC_MTSPR (DBAT1U, ubat); | |
| 282 CYGARC_MTSPR (DBAT1L, lbat); | |
| 283 break; | |
| 284 case 2: | |
| 285 CYGARC_MTSPR (IBAT2U, ubat); | |
| 286 CYGARC_MTSPR (IBAT2L, lbat); | |
| 287 CYGARC_MTSPR (DBAT2U, ubat); | |
| 288 CYGARC_MTSPR (DBAT2L, lbat); | |
| 289 break; | |
| 290 case 3: | |
| 291 CYGARC_MTSPR (IBAT3U, ubat); | |
| 292 CYGARC_MTSPR (IBAT3L, lbat); | |
| 293 CYGARC_MTSPR (DBAT3U, ubat); | |
| 294 CYGARC_MTSPR (DBAT3L, lbat); | |
| 295 break; | |
| 296 } | |
| 297 | |
| 298 size -= blk_size; | |
| 299 id++; | |
| 300 } | |
| 301 } | |
| 302 #endif | |
| 303 | |
| 304 | |
| 305 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 306 { | |
| 307 // The MPC8xx CPUs do not have BATs. Fortunately we don't | |
| 308 // currently use the MMU, so we can simulate BATs by using the | |
| 309 // TLBs. | |
| 310 | |
| 311 cyg_uint32 epn, rpn, ctr, twc; | |
| 312 int max_tlbs; | |
| 313 | |
| 314 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 315 // There are 32 TLBs. | |
| 316 max_tlbs = 32; | |
| 317 #endif | |
| 318 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 319 // There are 8 TLBs. | |
| 320 max_tlbs = 8; | |
| 321 #endif | |
| 322 | |
| 323 epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; | |
| 324 rpn = ((phys & MI_RPN_RPNMASK) | |
| 325 | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V); | |
| 326 if (flags & CYGARC_MEMDESC_CI) | |
| 327 rpn |= MI_RPN_CI; | |
| 328 | |
| 329 twc = MI_TWC_PS8MB | MI_TWC_V; | |
| 330 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 331 twc |= MI_TWC_G; | |
| 332 | |
| 333 // Ignore attempts to use more than max_tlbs. | |
| 334 while (id < max_tlbs && size > 0) { | |
| 335 ctr = id << MI_CTR_INDX_SHIFT; | |
| 336 | |
| 337 // Instruction TLB. | |
| 338 CYGARC_MTSPR (MI_TWC, twc); | |
| 339 CYGARC_MTSPR (MI_CTR, ctr); | |
| 340 CYGARC_MTSPR (MI_EPN, epn); | |
| 341 CYGARC_MTSPR (MI_RPN, rpn); | |
| 342 | |
| 343 // Data TLB. | |
| 344 { | |
| 345 cyg_uint32 drpn; | |
| 346 | |
| 347 // Need to mark data page as changed or an exception | |
| 348 // will be generated on first write to the page. | |
| 349 drpn = rpn | MD_RPN_CHANGED; | |
| 350 | |
| 351 CYGARC_MTSPR (MD_TWC, twc); | |
| 352 CYGARC_MTSPR (MD_CTR, ctr); | |
| 353 CYGARC_MTSPR (MD_EPN, epn); | |
| 354 CYGARC_MTSPR (MD_RPN, drpn); | |
| 355 } | |
| 356 | |
| 357 // Move to next 8MB block. | |
| 358 size -= 8*1024*1024; | |
| 359 epn += 8*1024*1024; | |
| 360 rpn += 8*1024*1024; | |
| 361 id++; | |
| 362 } | |
| 363 } | |
| 364 #endif | |
| 365 | |
| 366 return id; | |
| 367 } | |
| 368 | |
| 369 | |
| 370 // Initialize MMU to a sane (NOP) state. | |
| 371 static void | |
| 372 hal_clear_MMU (void) | |
| 373 { | |
| 374 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 375 { | |
| 376 cyg_uint32 ubat, lbat; | |
| 377 | |
| 378 // Initialize BATs with 0 -- VS&VP are unset, making all matches fail | |
| 379 ubat = 0; | |
| 380 lbat = 0; | |
| 381 | |
| 382 CYGARC_MTSPR (IBAT0U, ubat); | |
| 383 CYGARC_MTSPR (IBAT0L, lbat); | |
| 384 CYGARC_MTSPR (DBAT0U, ubat); | |
| 385 CYGARC_MTSPR (DBAT0L, lbat); | |
| 386 CYGARC_MTSPR (IBAT1U, ubat); | |
| 387 CYGARC_MTSPR (IBAT1L, lbat); | |
| 388 CYGARC_MTSPR (DBAT1U, ubat); | |
| 389 CYGARC_MTSPR (DBAT1L, lbat); | |
| 390 CYGARC_MTSPR (IBAT2U, ubat); | |
| 391 CYGARC_MTSPR (IBAT2L, lbat); | |
| 392 CYGARC_MTSPR (DBAT2U, ubat); | |
| 393 CYGARC_MTSPR (DBAT2L, lbat); | |
| 394 CYGARC_MTSPR (IBAT3U, ubat); | |
| 395 CYGARC_MTSPR (IBAT3L, lbat); | |
| 396 CYGARC_MTSPR (DBAT3U, ubat); | |
| 397 CYGARC_MTSPR (DBAT3L, lbat); | |
| 398 } | |
| 399 #endif | |
| 400 | |
| 401 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 402 { | |
| 403 // Initialize TLBs with 0, Valid bits unset. | |
| 404 | |
| 405 cyg_uint32 ctr; | |
| 406 int id; | |
| 407 int max_tlbs; | |
| 408 | |
| 409 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 410 // There are 32 TLBs. | |
| 411 max_tlbs = 32; | |
| 412 #endif | |
| 413 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 414 // There are 8 TLBs. | |
| 415 max_tlbs = 8; | |
| 416 #endif | |
| 417 | |
| 418 CYGARC_MTSPR (M_CASID, 0); | |
| 419 | |
| 420 for (id = 0; id < max_tlbs; id++) { | |
| 421 ctr = id << MI_CTR_INDX_SHIFT; | |
| 422 | |
| 423 // Instruction TLBs. | |
| 424 CYGARC_MTSPR (MI_TWC, 0); | |
| 425 CYGARC_MTSPR (MI_CTR, ctr); | |
| 426 CYGARC_MTSPR (MI_EPN, 0); | |
| 427 CYGARC_MTSPR (MI_RPN, 0); | |
| 428 // Data TLBs. | |
| 429 CYGARC_MTSPR (MD_TWC, 0); | |
| 430 CYGARC_MTSPR (MD_CTR, ctr); | |
| 431 CYGARC_MTSPR (MD_EPN, 0); | |
| 432 CYGARC_MTSPR (MD_RPN, 0); | |
| 433 } | |
| 434 } | |
| 435 #endif | |
| 436 } | |
| 437 | |
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438 // NB this demands that the platform HAL has provided an |
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439 // externC cyg_memdesc_t cyg_hal_mem_map[]; |
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440 // as detailed in hal_cache.h: |
| 2 | 441 externC void hal_MMU_init (void) |
| 442 { | |
| 443 int id = 0; | |
| 444 int i = 0; | |
| 445 | |
| 446 hal_clear_MMU (); | |
| 447 | |
| 448 while (cyg_hal_mem_map[i].size) { | |
| 449 id = hal_map_memory (id, | |
| 450 cyg_hal_mem_map[i].virtual_addr, | |
| 451 cyg_hal_mem_map[i].physical_addr, | |
| 452 cyg_hal_mem_map[i].size, | |
| 453 cyg_hal_mem_map[i].flags); | |
| 454 i++; | |
| 455 } | |
| 456 } | |
| 457 | |
| 458 //--------------------------------------------------------------------------- | |
| 459 // Initial cache enabling | |
|
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460 |
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461 // These are "indirected" to make it easier to support other platform |
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462 // variants in the future: |
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463 |
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464 #ifdef CYGPKG_HAL_POWERPC_COGENT |
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465 # define CYGPRI_INIT_CACHES 1 |
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466 # ifdef CYG_HAL_STARTUP_RAM |
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467 # define CYGPRI_ENABLE_CACHES 1 |
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468 # endif |
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469 #endif |
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470 |
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471 #ifdef CYGPKG_HAL_POWERPC_MBX // Enable all caches for MBX860 |
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472 # ifndef CYG_HAL_ROM_MONITOR // unless we are making a stub rom |
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473 # define CYGPRI_INIT_CACHES 1 |
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474 # define CYGPRI_ENABLE_CACHES 1 |
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475 # endif |
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476 #endif |
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477 |
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478 // Do not enable caches for the FADS port pro tem; the memory mapping is |
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479 // not set up. |
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480 |
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481 // Do not enable caches for the simulator, it just slows it down. |
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482 |
| 2 | 483 externC void |
| 484 hal_enable_caches(void) | |
| 485 { | |
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486 #ifdef CYGPRI_INIT_CACHES |
| 2 | 487 // Initialize caches. |
| 488 HAL_ICACHE_UNLOCK_ALL(); | |
| 489 HAL_DCACHE_UNLOCK_ALL(); | |
| 490 HAL_ICACHE_INVALIDATE_ALL(); | |
| 491 HAL_DCACHE_INVALIDATE_ALL(); | |
| 492 | |
| 493 // Enable caches. | |
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494 #ifdef CYGPRI_ENABLE_CACHES |
| 2 | 495 // Cogent board doesn't support burst access to the ROM and on the |
| 496 // MPC8xx caches require burst. | |
| 497 HAL_ICACHE_ENABLE(); | |
| 498 HAL_DCACHE_ENABLE(); | |
| 499 #endif | |
| 500 #endif | |
| 501 | |
| 502 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 503 // Disable serialization | |
| 504 { | |
| 505 cyg_uint32 ictrl; | |
| 506 CYGARC_MFSPR (ICTRL, ictrl); | |
| 507 ictrl |= ICTRL_NOSERSHOW; | |
| 508 CYGARC_MTSPR (ICTRL, ictrl); | |
| 509 } | |
| 510 #endif | |
| 511 } | |
| 512 | |
| 513 //--------------------------------------------------------------------------- | |
| 0 | 514 // End of hal_misc.c |