Mercurial > ecos
annotate packages/hal/powerpc/arch/current/src/hal_misc.c @ 32:5af43b635655 ecos-sw-1999-08-18
Merge from eCos master repository on 1999-08-18-15:20:01-BST
| author | jlarmour |
|---|---|
| date | Wed, 18 Aug 1999 15:33:44 +0000 |
| parents | 7253dcc42a09 |
| children | 29bc183297e1 |
| rev | line source |
|---|---|
| 2 | 1 //========================================================================== |
| 0 | 2 // |
| 3 // hal_misc.c | |
| 4 // | |
| 5 // HAL miscellaneous functions | |
| 6 // | |
| 2 | 7 //========================================================================== |
| 0 | 8 //####COPYRIGHTBEGIN#### |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 // by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions. |
| 26 // All Rights Reserved. | |
| 0 | 27 // ------------------------------------------- |
| 28 // | |
| 29 //####COPYRIGHTEND#### | |
| 2 | 30 //========================================================================== |
| 0 | 31 //#####DESCRIPTIONBEGIN#### |
| 32 // | |
| 2 | 33 // Author(s): nickg, jskov |
| 34 // Contributors: nickg, jskov, | |
| 35 // jlarmour | |
| 36 // Date: 1999-02-20 | |
| 37 // Purpose: HAL miscellaneous functions | |
| 38 // Description: This file contains miscellaneous functions provided by the | |
| 39 // HAL. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 2 | 43 //=========================================================================== |
| 0 | 44 |
|
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45 #include <pkgconf/system.h> |
| 0 | 46 #include <pkgconf/hal.h> |
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47 #include CYGBLD_HAL_TARGET_H |
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48 #include CYGBLD_HAL_PLATFORM_H |
| 0 | 49 |
| 2 | 50 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
| 51 #include <cyg/hal/ppc_regs.h> // SPR definitions | |
| 52 | |
| 0 | 53 #include <cyg/infra/cyg_type.h> |
| 54 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 55 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 2 | 56 #include <cyg/infra/diag.h> // diag_printf |
| 0 | 57 |
| 58 #include <cyg/hal/hal_arch.h> // HAL header | |
| 2 | 59 #include <cyg/hal/hal_cache.h> // HAL cache |
| 60 #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ | |
| 61 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 62 # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions | |
| 63 #endif | |
| 0 | 64 |
| 65 //--------------------------------------------------------------------------- | |
| 2 | 66 // Functions used during initialization. |
| 0 | 67 |
| 2 | 68 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
| 69 cyg_bool cyg_hal_stop_constructors; | |
| 70 #endif | |
| 71 | |
| 72 typedef void (*pfunc) (void); | |
| 73 extern pfunc __CTOR_LIST__[]; | |
| 74 extern pfunc __CTOR_END__[]; | |
| 0 | 75 |
| 2 | 76 void |
| 77 cyg_hal_invoke_constructors (void) | |
| 78 { | |
| 79 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG | |
| 80 static pfunc *p = &__CTOR_END__[-1]; | |
| 81 | |
| 82 cyg_hal_stop_constructors = 0; | |
| 83 for (; p >= __CTOR_LIST__; p--) { | |
| 84 (*p) (); | |
| 85 if (cyg_hal_stop_constructors) { | |
| 86 p--; | |
| 87 break; | |
| 0 | 88 } |
| 89 } | |
| 2 | 90 #else |
| 91 pfunc *p; | |
| 92 | |
| 93 for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) | |
| 94 (*p) (); | |
| 95 #endif | |
| 0 | 96 } |
| 97 | |
| 98 // Override any __eabi the compiler might generate. We don't want | |
| 99 // constructors to be called twice. | |
| 100 void __eabi (void) {} | |
| 101 | |
| 102 //--------------------------------------------------------------------------- | |
| 103 // First level C exception handler. | |
| 104 | |
| 105 externC void __handle_exception (void); | |
| 106 | |
| 107 externC HAL_SavedRegisters *_hal_registers; | |
| 108 | |
| 2 | 109 void |
| 110 cyg_hal_exception_handler(HAL_SavedRegisters *regs) | |
| 0 | 111 { |
| 112 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 113 | |
| 114 // Set the pointer to the registers of the current exception | |
| 115 // context. At entry the GDB stub will expand the | |
| 116 // HAL_SavedRegisters structure into a (bigger) register array. | |
| 117 _hal_registers = regs; | |
| 118 | |
| 119 __handle_exception(); | |
| 120 | |
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121 #ifdef CYGPKG_HAL_QUICC |
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122 { |
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123 // This is unpleasant: it appears that if we interrupt the board |
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124 // using ^C coming in on the QUICC's SMC1, by planting a breakpoint |
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125 // at the interrupt return address, the decrementer interrupt is |
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126 // not taken when the bp exception returns AND WORSE no other |
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127 // interrupt is possible until the decrementer fires again. This |
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128 // does not apply to simple "incoming character" interrupts; it |
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129 // seems it has to be combined with an immediate trap on RTI for |
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130 // this to occur. |
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131 // |
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132 // The solution is to test for decrementer underflow after the |
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133 // (any) exception, and maybe reinitialize the decrementer. If the |
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134 // decrementer interrupt gets taken, that causes decrementer reinit |
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135 // too, and no harm is done. |
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136 |
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137 cyg_uint32 result; |
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138 asm volatile( |
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139 "mfdec %0;" |
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140 : "=r"(result) |
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141 ); |
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142 |
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143 if ( CYGNUM_HAL_RTC_PERIOD < result ) { |
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144 // then we missed a tick, but the exception masked it |
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145 // reset the decrementer here |
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146 asm volatile( |
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147 "mtdec %0;" |
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148 : : "r"(CYGNUM_HAL_RTC_PERIOD) |
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149 ); |
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150 } |
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151 } |
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152 #endif |
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153 |
| 2 | 154 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \ |
| 155 defined(CYGPKG_HAL_EXCEPTIONS) | |
| 156 int vector = regs->vector>>8; | |
| 0 | 157 |
| 158 // We should decode the vector and pass a more appropriate | |
| 159 // value as the second argument. For now we simply pass a | |
| 160 // pointer to the saved registers. We should also divert | |
| 161 // breakpoint and other debug vectors into the debug stubs. | |
| 162 | |
| 2 | 163 if (vector==CYGNUM_HAL_VECTOR_PROGRAM) { |
| 164 int srr1; | |
| 165 CYGARC_MFSPR(CYGARC_REG_SRR1, srr1); // get srr1 | |
| 166 | |
| 167 switch ((srr1 >> 17) & 0xf) { | |
| 168 case 1: | |
| 169 vector = CYGNUM_HAL_EXCEPTION_TRAP; | |
| 170 break; | |
| 171 case 2: | |
| 172 vector = CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION; | |
| 173 break; | |
| 174 case 4: | |
| 175 vector = CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION; | |
| 176 break; | |
| 177 case 8: | |
| 178 vector = CYGNUM_HAL_EXCEPTION_FPU; | |
| 179 break; | |
| 180 default: | |
| 181 CYG_FAIL("Unknown PROGRAM exception!!"); | |
| 182 } | |
| 183 } | |
| 184 cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs ); | |
| 0 | 185 |
| 186 #else | |
| 187 | |
| 188 CYG_FAIL("Exception!!!"); | |
| 189 | |
| 190 #endif | |
| 191 | |
| 192 return; | |
| 193 } | |
| 194 | |
| 195 //--------------------------------------------------------------------------- | |
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196 // Default ISRs |
| 0 | 197 |
| 2 | 198 externC cyg_uint32 |
| 199 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) | |
| 0 | 200 { |
| 2 | 201 diag_printf("Interrupt: %d\n", vector); |
| 202 | |
| 0 | 203 CYG_FAIL("Spurious Interrupt!!!"); |
| 204 return 0; | |
| 205 } | |
| 206 | |
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207 // The decrementer default ISR has to do nothing. The reason is that |
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208 // decrementer interrupts cannot be disabled - if a kernel configuration |
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209 // does not use the RTC, but does use external interrupts, the decrementer |
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210 // underflow could cause a CYG_FAIL (as above) even though the user did |
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211 // not expect any decrementer interrupts to happen. |
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212 externC cyg_uint32 |
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213 hal_default_decrementer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
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214 { |
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215 return 0; |
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216 } |
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217 |
| 0 | 218 //--------------------------------------------------------------------------- |
| 219 // Idle thread action | |
| 220 | |
| 2 | 221 void |
| 222 hal_idle_thread_action( cyg_uint32 count ) | |
| 0 | 223 { |
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224 #if 0 |
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225 #ifdef CYG_HAL_POWERPC_MPC860 |
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226 register cyg_uint32 result; |
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227 |
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228 cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ; |
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229 cyg_uint32 *psimask = (cyg_uint32*)CYGARC_REG_IMM_SIMASK; |
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230 cyg_uint32 *psipend = (cyg_uint32*)CYGARC_REG_IMM_SIPEND; |
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231 cyg_uint16 *ptbscr = (cyg_uint16*)CYGARC_REG_IMM_TBSCR; |
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232 |
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233 asm volatile( |
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234 "mfdec %0;" |
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235 : "=r"(result) |
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236 ); |
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237 diag_printf( "Dec %08x, TBSCR %04x, vec %d: sivec %08x, simask %08x, sipend %08x\n", |
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238 result, (cyg_uint32)(*ptbscr), (*psivec)>>26, *psivec, *psimask, *psipend ); |
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239 #endif |
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240 #endif |
| 0 | 241 } |
| 242 | |
| 243 //--------------------------------------------------------------------------- | |
| 2 | 244 // Use MMU resources to map memory regions. |
| 245 // Takes and returns an int used to ID the MMU resource to use. This ID | |
| 246 // is increased as resources are used and should be used for subsequent | |
| 247 // invocations. | |
| 248 static int | |
| 249 hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys, | |
| 250 cyg_int32 size, cyg_uint8 flags) | |
| 251 { | |
| 252 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 253 { | |
| 254 // Use BATs to map the memory. | |
| 255 cyg_uint32 ubat, lbat; | |
| 256 | |
| 257 ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP; | |
| 258 lbat = (phys & LBAT_BRPNMASK); | |
| 259 if (flags & CYGARC_MEMDESC_CI) | |
| 260 lbat |= LBAT_I; | |
| 261 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 262 lbat |= LBAT_G; | |
| 263 | |
| 264 // There are 4 BATs, size is programmable. | |
| 265 while (id < 4 && size > 0) { | |
| 266 cyg_uint32 blk_size = 128*1024; | |
| 267 cyg_uint32 bl = 0; | |
| 268 while (blk_size < 256*1024*1024 && blk_size < size) { | |
| 269 blk_size *= 2; | |
| 270 bl = (bl << 1) | 1; | |
| 271 } | |
| 272 ubat = (ubat & ~UBAT_BLMASK) | (bl << 2); | |
| 273 | |
| 274 switch (id) { | |
| 275 case 0: | |
| 276 CYGARC_MTSPR (IBAT0U, ubat); | |
| 277 CYGARC_MTSPR (IBAT0L, lbat); | |
| 278 CYGARC_MTSPR (DBAT0U, ubat); | |
| 279 CYGARC_MTSPR (DBAT0L, lbat); | |
| 280 break; | |
| 281 case 1: | |
| 282 CYGARC_MTSPR (IBAT1U, ubat); | |
| 283 CYGARC_MTSPR (IBAT1L, lbat); | |
| 284 CYGARC_MTSPR (DBAT1U, ubat); | |
| 285 CYGARC_MTSPR (DBAT1L, lbat); | |
| 286 break; | |
| 287 case 2: | |
| 288 CYGARC_MTSPR (IBAT2U, ubat); | |
| 289 CYGARC_MTSPR (IBAT2L, lbat); | |
| 290 CYGARC_MTSPR (DBAT2U, ubat); | |
| 291 CYGARC_MTSPR (DBAT2L, lbat); | |
| 292 break; | |
| 293 case 3: | |
| 294 CYGARC_MTSPR (IBAT3U, ubat); | |
| 295 CYGARC_MTSPR (IBAT3L, lbat); | |
| 296 CYGARC_MTSPR (DBAT3U, ubat); | |
| 297 CYGARC_MTSPR (DBAT3L, lbat); | |
| 298 break; | |
| 299 } | |
| 300 | |
| 301 size -= blk_size; | |
| 302 id++; | |
| 303 } | |
| 304 } | |
| 305 #endif | |
| 306 | |
| 307 | |
| 308 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 309 { | |
| 310 // The MPC8xx CPUs do not have BATs. Fortunately we don't | |
| 311 // currently use the MMU, so we can simulate BATs by using the | |
| 312 // TLBs. | |
| 313 | |
| 314 cyg_uint32 epn, rpn, ctr, twc; | |
| 315 int max_tlbs; | |
| 316 | |
| 317 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 318 // There are 32 TLBs. | |
| 319 max_tlbs = 32; | |
| 320 #endif | |
| 321 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 322 // There are 8 TLBs. | |
| 323 max_tlbs = 8; | |
| 324 #endif | |
| 325 | |
| 326 epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV; | |
| 327 rpn = ((phys & MI_RPN_RPNMASK) | |
| 328 | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V); | |
| 329 if (flags & CYGARC_MEMDESC_CI) | |
| 330 rpn |= MI_RPN_CI; | |
| 331 | |
| 332 twc = MI_TWC_PS8MB | MI_TWC_V; | |
| 333 if (flags & CYGARC_MEMDESC_GUARDED) | |
| 334 twc |= MI_TWC_G; | |
| 335 | |
| 336 // Ignore attempts to use more than max_tlbs. | |
| 337 while (id < max_tlbs && size > 0) { | |
| 338 ctr = id << MI_CTR_INDX_SHIFT; | |
| 339 | |
| 340 // Instruction TLB. | |
| 341 CYGARC_MTSPR (MI_TWC, twc); | |
| 342 CYGARC_MTSPR (MI_CTR, ctr); | |
| 343 CYGARC_MTSPR (MI_EPN, epn); | |
| 344 CYGARC_MTSPR (MI_RPN, rpn); | |
| 345 | |
| 346 // Data TLB. | |
| 347 { | |
| 348 cyg_uint32 drpn; | |
| 349 | |
| 350 // Need to mark data page as changed or an exception | |
| 351 // will be generated on first write to the page. | |
| 352 drpn = rpn | MD_RPN_CHANGED; | |
| 353 | |
| 354 CYGARC_MTSPR (MD_TWC, twc); | |
| 355 CYGARC_MTSPR (MD_CTR, ctr); | |
| 356 CYGARC_MTSPR (MD_EPN, epn); | |
| 357 CYGARC_MTSPR (MD_RPN, drpn); | |
| 358 } | |
| 359 | |
| 360 // Move to next 8MB block. | |
| 361 size -= 8*1024*1024; | |
| 362 epn += 8*1024*1024; | |
| 363 rpn += 8*1024*1024; | |
| 364 id++; | |
| 365 } | |
| 366 } | |
| 367 #endif | |
| 368 | |
| 369 return id; | |
| 370 } | |
| 371 | |
| 372 | |
| 373 // Initialize MMU to a sane (NOP) state. | |
| 374 static void | |
| 375 hal_clear_MMU (void) | |
| 376 { | |
| 377 #ifdef CYG_HAL_POWERPC_MPC603 | |
| 378 { | |
| 379 cyg_uint32 ubat, lbat; | |
| 380 | |
| 381 // Initialize BATs with 0 -- VS&VP are unset, making all matches fail | |
| 382 ubat = 0; | |
| 383 lbat = 0; | |
| 384 | |
| 385 CYGARC_MTSPR (IBAT0U, ubat); | |
| 386 CYGARC_MTSPR (IBAT0L, lbat); | |
| 387 CYGARC_MTSPR (DBAT0U, ubat); | |
| 388 CYGARC_MTSPR (DBAT0L, lbat); | |
| 389 CYGARC_MTSPR (IBAT1U, ubat); | |
| 390 CYGARC_MTSPR (IBAT1L, lbat); | |
| 391 CYGARC_MTSPR (DBAT1U, ubat); | |
| 392 CYGARC_MTSPR (DBAT1L, lbat); | |
| 393 CYGARC_MTSPR (IBAT2U, ubat); | |
| 394 CYGARC_MTSPR (IBAT2L, lbat); | |
| 395 CYGARC_MTSPR (DBAT2U, ubat); | |
| 396 CYGARC_MTSPR (DBAT2L, lbat); | |
| 397 CYGARC_MTSPR (IBAT3U, ubat); | |
| 398 CYGARC_MTSPR (IBAT3L, lbat); | |
| 399 CYGARC_MTSPR (DBAT3U, ubat); | |
| 400 CYGARC_MTSPR (DBAT3L, lbat); | |
| 401 } | |
| 402 #endif | |
| 403 | |
| 404 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 405 { | |
| 406 // Initialize TLBs with 0, Valid bits unset. | |
| 407 | |
| 408 cyg_uint32 ctr; | |
| 409 int id; | |
| 410 int max_tlbs; | |
| 411 | |
| 412 #if defined(CYG_HAL_POWERPC_MPC860) | |
| 413 // There are 32 TLBs. | |
| 414 max_tlbs = 32; | |
| 415 #endif | |
| 416 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 417 // There are 8 TLBs. | |
| 418 max_tlbs = 8; | |
| 419 #endif | |
| 420 | |
| 421 CYGARC_MTSPR (M_CASID, 0); | |
| 422 | |
| 423 for (id = 0; id < max_tlbs; id++) { | |
| 424 ctr = id << MI_CTR_INDX_SHIFT; | |
| 425 | |
| 426 // Instruction TLBs. | |
| 427 CYGARC_MTSPR (MI_TWC, 0); | |
| 428 CYGARC_MTSPR (MI_CTR, ctr); | |
| 429 CYGARC_MTSPR (MI_EPN, 0); | |
| 430 CYGARC_MTSPR (MI_RPN, 0); | |
| 431 // Data TLBs. | |
| 432 CYGARC_MTSPR (MD_TWC, 0); | |
| 433 CYGARC_MTSPR (MD_CTR, ctr); | |
| 434 CYGARC_MTSPR (MD_EPN, 0); | |
| 435 CYGARC_MTSPR (MD_RPN, 0); | |
| 436 } | |
| 437 } | |
| 438 #endif | |
| 439 } | |
| 440 | |
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441 // NB this demands that the platform HAL has provided an |
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442 // externC cyg_memdesc_t cyg_hal_mem_map[]; |
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443 // as detailed in hal_cache.h: |
| 2 | 444 externC void hal_MMU_init (void) |
| 445 { | |
| 446 int id = 0; | |
| 447 int i = 0; | |
| 448 | |
| 449 hal_clear_MMU (); | |
| 450 | |
| 451 while (cyg_hal_mem_map[i].size) { | |
| 452 id = hal_map_memory (id, | |
| 453 cyg_hal_mem_map[i].virtual_addr, | |
| 454 cyg_hal_mem_map[i].physical_addr, | |
| 455 cyg_hal_mem_map[i].size, | |
| 456 cyg_hal_mem_map[i].flags); | |
| 457 i++; | |
| 458 } | |
| 459 } | |
| 460 | |
| 461 //--------------------------------------------------------------------------- | |
| 462 // Initial cache enabling | |
|
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463 |
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464 // These are "indirected" to make it easier to support other platform |
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465 // variants in the future: |
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466 |
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467 #ifdef CYGPKG_HAL_POWERPC_COGENT |
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468 # define CYGPRI_INIT_CACHES 1 |
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469 # ifdef CYG_HAL_STARTUP_RAM |
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470 # define CYGPRI_ENABLE_CACHES 1 |
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471 # endif |
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472 #endif |
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473 |
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474 #ifdef CYGPKG_HAL_POWERPC_MBX // Enable all caches for MBX860 |
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475 # ifndef CYG_HAL_ROM_MONITOR // unless we are making a stub rom |
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476 # define CYGPRI_INIT_CACHES 1 |
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477 # define CYGPRI_ENABLE_CACHES 1 |
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478 # endif |
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479 #endif |
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480 |
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481 // Do not enable caches for the FADS port pro tem; the memory mapping is |
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482 // not set up. |
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483 |
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484 // Do not enable caches for the simulator, it just slows it down. |
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485 |
| 2 | 486 externC void |
| 487 hal_enable_caches(void) | |
| 488 { | |
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489 #ifdef CYGPRI_INIT_CACHES |
| 2 | 490 // Initialize caches. |
| 491 HAL_ICACHE_UNLOCK_ALL(); | |
| 492 HAL_DCACHE_UNLOCK_ALL(); | |
| 493 HAL_ICACHE_INVALIDATE_ALL(); | |
| 494 HAL_DCACHE_INVALIDATE_ALL(); | |
| 495 | |
| 496 // Enable caches. | |
|
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497 #ifdef CYGPRI_ENABLE_CACHES |
| 2 | 498 // Cogent board doesn't support burst access to the ROM and on the |
| 499 // MPC8xx caches require burst. | |
| 500 HAL_ICACHE_ENABLE(); | |
| 501 HAL_DCACHE_ENABLE(); | |
| 502 #endif | |
| 503 #endif | |
| 504 | |
| 505 #ifdef CYG_HAL_POWERPC_MPC8xx | |
| 506 // Disable serialization | |
| 507 { | |
| 508 cyg_uint32 ictrl; | |
| 509 CYGARC_MFSPR (ICTRL, ictrl); | |
| 510 ictrl |= ICTRL_NOSERSHOW; | |
| 511 CYGARC_MTSPR (ICTRL, ictrl); | |
| 512 } | |
| 513 #endif | |
| 514 } | |
| 515 | |
| 516 //--------------------------------------------------------------------------- | |
| 0 | 517 // End of hal_misc.c |