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annotate packages/hal/mips/arch/current/src/vectors.S @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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children 443894e2e912
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1 ##=============================================================================
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2 ##
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3 ## vectors.S
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4 ##
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5 ## MIPS exception vectors
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6 ##
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7 ##=============================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Cygnus eCos Public License
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12 # Version 1.0 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://sourceware.cygnus.com/ecos
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Cygnus Operating System, released
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22 # September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Cygnus. Portions created
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25 # by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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26 # -------------------------------------------
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27 #
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28 #####COPYRIGHTEND####
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29 ##=============================================================================
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30 #######DESCRIPTIONBEGIN####
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31 ##
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32 ## Author(s): nickg
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33 ## Contributors: nickg
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34 ## Date: 1998-02-04
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35 ## Purpose: MIPS exception vectors
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36 ## Description: This file defines the code placed into the exception
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37 ## vectors. It also contains the first level default VSRs
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38 ## that save and restore state for both exceptions and
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39 ## interrupts.
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40 ##
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41 ######DESCRIPTIONEND####
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42 ##
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43 ##=============================================================================
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44
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45 # .file "vectors.S"
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46
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47 #include <pkgconf/system.h>
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48 #include <pkgconf/hal.h>
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49
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50 #ifdef CYGPKG_KERNEL
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51 # include <pkgconf/kernel.h>
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52 #endif
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53
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54 #include <cyg/hal/mips.inc>
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55
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56 .extern cyg_instrument
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57
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58 ##-----------------------------------------------------------------------------
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59
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60 #define MAX_SAVE_REG 31
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61
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62 #if defined(CYG_HAL_STARTUP_RAM)
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63 # if defined(CYG_HAL_MIPS_SIM) || !defined(CYG_HAL_USE_ROM_MONITOR)
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64 # define INITIAL_SR 0x1000ff00 /* CP0 usable, Ints enabled */
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65 //#define INITIAL_SR 0x10000000 /* CP0 usable, Ints disabled */
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66 # else
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67 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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68 # endif
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69 #elif defined(CYG_HAL_STARTUP_ROM)
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70 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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71 #endif
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72
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73 ##-----------------------------------------------------------------------------
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74 ## Hardware supplied vectors
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75
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76 .set noreorder
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77 .set noat
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78
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79 .section ".reset_vector","ax"
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80
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81 # Reset vector at 0xBFC00000
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82
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83 .globl reset_vector
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84 reset_vector:
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85 la v0,_start # jump to start
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86 jr v0
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87 nop # (delay slot)
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88
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89 .section ".debug_vector","ax"
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90
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91 # Debug vector at 0xBFC00200
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92
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93 .globl debug_vector
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94 debug_vector:
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95 la k0,32
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96 la k1,hal_vsr_table # Get VSR table
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97 lw k1,32*4(k1) # load debug vector
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98 jr k1 # go there
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99 nop # (delay slot)
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100
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101 .section ".other_vector","ax"
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102
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103 # Common vector at 0x80000080 or 0xBFC00180
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104
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105 .globl other_vector
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106 other_vector:
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107 mfc0 k0,cause # K0 = exception cause
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108 nop
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109 andi k0,k0,0x7F # isolate exception code
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110 la k1,hal_vsr_table # address of VSR table
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111 add k1,k1,k0 # offset of VSR entry
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112 lw k1,0(k1) # k1 = pointer to VSR
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113 jr k1 # go there
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114 nop # (delay slot)
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115
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116 .section ".utlb_vector","ax"
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117
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118 .globl utlb_vector
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119 utlb_vector:
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120 la k0,33
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121 la k1,hal_vsr_table # Get VSR table
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122 lw k1,33*4(k1) # load utlb vector
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123 jr k1 # go there
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124 nop # (delay slot)
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125
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126
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127 ##-----------------------------------------------------------------------------
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128 ## Startup code
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129
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130 .text
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131
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132 .globl _start
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133 .ent _start
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134 _start:
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135 # init CPU registers
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136 mtc0 zero,cause # zero cause reg
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137 la v0,INITIAL_SR
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138 mtc0 v0,sr
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139 mfc0 v0,config
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140 nop
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141 .set at
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142 and v0,v0,0xffffffcf
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143 # la v0,0
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144 .set noat
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145 mtc0 v0,config
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146
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147
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148 # Initialize hardware
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149
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150 #ifdef CYG_HAL_MIPS_JMR3904
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151
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152 # These mappings need to be set up before we
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153 # can use the stack and make calls to other
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154 # functions
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155
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156 # SCS0,1 base addr of ISA & PCI
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157 la a0,0xffffe010
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158 la a1,0x20201410
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159 sw a1,0(a0)
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160
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161 la a0,0xffffe014
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162 la a1,0x0000fcfc
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163 sw a1,0(a0)
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164
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165 # ROM configuration
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166 la a0,0xffff9000
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167 la a1,0x1fc00400
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168 sw a1,0(a0)
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169
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170 # SRAM config
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171 la a0,0xffff9100
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172 la a1,0x00000000
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173 sw a1,0(a0)
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174
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175 la a0,0xfffff500
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176 la a1,0xff
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177 sb a1,0(a0)
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178 la a1,0
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179 sb a1,4(a0)
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180 #endif
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181
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182 # Load Global Pointer register.
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183 la gp,_gp
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184
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185 # load initial stack pointer
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186 la a0,__interrupt_stack
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187 move sp,a0
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188
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189 #if defined(CYG_HAL_STARTUP_ROM) || \
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190 (defined(CYG_HAL_STARTUP_RAM) && !defined(CYG_HAL_USE_ROM_MONITOR))
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191
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192 # If we are starting up from ROM, or we are starting in
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193 # RAM and NOT using a ROM monitor, initialize the VSR table.
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194
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195 la a0,__default_interrupt_vsr
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196 la a1,__default_exception_vsr
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197 la a3,hal_vsr_table
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198 sw a0,0(a3)
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199 sw a1,1*4(a3)
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200 sw a1,2*4(a3)
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201 sw a1,3*4(a3)
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202 sw a1,4*4(a3)
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203 sw a1,5*4(a3)
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204 sw a1,6*4(a3)
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205 sw a1,7*4(a3)
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206 sw a1,8*4(a3)
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207 sw a1,9*4(a3)
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208 sw a1,10*4(a3)
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209 sw a1,11*4(a3)
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210 sw a1,12*4(a3)
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211 sw a1,13*4(a3)
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212 sw a1,14*4(a3)
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213 sw a1,15*4(a3)
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214
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215 sw a1,32*4(a3)
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216 sw a1,33*4(a3)
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217
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218 #ifdef CYG_HAL_ROM_MONITOR
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219
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220 # Install vectors to debug read and write functions
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221
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222 .extern hal_diag_write_char
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223 .extern hal_diag_read_char
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224 .extern breakpoint
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225
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226 la a0,hal_diag_write_char
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227 sw a0,63*4(a3)
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228 la a1,hal_diag_read_char
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229 sw a1,62*4(a3)
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230 la a0,breakpoint
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231 sw a0,61*4(a3)
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232
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233 #endif
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234
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235 #endif
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236 #if defined(CYG_HAL_STARTUP_RAM) && defined(CYG_HAL_USE_ROM_MONITOR)
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237
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238 # initialize the VSR table
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239 # We only take control of the interrupt vector,
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240 # the rest are left to the ROM for now...
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241
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242 la a0,__default_interrupt_vsr
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243 la a3,hal_vsr_table
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244 sw a0,0(a3)
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245
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246 #endif
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247
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248 #ifdef CYG_HAL_STARTUP_ROM
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249 # Copy data from ROM to RAM
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250
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251 .extern hal_copy_data
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252 jal hal_copy_data
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253 nop
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254 #endif
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255
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256 # Zero BSS
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257
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258 .extern hal_zero_bss
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259 jal hal_zero_bss
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260 nop
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261
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262 # Call constructors
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263
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264 .extern cyg_hal_invoke_constructors
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265 jal cyg_hal_invoke_constructors
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266 nop
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267
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268 # Call cyg_start
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269
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270 .extern cyg_start
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271 jal cyg_start
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272 nop
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273
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274 9:
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275 j 9b # Loop if we return
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276 nop # (delay slot)
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277
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278 .end _start
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279
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280 ##-----------------------------------------------------------------------------
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281 ## Default exception VSR.
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282 ## Saves machine state and calls external handling code.
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283
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284 .globl __default_exception_vsr
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285 .ent __default_exception_vsr
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286 __default_exception_vsr:
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287
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288 # We enter here with all of the CPU state still
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289 # in its registers except:
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290 # K0 = vector index
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291 # K1 = address of this function
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292
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293 #ifdef CYG_HAL_ROM_MONITOR
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294 # Switch to interrupt stack to handle exception
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295 move k1,sp
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296 la sp,__interrupt_stack
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297 #endif
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298
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299 addi sp,sp,-mips_exception_decrement
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300 # space for registers + safety margin
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301
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302 sw k0,mipsreg_vector(sp) # store vector
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303
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304 .set noat
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305 # store GPRs
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306 sw $0,(mipsreg_regs+0*4)(sp)
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307 sw $1,(mipsreg_regs+1*4)(sp)
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308 sw $2,(mipsreg_regs+2*4)(sp)
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309 sw $3,(mipsreg_regs+3*4)(sp)
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310 sw $4,(mipsreg_regs+4*4)(sp)
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311 sw $5,(mipsreg_regs+5*4)(sp)
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312 sw $6,(mipsreg_regs+6*4)(sp)
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313 sw $7,(mipsreg_regs+7*4)(sp)
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314 sw $8,(mipsreg_regs+8*4)(sp)
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315 sw $9,(mipsreg_regs+9*4)(sp)
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316 sw $10,(mipsreg_regs+10*4)(sp)
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317 sw $11,(mipsreg_regs+11*4)(sp)
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318 sw $12,(mipsreg_regs+12*4)(sp)
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319 sw $13,(mipsreg_regs+13*4)(sp)
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320 sw $14,(mipsreg_regs+14*4)(sp)
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321 sw $15,(mipsreg_regs+15*4)(sp)
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322 sw $16,(mipsreg_regs+16*4)(sp)
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323 sw $17,(mipsreg_regs+17*4)(sp)
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324 sw $18,(mipsreg_regs+18*4)(sp)
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325 sw $19,(mipsreg_regs+19*4)(sp)
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326 sw $20,(mipsreg_regs+20*4)(sp)
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327 sw $21,(mipsreg_regs+21*4)(sp)
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328 sw $22,(mipsreg_regs+22*4)(sp)
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329 sw $23,(mipsreg_regs+23*4)(sp)
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330 sw $24,(mipsreg_regs+24*4)(sp)
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331 sw $25,(mipsreg_regs+25*4)(sp)
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332 # sw $26,(mipsreg_regs+26*4)(sp) # == K0
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333 # sw $27,(mipsreg_regs+27*4)(sp) # == K1
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334 sw $28,(mipsreg_regs+28*4)(sp) # == GP
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335 # sw $29,(mipsreg_regs+29*4)(sp) # == SP
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336 sw $30,(mipsreg_regs+30*4)(sp) # == FP
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337 sw $31,(mipsreg_regs+31*4)(sp) # == RA
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338
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339 mfhi a0
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340 mflo a1
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341 sw a0,mipsreg_hi(sp)
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342 sw a1,mipsreg_lo(sp)
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343
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344 #ifdef CYG_HAL_ROM_MONITOR
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345 # K1 contains original SP
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346 sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump
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347 #else
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348 # synthesize original SP value
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349 move a2,sp # a2 = sp
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350 addi a2,a2,mips_exception_decrement # a2 = original sp
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351 sw a2,(mipsreg_regs+29*4)(sp) # store in reg dump
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352 #endif
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353
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354 # save remaining machine state registers
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355 mfc0 t0,cause
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356 mfc0 t1,sr
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357 # mfc0 t2,cache
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358 mfc0 t3,badvr
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359 mfc0 t4,config
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360 mfc0 t5,prid
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361 mfc0 t6,epc
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362
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363 #ifndef CYG_HAL_MIPS_SIM
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364 mfc0 t2,cache
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365 #endif
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366
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367 sw t0,mipsreg_cause(sp)
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368 sw t1,mipsreg_sr(sp)
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369 sw t2,mipsreg_cache(sp)
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370 sw t3,mipsreg_badvr(sp)
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371 sw t4,mipsreg_config(sp)
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372 sw t5,mipsreg_prid(sp)
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373 sw t6,mipsreg_pc(sp)
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374
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375
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376 # The machine state is now all saved on the stack.
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377
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378 # Load Global Pointer register.
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parents:
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379 la gp,_gp
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380
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381 move s0,sp # save pointer to saved state
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382
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383 addi sp,sp,-mips_stack_frame_size # make a null frame
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diff changeset
384
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diff changeset
385 # Need to set up back pointers etc. ???
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386
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387 la ra,restore_state # load return address
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388
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389 .extern exception_handler
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390 j exception_handler # call C code
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391 move a0,s0 # arg0 = register dump (delay slot)
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392
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393 # When the exception handler returns, it will
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394 # go back to restore_state, below.
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395
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396 .end __default_exception_vsr
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397
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398 ##------------------------------------------------------------------------------
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399 ## Default interrupt VSR.
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400 ## Saves machine state and calls appropriate ISR. When done, calls
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401 ## interrupt_end() to finish up and possibly reschedule.
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402
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403 .globl __default_interrupt_vsr
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404 .ent __default_interrupt_vsr
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405 __default_interrupt_vsr:
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406
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407
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408 # We enter here with all of the CPU state still
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409 # in its registers except:
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410 # K0 = vector index
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411 # K1 = address of this function
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412
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413 addi sp,sp,-mips_exception_decrement
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414 # space for registers + safety margin
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415
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416 sw k0,mipsreg_vector(sp) # store vector
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417
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418 # store GPRs
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419 sw $0,(mipsreg_regs+0*4)(sp)
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420 sw $1,(mipsreg_regs+1*4)(sp)
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421 sw $2,(mipsreg_regs+2*4)(sp)
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422 sw $3,(mipsreg_regs+3*4)(sp)
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423 sw $4,(mipsreg_regs+4*4)(sp)
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424 sw $5,(mipsreg_regs+5*4)(sp)
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425 sw $6,(mipsreg_regs+6*4)(sp)
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426 sw $7,(mipsreg_regs+7*4)(sp)
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427 sw $8,(mipsreg_regs+8*4)(sp)
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428 sw $9,(mipsreg_regs+9*4)(sp)
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429 sw $10,(mipsreg_regs+10*4)(sp)
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430 sw $11,(mipsreg_regs+11*4)(sp)
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431 sw $12,(mipsreg_regs+12*4)(sp)
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432 sw $13,(mipsreg_regs+13*4)(sp)
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433 sw $14,(mipsreg_regs+14*4)(sp)
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434 sw $15,(mipsreg_regs+15*4)(sp)
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435 sw $16,(mipsreg_regs+16*4)(sp)
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436 sw $17,(mipsreg_regs+17*4)(sp)
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437 sw $18,(mipsreg_regs+18*4)(sp)
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438 sw $19,(mipsreg_regs+19*4)(sp)
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439 sw $20,(mipsreg_regs+20*4)(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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440 sw $21,(mipsreg_regs+21*4)(sp)
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441 sw $22,(mipsreg_regs+22*4)(sp)
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diff changeset
442 sw $23,(mipsreg_regs+23*4)(sp)
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443 sw $24,(mipsreg_regs+24*4)(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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444 sw $25,(mipsreg_regs+25*4)(sp)
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445 # sw $26,(mipsreg_regs+26*4)(sp) # == K0
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446 # sw $27,(mipsreg_regs+27*4)(sp) # == K1
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447 sw $28,(mipsreg_regs+28*4)(sp) # == GP
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448 # sw $29,(mipsreg_regs+29*4)(sp) # == SP
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449 sw $30,(mipsreg_regs+30*4)(sp) # == FP
3111d98ba7b3 Initial commit of eCos version 1.1
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450 sw $31,(mipsreg_regs+31*4)(sp) # == RA
3111d98ba7b3 Initial commit of eCos version 1.1
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451
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452 mfhi a0
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diff changeset
453 mflo a1
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
454 sw a0,mipsreg_hi(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
455 sw a1,mipsreg_lo(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
456
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457 # synthesize original SP value
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diff changeset
458 move a2,sp # a2 = sp
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diff changeset
459 addi a2,a2,mips_exception_decrement # a2 = original sp
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
460 sw a2,(mipsreg_regs+29*4)(sp) # store in reg dump
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
461
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
462 mfc0 t1,sr
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
463 mfc0 t3,epc
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
464
3111d98ba7b3 Initial commit of eCos version 1.1
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465 #ifndef CYG_HAL_MIPS_SIM
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466 mfc0 t2,cache
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467 #endif
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diff changeset
468 sw t1,mipsreg_sr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
469 sw t2,mipsreg_cache(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
470 sw t3,mipsreg_pc(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
471
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diff changeset
472 # The machine state is now all saved on the stack.
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diff changeset
473
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diff changeset
474 # Load Global Pointer register.
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diff changeset
475 la gp,_gp
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diff changeset
476
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477 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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478 .extern _18Cyg_Scheduler_Base$sched_lock
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diff changeset
479 la v0,_18Cyg_Scheduler_Base$sched_lock
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
480 lw a0,0(v0)
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
481 addi a0,a0,1
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
482 sw a0,0(v0)
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
483 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
484
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
485 move s0,sp # save pointer to saved state
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
486
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
487 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
488
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
489 la a0,__interrupt_stack # a0 = stack top
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
490 la a1,__interrupt_stack_base # a1 = stack base
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
491 sub a3,sp,a1 # a3 = sp - base
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
492 bltz a3,1f # if < 0 - not on istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
493 nop # delay slot
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
494 sub t0,a0,sp # t0 = top - sp
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
495 bgtz t0,8f # if > 0 - already on istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
496 nop # delay slot
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
497 1:
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
498 move sp,a0 # switch to istack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
499 8:
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
500 addi sp,sp,-4 # space for old SP
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
501 sw s0,0(sp) # save old SP on stack
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
502
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
503 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
504
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
505 subu sp,sp,mips_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
506
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
507 # Need to set up back pointers etc. ???
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parents:
diff changeset
508
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
509 # Decode external interrupt via interrupt controller
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
510
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
511 mfc0 a1,cause # get cause register
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
512 nop
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
513 srl a1,a1,10 # shift IP bits to ls bits
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
514 andi a1,a1,0x7F # isolate IP bits
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
515 la t0,interrupt_translation_table # address of translation table
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
516 add t0,t0,a1 # offset of index byte
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
517 lb s2,0(t0) # load it
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
518
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
519 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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jlarmour
parents:
diff changeset
520 move s1,zero # Just vector zero is supported
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jlarmour
parents:
diff changeset
521 #else
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
522 move s1,s2 # Vector == interrupt number
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parents:
diff changeset
523 #endif
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parents:
diff changeset
524
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
525 # Here s1 is the number of the vector to be called and s2 is
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
526 # the number of the interrupt being serviced.
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
527
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
528 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
529
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
530 # Call cyg_instrument to record that this interrupt is being raised.
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
531
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
532 li a0,0x0301 # a0 = type = INTR,RAISE
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
533 move a1,s1 # a1 = vector number
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
534 jal cyg_instrument # call instrument function
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
535 xor a2,a2,a2 # arg2 = 0 (delay slot)
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
536 #endif
3111d98ba7b3 Initial commit of eCos version 1.1
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parents:
diff changeset
537
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
538 sll s1,s1,2 # s1 = byte offset of vector
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
539
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
540 la t2,hal_interrupt_handlers # handler table
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
541 add t2,t2,s1 # address of ISR ptr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
542 lw t2,0(t2) # ISR pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
543
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
544 la a1,hal_interrupt_data # data table
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
545 add a1,a1,s1 # address of data ptr
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
546 lw a1,0(a1) # Data pointer
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
547
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
548 move a0,s2 # pass interrupt number
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
549
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
550 jalr t2 # call ISR via t2
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
551 nop # (delay slot)
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
552
3111d98ba7b3 Initial commit of eCos version 1.1
jlarmour
parents:
diff changeset
553 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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554
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diff changeset
555 # If we are returning from the last nested interrupt, move back
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
556 # to the thread stack. interrupt_end() must be called on the
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diff changeset
557 # thread stack since it potentially causes a context switch.
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diff changeset
558 # Since we have arranged for the top of stack location to
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diff changeset
559 # contain the sp we need to go back to here, just pop it off
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diff changeset
560 # and put it in SP.
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561
3111d98ba7b3 Initial commit of eCos version 1.1
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562
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
563 lw sp,mips_stack_frame_size(sp) # sp = *sp
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diff changeset
564 subu sp,sp,mips_stack_frame_size # make a null frame
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diff changeset
565 #endif
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566
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diff changeset
567 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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568
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diff changeset
569 # We only need to call _interrupt_end() when there is a kernel
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570 # present to do any tidying up.
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571
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572 # On return v0 bit 1 will indicate whether a DSR is
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573 # to be posted. Pass this together with a pointer to
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574 # the interrupt object we have just used to the
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diff changeset
575 # interrupt tidy up routine.
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576
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577 # Note that s0, s1 and s2 are defined to be preserved across
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578 # calls by the calling convention, so they still contain
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579 # the register dump, the vector offset and the interrupt number
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580 # respectively.
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581
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582 move a0,v0 # put ISR result in arg0
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583
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584 la a1,hal_interrupt_objects # interrupt object table
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585 add a1,a1,s1 # address of object ptr
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586 lw a1,0(a1) # a1 = object ptr
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587
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588 move a2,s0 # arg3 = saved register dump
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589
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590 # interrupt_end() must be called with interrupts enabled.
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591
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592 rfe # restore previous status bits
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593 # this may enable interrupts
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594
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595 .extern interrupt_end
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596 jal interrupt_end # call into C to finish off
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597 nop # (delay slot)
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598
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599 #endif
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600
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601 restore_state:
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602
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603 # All done, restore CPU state and continue
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604
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605 addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr
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606
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607 # Load status register and cache control register.
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diff changeset
608 # This will put the interrupt, mode and cache control
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609 # bits back to their post-exception values, so we will
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610 # need to do another RFE before we finish.
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611
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612 lw t1,mipsreg_sr(sp)
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diff changeset
613 lw t2,mipsreg_cache(sp)
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614
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615 mtc0 t1,sr
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616 #ifndef CYG_HAL_MIPS_SIM
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617 mtc0 t2,cache
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618 #endif
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619
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620 lw a0,mipsreg_hi(sp)
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diff changeset
621 lw a1,mipsreg_lo(sp)
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622 mthi a0
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diff changeset
623 mtlo a1
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624
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625 # load GPRs
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626 # lw $0,(mipsreg_regs+0*4)(sp)
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627 lw $1,(mipsreg_regs+1*4)(sp)
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628 lw $2,(mipsreg_regs+2*4)(sp)
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629 lw $3,(mipsreg_regs+3*4)(sp)
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630 lw $4,(mipsreg_regs+4*4)(sp)
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631 lw $5,(mipsreg_regs+5*4)(sp)
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632 lw $6,(mipsreg_regs+6*4)(sp)
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633 lw $7,(mipsreg_regs+7*4)(sp)
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634 lw $8,(mipsreg_regs+8*4)(sp)
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635 lw $9,(mipsreg_regs+9*4)(sp)
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636 lw $10,(mipsreg_regs+10*4)(sp)
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637 lw $11,(mipsreg_regs+11*4)(sp)
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638 lw $12,(mipsreg_regs+12*4)(sp)
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639 lw $13,(mipsreg_regs+13*4)(sp)
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640 lw $14,(mipsreg_regs+14*4)(sp)
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641 lw $15,(mipsreg_regs+15*4)(sp)
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642 lw $16,(mipsreg_regs+16*4)(sp)
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diff changeset
643 lw $17,(mipsreg_regs+17*4)(sp)
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644 lw $18,(mipsreg_regs+18*4)(sp)
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645 lw $19,(mipsreg_regs+19*4)(sp)
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646 lw $20,(mipsreg_regs+20*4)(sp)
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647 lw $21,(mipsreg_regs+21*4)(sp)
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648 lw $22,(mipsreg_regs+22*4)(sp)
3111d98ba7b3 Initial commit of eCos version 1.1
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649 lw $23,(mipsreg_regs+23*4)(sp)
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650 lw $24,(mipsreg_regs+24*4)(sp)
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651 lw $25,(mipsreg_regs+25*4)(sp)
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652 # lw $26,(mipsreg_regs+26*4)(sp) # == K0
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diff changeset
653 # lw $27,(mipsreg_regs+27*4)(sp) # == K1
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654 lw $28,(mipsreg_regs+28*4)(sp) # == GP
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655 # lw $29,(mipsreg_regs+29*4)(sp) # == SP
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656 lw $30,(mipsreg_regs+30*4)(sp) # == FP
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diff changeset
657 lw $31,(mipsreg_regs+31*4)(sp) # == RA
3111d98ba7b3 Initial commit of eCos version 1.1
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diff changeset
658
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diff changeset
659 lw k0,mipsreg_pc(sp) # K0 = return PC
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660 lw sp,(mipsreg_regs+29*4)(sp) # load SP
3111d98ba7b3 Initial commit of eCos version 1.1
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661 sync
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662 jr k0 # jump back to interrupted code
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663 rfe # restore state (delay slot)
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diff changeset
664
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665 .end __default_interrupt_vsr
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666
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667 # This table translates from the 6 bit value supplied in the IP bits
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diff changeset
668 # of the cause register into a 0..16 offset into the ISR tables.
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diff changeset
669 interrupt_translation_table:
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670 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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671 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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672 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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673 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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674
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675 ##-----------------------------------------------------------------------------
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676 ## Interrupt Stack.
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677 ## Used during intialization and for executing ISRs.
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678
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679 .bss
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680
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681 .balign 16
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682 __interrupt_stack_base:
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683 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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684 .byte 0
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685 .endr
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686 .balign 16
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687 __interrupt_stack:
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688
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689 .long 0,0,0,0,0,0,0,0
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690
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691 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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692
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693 .globl idle_thread_stack
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694 idle_thread_stack:
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695 .rept CYGNUM_KERNEL_THREADS_IDLE_STACK_SIZE
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696 .byte 0
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697 .endr
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698
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699 #endif
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700
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701 ##-----------------------------------------------------------------------------
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702 ## VSR table.
3111d98ba7b3 Initial commit of eCos version 1.1
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703 ## The main interrupt code indirects through here to find the VSR
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diff changeset
704 ## to execute for each architecture defined interrupt.
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705 ## This is only used for simulated targets, on real targets a fixed location VSR
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706 ## table is now allocated at 0x80000100.
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707
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708 #if defined(CYG_HAL_MIPS_SIM) || \
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709 ( defined(CYG_HAL_MIPS_TX3904) && \
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710 defined(CYG_HAL_STARTUP_RAM) && \
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711 !defined(CYG_HAL_USE_ROM_MONITOR) \
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712 )
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713 .section ".vsr_table","a"
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714
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715 .globl hal_vsr_table
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716
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717 hal_vsr_table:
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718 .long __default_interrupt_vsr
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diff changeset
719 .rept 63
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720 .long __default_exception_vsr
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diff changeset
721 .endr
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722
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723 #endif
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724
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725 #------------------------------------------------------------------------------
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diff changeset
726 # Interrupt vector tables.
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727 # These tables contain the isr, data and object pointers used to deliver
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diff changeset
728 # interrupts to user code.
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729 # hal_interrupt_level contains the interrupt level set by
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730 # HAL_INTERRUPT_CONFIGURE().
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731
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732
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733 .extern hal_default_isr
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734
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735 .data
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736
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737 .globl hal_interrupt_handlers
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738 hal_interrupt_handlers:
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739 .long hal_default_isr
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740 .long hal_default_isr
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741 .long hal_default_isr
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742 .long hal_default_isr
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743 .long hal_default_isr
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744 .long hal_default_isr
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745 .long hal_default_isr
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746 .long hal_default_isr
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747 .long hal_default_isr
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748 .long hal_default_isr
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749 .long hal_default_isr
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750 .long hal_default_isr
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751 .long hal_default_isr
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752 .long hal_default_isr
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753 .long hal_default_isr
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754 .long hal_default_isr
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755 .long hal_default_isr
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756
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757 .globl hal_interrupt_data
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758 hal_interrupt_data:
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759 .rept 17
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760 .long 0
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761 .endr
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762
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763 .globl hal_interrupt_objects
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764 hal_interrupt_objects:
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765 .rept 17
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766 .long 0
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767 .endr
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768
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769 .globl hal_interrupt_level
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770 hal_interrupt_level:
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771 .rept 17
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772 .byte 7
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773 .endr
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774
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775 ##-----------------------------------------------------------------------------
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776 ## end of vectors.S