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1 /*========================================================================== |
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2 // |
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3 // sim.ld |
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4 // |
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5 // Linker script for MIPS simulator |
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6 // |
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7 //========================================================================== |
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8 //####COPYRIGHTBEGIN#### |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Cygnus eCos Public License |
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12 // Version 1.0 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://sourceware.cygnus.com/ecos |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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22 // September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Cygnus. Portions created |
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25 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved. |
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26 // ------------------------------------------- |
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27 // |
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28 //####COPYRIGHTEND#### |
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29 //========================================================================== |
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30 //#####DESCRIPTIONBEGIN#### |
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31 // |
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32 // Author(s): nickg |
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33 // Contributors: nickg |
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34 // Date: 1998-02-17 |
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35 // Purpose: MIPS simulator Linker script |
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36 // Description: This script is passed to the linker to define the memory |
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37 // of the MIPS simulator. |
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38 // |
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39 //####DESCRIPTIONEND#### |
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40 // |
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41 //========================================================================*/ |
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42 |
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43 STARTUP(vectors.o) |
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44 ENTRY(reset_vector) |
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45 |
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46 GROUP(libtarget.a libgcc.a) |
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47 |
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48 #include <pkgconf/hal.h> |
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49 |
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50 #if defined(CYG_HAL_STARTUP_RAM) |
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51 #define LOAD_BASE 0x80000000 |
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52 #define DATA_BASE |
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53 #define AT(x) |
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54 #elif defined(CYG_HAL_STARTUP_ROM) |
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55 #define LOAD_BASE 0xBFC00000 |
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56 #define DATA_BASE 0x80000200 |
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57 #endif |
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58 |
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59 /* |
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60 * Allocate the stack to be at the top of memory, since the stack |
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61 * grows down |
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62 */ |
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63 |
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64 /*__interrupt_stack = DATA_BASE + 0x00100000; */ |
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65 |
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66 SECTIONS |
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67 { |
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68 /*------------------------------------------------------------*/ |
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69 |
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70 /* Start of ROM */ |
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71 . = LOAD_BASE; |
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72 |
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73 .rom_vectors : |
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74 { |
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75 #if defined(CYG_HAL_STARTUP_RAM) |
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76 KEEP(*(.utlb_vector)) |
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77 . = ALIGN(0x80); |
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78 KEEP(*(.other_vector)) |
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79 /* debug and reset vector not used in RAM version */ |
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80 KEEP(*(.debug_vector)) |
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81 KEEP(*(.reset_vector)) |
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82 #elif defined(CYG_HAL_STARTUP_ROM) |
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83 KEEP(*(.reset_vector)) |
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84 . = ALIGN(0x100); |
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85 KEEP(*(.utlb_vector)) |
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86 . = ALIGN(0x80); |
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87 KEEP(*(.debug_vector)) |
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88 . = ALIGN(0x100); |
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89 KEEP(*(.other_vector)) |
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90 #endif |
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91 } |
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92 |
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93 /*------------------------------------------------------------*/ |
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94 |
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95 .text : |
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96 { |
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97 _stext = .; |
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98 #ifndef CYG_KERNEL_USE_INIT_PRIORITY |
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99 __sched_text_start = .; |
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100 *sched.o(.text*) |
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101 __sched_text_end = .; |
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102 __clock_text_start = .; |
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103 *clock.o(.text*) |
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104 __clock_text_end = .; |
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105 __thread_text_start = .; |
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106 *thread.o(.text*) |
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107 __thread_text_end = .; |
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108 #endif |
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109 *(.text*) |
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110 *(.gnu.warning) |
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111 *(.gnu.linkonce*) |
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112 *(.init) |
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113 |
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114 } |
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115 _etext = .; |
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116 PROVIDE (etext = .); |
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117 .fini : { *(.fini) } |
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118 .rodata : { *(.rodata*) } |
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119 .rodata1 : { *(.rodata1) } |
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120 .fixup : { *(.fixup) } |
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121 .gcc_except_table : { *(.gcc_except_table) } |
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122 |
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123 /*------------------------------------------------------------*/ |
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124 |
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125 /* __rom_data_start = __rom_ram_vectors_start + SIZEOF( .ram_vectors ); */ |
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126 __rom_data_start = ALIGN(8); |
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127 .data DATA_BASE : |
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128 { |
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129 __ram_data_start = .; |
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130 *(.data*) |
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131 *(.data1) |
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132 _GOT1_START_ = .; |
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133 *(.got1) |
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134 _GOT1_END_ = .; |
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135 /* Put .ctors and .dtors next to the .got2 section, so that the pointers |
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136 get relocated with -mrelocatable. */ |
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137 _GOT2_START_ = .; |
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138 *(.got2) |
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139 #ifdef CYG_KERNEL_USE_INIT_PRIORITY |
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140 SORT(CONSTRUCTORS) |
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141 *(.ctors*) |
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142 *(.dtors*) |
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143 #else |
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144 CONSTRUCTORS |
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145 *(.ctors*) |
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146 *(.dtors*) |
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147 #endif |
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148 _GOT2_END_ = .; |
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149 . = ALIGN(8); |
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150 _gp = .; |
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151 __global = _gp; |
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152 _GLOBAL_OFFSET_TABLE_ = .; |
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153 _GOT_START_ = .; |
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154 _SDA_BASE_ = .; |
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155 *(.got.plt) |
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156 *(.got) |
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157 _GOT_END_ = .; |
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158 *(.dynamic) |
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159 /* We want the small data sections together, so single-instruction offsets |
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160 can access them all, and initialized data all before uninitialized, so |
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161 we can shorten the on-disk segment size. */ |
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162 *(.sdata*) |
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163 *(.sbss*) |
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164 } |
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165 __ram_data_end = .; |
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166 PROVIDE( __ram_data_end = .); |
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167 _edata = .; |
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168 PROVIDE (edata = .); |
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169 |
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170 /*------------------------------------------------------------*/ |
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171 |
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172 . = ALIGN(4); |
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173 __bss_start = .; |
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174 .bss : |
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175 { |
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176 *(.scommon) |
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177 *(.dynbss) |
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178 *(.bss) |
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179 *(COMMON) |
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180 } |
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181 . = ALIGN(4); |
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182 _end = . ; |
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183 PROVIDE (end = .); |
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184 |
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185 /*------------------------------------------------------------*/ |
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186 /* DWARF debug sections. |
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187 Symbols in the DWARF debugging sections are relative to |
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188 the beginning of the section so we begin them at 0. */ |
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189 |
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190 /* DWARF 1 */ |
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191 .debug 0 : { *(.debug) } |
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192 .line 0 : { *(.line) } |
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193 |
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194 /* GNU DWARF 1 extensions */ |
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195 .debug_srcinfo 0 : { *(.debug_srcinfo) } |
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196 .debug_sfnames 0 : { *(.debug_sfnames) } |
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197 |
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198 /* DWARF 1.1 and DWARF 2 */ |
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199 .debug_aranges 0 : { *(.debug_aranges) } |
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200 .debug_pubnames 0 : { *(.debug_pubnames) } |
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201 |
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202 /* DWARF 2 */ |
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203 .debug_info 0 : { *(.debug_info) } |
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204 .debug_abbrev 0 : { *(.debug_abbrev) } |
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205 .debug_line 0 : { *(.debug_line) } |
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206 .debug_frame 0 : { *(.debug_frame) } |
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207 .debug_str 0 : { *(.debug_str) } |
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208 .debug_loc 0 : { *(.debug_loc) } |
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209 .debug_macinfo 0 : { *(.debug_macinfo) } |
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210 |
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211 /* SGI/MIPS DWARF 2 extensions */ |
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212 .debug_weaknames 0 : { *(.debug_weaknames) } |
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213 .debug_funcnames 0 : { *(.debug_funcnames) } |
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214 .debug_typenames 0 : { *(.debug_typenames) } |
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215 .debug_varnames 0 : { *(.debug_varnames) } |
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216 |
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217 } |
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218 |
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219 //hal_vsr_table = 0x80000100; |
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220 |
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221 // End of sim.ld |
