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annotate packages/hal/mn10300/arch/current/include/hal_cache.h @ 0:3111d98ba7b3 ecos-v1_1-release

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Initial commit of eCos version 1.1
author jlarmour
date Tue, 11 May 1999 11:16:07 +0000
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children 443894e2e912
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Cygnus eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released
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25 // September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Cygnus. Portions created
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28 // by Cygnus are Copyright (C) 1998 Cygnus Solutions. All Rights Reserved.
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29 // -------------------------------------------
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30 //
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31 //####COPYRIGHTEND####
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32 //=============================================================================
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33 //#####DESCRIPTIONBEGIN####
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34 //
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35 // Author(s): nickg
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36 // Contributors: nickg
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37 // Date: 1998-02-17
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38 // Purpose: Cache control API
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39 // Description: The macros defined here provide the HAL APIs for handling
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40 // cache control operations.
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41 // Usage:
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42 // #include <cyg/hal/hal_cache.h>
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43 // ...
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44 //
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45 //
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <cyg/infra/cyg_type.h>
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51
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52 //=============================================================================
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53 // MN10300 Simulator
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54
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55 #if defined(CYG_HAL_MN10300_SIM)
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56
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57 //-----------------------------------------------------------------------------
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58 // Cache dimensions
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59
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60 // Data cache
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61 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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62 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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63 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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64
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65 // Instruction cache
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66 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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67 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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68 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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69
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70 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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71 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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72
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73 //-----------------------------------------------------------------------------
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74 // Global control of data cache
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75
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76 // Enable the data cache
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77 #define HAL_DCACHE_ENABLE()
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78
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79 // Disable the data cache
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80 #define HAL_DCACHE_DISABLE()
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81
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82 // Invalidate the entire cache
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83 #define HAL_DCACHE_INVALIDATE_ALL()
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84
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85 // Synchronize the contents of the cache with memory.
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86 #define HAL_DCACHE_SYNC()
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87
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88 // Set the data cache refill burst size
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89 //#define HAL_DCACHE_BURST_SIZE(_size_)
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90
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91 // Set the data cache write mode
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92 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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93
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94 // Load the contents of the given address range into the data cache
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95 // and then lock the cache so that it stays there.
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96 //#define HAL_DCACHE_LOCK(_base_, _size_)
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97
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98 // Undo a previous lock operation
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99 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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100
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101 //-----------------------------------------------------------------------------
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102 // Data cache line control
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103
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104 // Allocate cache lines for the given address range without reading its
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105 // contents from memory.
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106 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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107
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108 // Write dirty cache lines to memory and invalidate the cache entries
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109 // for the given address range.
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110 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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111
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112 // Invalidate cache lines in the given range without writing to memory.
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113 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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114
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115 // Write dirty cache lines to memory for the given address range.
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116 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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117
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118 // Preread the given range into the cache with the intention of reading
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119 // from it later.
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120 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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121
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122 // Preread the given range into the cache with the intention of writing
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123 // to it later.
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124 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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125
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126 // Allocate and zero the cache lines associated with the given range.
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127 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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128
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129 //-----------------------------------------------------------------------------
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130 // Global control of Instruction cache
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131
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132 // Enable the instruction cache
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133 #define HAL_ICACHE_ENABLE()
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134
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135 // Disable the instruction cache
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136 #define HAL_ICACHE_DISABLE()
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137
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138 // Invalidate the entire cache
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139 #define HAL_ICACHE_INVALIDATE_ALL()
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140
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141 // Synchronize the contents of the cache with memory.
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142 #define HAL_ICACHE_SYNC()
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143
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144 // Set the instruction cache refill burst size
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145 //#define HAL_ICACHE_BURST_SIZE(_size_)
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146
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147 // Load the contents of the given address range into the instruction cache
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148 // and then lock the cache so that it stays there.
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149 //#define HAL_ICACHE_LOCK(_base_, _size_)
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150
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151 // Undo a previous lock operation
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152 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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153
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154 //-----------------------------------------------------------------------------
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155 // Instruction cache line control
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156
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157 // Invalidate cache lines in the given range without writing to memory.
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158 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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159
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160 #endif
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161
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162
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163 //=============================================================================
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164 // MN103002 implementation
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165
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166 #if !defined(CYG_HAL_MN10300_SIM) && defined(CYG_HAL_MN10300_MN103002)
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167
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168 //-----------------------------------------------------------------------------
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169 // Cache dimensions
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170
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171
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172 // Data cache
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173 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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174 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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175 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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176
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177 // Instruction cache
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178 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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179 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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180 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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181
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182 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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183 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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184
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185 //-----------------------------------------------------------------------------
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186 // Control registers
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187
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188 #define HAL_CHCTR ((CYG_ADDRWORD *)0x20000070)
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189
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190 #define HAL_CHCTR_ICEN 0x0001
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191 #define HAL_CHCTR_DCEN 0x0002
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192 #define HAL_CHCTR_ICBUSY 0x0004
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193 #define HAL_CHCTR_DCBUSY 0x0008
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194 #define HAL_CHCTR_ICINV 0x0010
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195 #define HAL_CHCTR_DCINV 0x0020
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196 #define HAL_CHCTR_DCWTMD 0x0040
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197 #define HAL_CHCTR_ICWMD 0x0300
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198 #define HAL_CHCTR_DCWMD 0x3000
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199
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200 #define HAL_DCACHE_PURGE_WAY0 ((CYG_ADDRWORD *)0x28400000)
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201 #define HAL_DCACHE_PURGE_WAY1 ((CYG_ADDRWORD *)0x28401000)
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202
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203 //-----------------------------------------------------------------------------
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204 // Global control of data cache
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205
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206 // Enable the data cache
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207 #define HAL_DCACHE_ENABLE() \
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208 { \
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209 CYG_ADDRWORD chctr = *HAL_CHCTR; \
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210 chctr |= HAL_CHCTR_DCEN; \
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211 *HAL_CHCTR = chctr; \
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212 }
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213
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214 // Disable the data cache
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215 #define HAL_DCACHE_DISABLE() \
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216 { \
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217 CYG_ADDRWORD chctr = *HAL_CHCTR; \
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218 chctr &= ~HAL_CHCTR_DCEN; \
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219 *HAL_CHCTR = chctr; \
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220 }
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221
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222 // Invalidate the entire cache
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223 #define HAL_DCACHE_INVALIDATE_ALL() \
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224 { \
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225 CYG_ADDRWORD chctr, chctr1; \
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226 chctr1 = *HAL_CHCTR; \
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227 HAL_DCACHE_DISABLE(); \
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228 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \
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229 chctr = *HAL_CHCTR; \
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230 chctr |= HAL_CHCTR_DCINV; \
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231 *HAL_CHCTR = chctr; \
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232 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \
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233 *HAL_CHCTR = chctr1; \
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234 }
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235
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236 // Synchronize the contents of the cache with memory.
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237 #define HAL_DCACHE_SYNC()
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238
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239 // Set the data cache refill burst size
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240 //#define HAL_DCACHE_BURST_SIZE(_size_)
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241
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242 // Set the data cache write mode
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243 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
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244 { \
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245 CYG_ADDRWORD chctr; \
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246 chctr = *HAL_CHCTR; \
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247 HAL_DCACHE_DISABLE(); \
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248 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \
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249 chctr |= HAL_CHCTR_DCWTMD*(_mode_); \
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250 *HAL_CHCTR = chctr; \
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251 }
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252
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253 #define HAL_DCACHE_WRITEBACK_MODE 0
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254 #define HAL_DCACHE_WRITETHRU_MODE 1
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255
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256 // Load the contents of the given address range into the data cache
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257 // and then lock the cache so that it stays there.
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258 //#define HAL_DCACHE_LOCK(_base_, _size_)
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259
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260 // Undo a previous lock operation
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261 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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262
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263 //-----------------------------------------------------------------------------
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264 // Data cache line control
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265
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266 // Allocate cache lines for the given address range without reading its
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267 // contents from memory.
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268 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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269
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270 // Write dirty cache lines to memory and invalidate the cache entries
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271 // for the given address range.
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272 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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273
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274 // Invalidate cache lines in the given range without writing to memory.
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275 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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276
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277 // Write dirty cache lines to memory for the given address range.
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278 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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279 { \
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280 volatile CYG_ADDRWORD *way0 = HAL_DCACHE_PURGE_WAY0; \
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281 volatile CYG_ADDRWORD *way1 = HAL_DCACHE_PURGE_WAY1; \
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282 int i; \
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283 CYG_ADDRWORD chctr; \
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284 chctr = *HAL_CHCTR; \
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285 HAL_DCACHE_DISABLE(); \
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286 while( *HAL_CHCTR & HAL_CHCTR_DCBUSY ); \
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287 \
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288 way0 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \
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289 way1 += ((CYG_ADDRWORD)_base_) & 0x000007f0; \
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290 for( i = 0; i < _size_ ; i += HAL_DCACHE_LINE_SIZE ) \
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291 { \
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292 *way0 = 0; \
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293 *way1 = 0; \
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294 way0 += HAL_DCACHE_LINE_SIZE; \
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295 way1 += HAL_DCACHE_LINE_SIZE; \
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296 } \
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297 *HAL_CHCTR = chctr; \
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298 }
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299
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300 // Preread the given range into the cache with the intention of reading
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301 // from it later.
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302 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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303
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304 // Preread the given range into the cache with the intention of writing
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305 // to it later.
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306 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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307
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308 // Allocate and zero the cache lines associated with the given range.
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309 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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310
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311 //-----------------------------------------------------------------------------
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312 // Global control of Instruction cache
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313
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314 // Enable the instruction cache
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315 #define HAL_ICACHE_ENABLE() \
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316 { \
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317 CYG_ADDRWORD chctr = *HAL_CHCTR; \
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318 chctr |= HAL_CHCTR_ICEN; \
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319 *HAL_CHCTR = chctr; \
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320 }
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321
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322 // Disable the instruction cache
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323 #define HAL_ICACHE_DISABLE() \
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324 { \
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325 CYG_ADDRWORD chctr = *HAL_CHCTR; \
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326 chctr &= ~HAL_CHCTR_ICEN; \
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327 *HAL_CHCTR = chctr; \
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328 }
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329
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330 // Invalidate the entire cache
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331 #define HAL_ICACHE_INVALIDATE_ALL() \
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332 { \
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333 CYG_ADDRWORD chctr, chctr1; \
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334 chctr1 = *HAL_CHCTR; \
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335 HAL_ICACHE_DISABLE(); \
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336 while( *HAL_CHCTR & HAL_CHCTR_ICBUSY ); \
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337 chctr = *HAL_CHCTR; \
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338 chctr |= HAL_CHCTR_ICINV; \
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339 *HAL_CHCTR = chctr; \
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340 while( *HAL_CHCTR & HAL_CHCTR_ICBUSY ); \
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341 *HAL_CHCTR = chctr1; \
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342 }
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343
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344 // Synchronize the contents of the cache with memory.
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345 #define HAL_ICACHE_SYNC()
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346
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347 // Set the instruction cache refill burst size
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348 //#define HAL_ICACHE_BURST_SIZE(_size_)
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349
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350 // Load the contents of the given address range into the instruction cache
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351 // and then lock the cache so that it stays there.
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352 //#define HAL_ICACHE_LOCK(_base_, _size_)
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353
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354 // Undo a previous lock operation
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355 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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356
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357 //-----------------------------------------------------------------------------
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358 // Instruction cache line control
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359
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360 // Invalidate cache lines in the given range without writing to memory.
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361 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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362
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363 #endif
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364
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365
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366 //-----------------------------------------------------------------------------
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367 #endif // ifndef CYGONCE_HAL_CACHE_H
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368 // End of hal_cache.h