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annotate packages/hal/arm/arch/current/src/context.S @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
parents bf00f99aec69
children 2085233a121a
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1 // #=============================================================================
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2 // #
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3 // # context.S
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4 // #
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5 // # ARM context switch code
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6 // #
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7 // #=============================================================================
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8 // ####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 // ####COPYRIGHTEND####
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31 // #=============================================================================
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32 // ######DESCRIPTIONBEGIN####
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33 // #
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34 // # Author(s): nickg, gthomas
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35 // # Contributors: nickg, gthomas
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36 // # Date: 1998-09-15
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37 // # Purpose: ARM context switch code
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38 // # Description: This file contains implementations of the thread context
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39 // # switch routines. It also contains the longjmp() and setjmp()
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40 // # routines.
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41 // #
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42 // #####DESCRIPTIONEND####
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43 // #
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44 // #=============================================================================
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45
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46 #include <pkgconf/hal.h>
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47
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48 #include "arm.inc"
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49
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50 .text
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51
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52 // ------------------------------------------------------------------------------
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53 // function declaration macro
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54
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55 #define FUNC_START(name) \
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56 .globl name; \
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57 name:
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58
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59 // ------------------------------------------------------------------------------
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60 // hal_thread_switch_context
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61 // Switch thread contexts
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62 // R0 = address of sp of next thread to execute
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63 // R1 = address of sp save location of current thread
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64
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65 // Need to save/restore R4..R12, R13 (sp), R14 (lr)
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66
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67 // Note: this is a little wasteful since r0..r3 don't need to be saved.
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68 // They are saved here though so that the information can match the HAL_SavedRegisters
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69
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70 #ifdef __thumb__
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71 .code 16
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72 .thumb_func
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73 #endif
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74 FUNC_START(hal_thread_switch_context)
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75 #ifdef __thumb__
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76 ldr r2,=hal_thread_switch_context_ARM
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77 bx r2
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78 .code 32
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79 FUNC_START(hal_thread_switch_context_ARM)
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80 #endif
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81 mov ip,sp // saved stack pointer
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82 stmfd sp!,{fp,ip,lr,pc} // filler
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83 stmfd sp!,{r0-r10,fp,ip,lr,pc}
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84 mrs r2,cpsr
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85 str r2,[sp,#armreg_cpsr]
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86 str sp,[r1] // return new stack pointer
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87 #ifdef __thumb__
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88 b hal_thread_load_context_ARM // skip mode switch stuff
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89 #endif
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90
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91 # Now load the destination thread by dropping through
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92 # to hal_thread_load_context
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93
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94 // ------------------------------------------------------------------------------
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95 // hal_thread_load_context
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96 // Load thread context
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97 // R0 = address of sp of next thread to execute
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98 // Note that this function is also the second half of hal_thread_switch_context
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99 // and is simply dropped into from it.
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100
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101 #ifdef __thumb__
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102 .code 16
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103 .thumb_func
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104 #endif
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105 FUNC_START(hal_thread_load_context)
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106 #ifdef __thumb__
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107 ldr r2,=hal_thread_load_context_ARM
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108 bx r2
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109 .code 32
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110 FUNC_START(hal_thread_load_context_ARM)
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111 #endif
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112 ldr fp,[r0] // get context to restore
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113 mrs r0,cpsr // disable IRQ's
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114 orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
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115 msr cpsr,r0
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116 ldr r0,[fp,#armreg_cpsr]
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117 msr spsr,r0
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118 ldmfd fp,{r0-r10,fp,sp,lr}
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119 #ifdef __thumb__
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120 mrs r1,spsr // r1 is scratch
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121 // [r0 holds initial thread arg]
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122 msr cpsr,r1 // hopefully no mode switch here!
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123 bx lr
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124 #else
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125 movs pc,lr // also restores saved PSR
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126 #endif
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127
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128 // ------------------------------------------------------------------------------
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129 // HAL longjmp, setjmp implementations
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130 // hal_setjmp saves only to callee save registers 4-14
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131 // and lr into buffer supplied in r0[arg0]
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132
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133 #ifdef __thumb__
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134 .code 16
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135 .thumb_func
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136 #endif
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137 FUNC_START(hal_setjmp)
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138 #ifdef __thumb__
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139 ldr r2,=hal_setjmp_ARM
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140 bx r2
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141 .code 32
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142 FUNC_START(hal_setjmp_ARM)
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143 #endif
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144 stmea r0,{r4-r14}
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145 mov r0,#0
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146 #ifdef __thumb__
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147 bx lr
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148 #else
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149 mov pc,lr; # return
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150 #endif
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151
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152 // hal_longjmp loads state from r0[arg0] and returns
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153
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154 #ifdef __thumb__
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155 .code 16
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156 .thumb_func
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157 #endif
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158 FUNC_START(hal_longjmp)
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159 #ifdef __thumb__
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160 ldr r2,=hal_longjmp_ARM
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161 bx r2
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162 .code 32
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163 FUNC_START(hal_longjmp_ARM)
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164 #endif
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165 ldmfd r0,{r4-r14}
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166 mov r0,r1; # return [arg1]
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167 #ifdef __thumb__
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168 bx lr
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169 #else
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170 mov pc,lr
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171 #endif
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172
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173 // ------------------------------------------------------------------------------
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174 // end of context.S
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175
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176