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annotate packages/hal/arm/ebsa285/current/include/plf_io.h @ 76:435cced73e2f ecos-v1_3_1-release

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eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
author jlarmour
date Tue, 28 Mar 2000 14:10:45 +0000
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children 6ed91473a1cd
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435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST
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1 #ifndef CYGONCE_PLF_IO_H
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2 #define CYGONCE_PLF_IO_H
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3
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4 //=============================================================================
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5 //
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6 // plf_io.h
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7 //
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8 // Platform specific IO support
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): hmt, jskov
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38 // Contributors: hmt, jskov
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39 // Date: 1999-08-09
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40 // Purpose: Intel EBSA285 PCI IO support macros
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41 // Description:
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42 // Usage: #include <cyg/hal/plf_io.h>
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43 //
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44 // Note: Based on information in
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45 // "21285 Core Logic for SA-110 Microprocessor"
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46 //####DESCRIPTIONEND####
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47 //
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48 //=============================================================================
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49
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50 #include <pkgconf/hal_arm_ebsa285.h>
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51
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52 #include <cyg/hal/hal_ebsa285.h>
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53
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54 #include <cyg/hal/hal_io.h> // IO macros
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55 #include <cyg/hal/hal_platform_ints.h> // Interrupt vectors
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56
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57 // The PCI resources required by the EBSA are hardcoded to the lowest
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58 // addresses in the PCI address space, thus:
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59 // PCI Memory Space
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60 #define EBSA_SDRAM_PCI_ADDR 0
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61 #define EBSA_SDRAM_PCI_SIZE (CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE)
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62 #define EBSA_CSR_MEM_PCI_ADDR (EBSA_SDRAM_PCI_SIZE)
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63 #define EBSA_CSR_MEM_PCI_SIZE 0x80
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64 // PCI IO Space
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65 #define EBSA_CSR_IO_PCI_ADDR 0
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66 #define EBSA_CSR_IO_PCI_SIZE 0x80
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67
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68 // Initialize the PCI bus.
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69 #define HAL_PCI_INIT() \
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70 CYG_MACRO_START \
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71 cyg_uint32 __tmp, __tmp2; \
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72 \
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73 /* Disable PCI Outbound interrupts */ \
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74 /* (according to 7-14 SA110_OUT_INT_MASK is not accessible */ \
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75 /* by SA-100) */ \
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76 HAL_WRITE_UINT32(SA110_OUT_INT_STATUS, \
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77 SA110_OUT_INT_STATUS_DOORBELL_INT \
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78 |SA110_OUT_INT_STATUS_OUTBOUND_INT); \
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79 \
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80 /* Disable Doorbells */ \
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81 HAL_WRITE_UINT32(SA110_DOORBELL_PCI_MASK, 0); \
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82 HAL_WRITE_UINT32(SA110_DOORBELL_SA_MASK, 0); \
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83 \
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84 /* Map high PCI address bits to 0 */ \
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85 HAL_WRITE_UINT32(SA110_PCI_ADDR_EXT, 0); \
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86 \
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87 /* Interrupt ID to 1 */ \
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88 HAL_WRITE_UINT16(SA110_PCI_CFG_INT_LINE, 0x0100); \
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89 \
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90 /* Remove PCI_reset */ \
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91 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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92 __tmp |= SA110_CONTROL_RST_I; \
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93 HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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94 \
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95 /* Open a window to SDRAM from PCI address space */ \
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96 HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_MASK, \
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97 ((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE-1) & 0xfffc0000)); \
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98 HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_OFFSET, \
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99 CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE); \
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100 \
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101 /* Only init PCI if central function is set and */ \
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102 /* standalone bit is cleared */ \
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103 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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104 HAL_READ_UINT32(SA110_XBUS_XCS2, __tmp2); \
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105 if ((__tmp & SA110_CONTROL_CFN) == SA110_CONTROL_CFN \
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106 && (__tmp2 & SA110_XBUS_XCS2_PCI_DISABLE) == 0) { \
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107 \
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108 /* Don't respond to any commands */ \
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109 HAL_WRITE_UINT16(SA110_PCI_CFG_COMMAND, 0); \
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110 \
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111 /* Set up default addresses for board's resources. */ \
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112 HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_MEM_BAR, \
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113 EBSA_CSR_MEM_PCI_ADDR); \
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114 HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_IO_BAR, EBSA_CSR_IO_PCI_ADDR);\
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115 HAL_WRITE_UINT32(SA110_PCI_CFG_SDRAM_BAR, EBSA_SDRAM_PCI_ADDR); \
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116 \
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117 /* Respond to I/O space & Memory transactions. */ \
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118 HAL_WRITE_UINT32(SA110_PCI_CFG_COMMAND, \
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119 CYG_PCI_CFG_COMMAND_INVALIDATE \
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120 |CYG_PCI_CFG_COMMAND_IO \
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121 |CYG_PCI_CFG_COMMAND_MEMORY \
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122 |CYG_PCI_CFG_COMMAND_MASTER); \
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123 } \
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124 /* Signal PCI_init_complete */ \
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125 HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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126 __tmp |= SA110_CONTROL_INIT_COMPLETE; \
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127 HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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128 \
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129 CYG_MACRO_END
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130
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131
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132 // Compute address necessary to access PCI config space for the given
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133 // bus and device.
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134 #define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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135 ({ \
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136 cyg_uint32 __addr; \
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137 cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
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138 if (0 == __bus) { \
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139 if (0 == __dev) { \
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140 /* Access self via CSR base */ \
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141 __addr = SA110_CONTROL_STATUS_BASE; \
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142 } else { \
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143 /* Page 3-17, table 3-5: bits 15-11 generate PCI address */ \
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144 __addr = SA110_PCI_CONFIG0_BASE | 0x00c00000 | (__dev << 11);\
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145 } \
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146 } else { \
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147 __addr = SA110_PCI_CONFIG1_BASE | (__bus << 16) | (__dev << 11); \
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148 } \
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149 __addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
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150 __addr |= __offset; \
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151 __addr; \
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152 })
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153
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154 // Read a value from the PCI configuration space of the appropriate
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155 // size at an address composed from the bus, devfn and offset.
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156 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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157 HAL_READ_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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158
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159 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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160 HAL_READ_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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161
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162 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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163 HAL_READ_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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164
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165 // Write a value to the PCI configuration space of the appropriate
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166 // size at an address composed from the bus, devfn and offset.
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167 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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168 HAL_WRITE_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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169
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170 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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171 HAL_WRITE_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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172
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173 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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174 HAL_WRITE_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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175
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176 //-----------------------------------------------------------------------------
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177 // Resources
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178
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179 // Map PCI device resources starting from these addresses in PCI space.
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180 #define HAL_PCI_ALLOC_BASE_MEMORY (EBSA_SDRAM_PCI_SIZE+EBSA_CSR_MEM_PCI_SIZE)
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181 #define HAL_PCI_ALLOC_BASE_IO (EBSA_CSR_IO_PCI_SIZE)
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182
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183 // This is where the PCI spaces are mapped in the CPU's address space.
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184 #define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
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185 #define HAL_PCI_PHYSICAL_IO_BASE 0x7c000000
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186
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187 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
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188 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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189 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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190 CYG_MACRO_START \
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191 cyg_uint8 __req; \
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192 HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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193 if (0 != __req) { \
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194 /* Interrupt assignment as 21285 sees them. (From */ \
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195 /* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
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196 CYG_ADDRWORD __translation[4] = { \
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197 CYGNUM_HAL_INTERRUPT_IRQ_IN_1, /* INTC# */ \
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198 CYGNUM_HAL_INTERRUPT_IRQ_IN_0, /* INTB# */ \
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199 CYGNUM_HAL_INTERRUPT_PCI_IRQ, /* INTA# */ \
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200 CYGNUM_HAL_INTERRUPT_IRQ_IN_3}; /* INTD# */ \
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201 \
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202 /* The PCI lines from the different slots are wired like this */ \
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203 /* on the PCI backplane: */ \
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204 /* pin6A pin7B pin7A pin8B */ \
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205 /* System Slot INTA# INTB# INTC# INTD# */ \
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206 /* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
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207 /* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
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208 /* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
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209 /* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
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210 /* */ \
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211 /* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
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212 /* */ \
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213 /* Devsel signals are wired to, resulting in device IDs: */ \
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214 /* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
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215 /* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
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216 /* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
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217 /* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
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218 /* */ \
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219 /* (From PCI Development Backplane, 3.2.1 General) */ \
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220 /* */ \
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221 /* The observant reader will notice that the array does not */ \
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222 /* match the table of how interrupts are wired. The array */ \
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223 /* does however match observed behavior of the hardware: */ \
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224 /* */ \
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225 /* Observed interrupts with an Intel ethernet card */ \
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226 /* put in the slots in turn and set to generate interrupts: */ \
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227 /* slot 1/intA# (dev 8): caused host INTB# */ \
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228 /* slot 2/intA# (dev 7): caused host INTC# */ \
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229 /* slot 3/intA# (dev 6): caused host INTD# */ \
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230 /* slot 4/intA# (dev 5): caused host INTA# */ \
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231 \
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232 __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
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233 __valid = true; \
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234 } else { \
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235 /* Device will not generate interrupt requests. */ \
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236 __valid = false; \
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237 } \
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238 CYG_MACRO_END
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239
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240 //-----------------------------------------------------------------------------
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241 // end of plf_io.h
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242 #endif // CYGONCE_PLF_IO_H