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1 #ifndef CYGONCE_HAL_HAL_IO_H |
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2 #define CYGONCE_HAL_HAL_IO_H |
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3 |
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4 //============================================================================= |
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5 // |
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6 // hal_io.h |
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7 // |
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8 // HAL device IO register support. |
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9 // |
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10 //============================================================================= |
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11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Cygnus eCos Public License |
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15 // Version 1.0 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://sourceware.cygnus.com/ecos |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
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25 // September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Cygnus. Portions created |
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28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
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29 // ------------------------------------------- |
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30 // |
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31 //####COPYRIGHTEND#### |
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32 //============================================================================= |
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33 //#####DESCRIPTIONBEGIN#### |
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34 // |
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35 // Author(s): nickg |
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36 // Contributors: nickg |
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37 // Date: 1998-02-17 |
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38 // Purpose: Define IO register support |
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39 // Description: The macros defined here provide the HAL APIs for handling |
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40 // device IO control registers. |
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41 // |
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42 // Usage: |
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43 // #include <cyg/hal/hal_io.h> |
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44 // ... |
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45 // |
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46 // |
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47 //####DESCRIPTIONEND#### |
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48 // |
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49 //============================================================================= |
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50 |
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51 #include <cyg/infra/cyg_type.h> |
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52 |
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53 //----------------------------------------------------------------------------- |
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54 // IO Register address. |
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55 // This type is for recording the address of an IO register. |
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56 |
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57 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; |
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58 |
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59 //----------------------------------------------------------------------------- |
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60 // BYTE Register access. |
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61 // Individual and vectorized access to 8 bit registers. |
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62 |
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63 #define HAL_READ_UINT8( _register_, _value_ ) \ |
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64 ((_value_) = *((volatile CYG_BYTE *)(_register_))) |
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65 |
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66 #define HAL_WRITE_UINT8( _register_, _value_ ) \ |
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67 (*((volatile CYG_BYTE *)(_register_)) = (_value_)) |
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68 |
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69 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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70 { \ |
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71 cyg_count32 _i_,_j_; \ |
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72 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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73 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ |
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74 } |
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75 |
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76 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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77 { \ |
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78 cyg_count32 _i_,_j_; \ |
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79 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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80 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ |
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81 } |
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82 |
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83 |
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84 //----------------------------------------------------------------------------- |
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85 // 16 bit access. |
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86 // Individual and vectorized access to 16 bit registers. |
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87 |
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88 #define HAL_READ_UINT16( _register_, _value_ ) \ |
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89 ((_value_) = *((volatile CYG_WORD16 *)(_register_))) |
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90 |
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91 #define HAL_WRITE_UINT16( _register_, _value_ ) \ |
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92 (*((volatile CYG_WORD16 *)(_register_)) = (_value_)) |
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93 |
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94 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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95 { \ |
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96 cyg_count32 _i_,_j_; \ |
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97 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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98 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ |
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99 } |
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100 |
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101 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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102 { \ |
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103 cyg_count32 _i_,_j_; \ |
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104 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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105 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
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106 } |
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107 |
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108 //----------------------------------------------------------------------------- |
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109 // 32 bit access. |
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110 // Individual and vectorized access to 32 bit registers. |
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111 |
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112 #define HAL_READ_UINT32( _register_, _value_ ) \ |
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113 ((_value_) = *((volatile CYG_WORD32 *)(_register_))) |
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114 |
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115 #define HAL_WRITE_UINT32( _register_, _value_ ) \ |
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116 (*((volatile CYG_WORD32 *)(_register_)) = (_value_)) |
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117 |
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118 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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119 { \ |
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120 cyg_count32 _i_,_j_; \ |
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121 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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122 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ |
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123 } |
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124 |
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125 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
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126 { \ |
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127 cyg_count32 _i_,_j_; \ |
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128 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
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129 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
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130 } |
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131 |
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132 //----------------------------------------------------------------------------- |
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133 #endif // ifndef CYGONCE_HAL_HAL_IO_H |
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134 // End of hal_io.h |
