|
2
|
1 #ifndef CYGONCE_HAL_CACHE_H |
|
|
2 #define CYGONCE_HAL_CACHE_H |
|
|
3 |
|
|
4 //============================================================================= |
|
|
5 // |
|
|
6 // hal_cache.h |
|
|
7 // |
|
|
8 // HAL Cache control support (such as it is in the simulator) |
|
|
9 // |
|
|
10 //============================================================================= |
|
|
11 //####COPYRIGHTBEGIN#### |
|
|
12 // |
|
|
13 // ------------------------------------------- |
|
|
14 // The contents of this file are subject to the Cygnus eCos Public License |
|
|
15 // Version 1.0 (the "License"); you may not use this file except in |
|
|
16 // compliance with the License. You may obtain a copy of the License at |
|
|
17 // http://sourceware.cygnus.com/ecos |
|
|
18 // |
|
|
19 // Software distributed under the License is distributed on an "AS IS" |
|
|
20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
|
|
21 // License for the specific language governing rights and limitations under |
|
|
22 // the License. |
|
|
23 // |
|
|
24 // The Original Code is eCos - Embedded Cygnus Operating System, released |
|
|
25 // September 30, 1998. |
|
|
26 // |
|
|
27 // The Initial Developer of the Original Code is Cygnus. Portions created |
|
|
28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
|
|
29 // ------------------------------------------- |
|
|
30 // |
|
|
31 //####COPYRIGHTEND#### |
|
|
32 //============================================================================= |
|
|
33 //#####DESCRIPTIONBEGIN#### |
|
|
34 // |
|
|
35 // Author(s): nickg, gthomas, hmt |
|
|
36 // Contributors: nickg, gthomas, hmt |
|
|
37 // Date: 1999-01-28 |
|
|
38 // Purpose: Define Interrupt support |
|
|
39 // Description: The macros defined here provide the HAL APIs for handling |
|
|
40 // the caches. |
|
|
41 // |
|
|
42 // Usage: |
|
|
43 // #include <cyg/hal/hal_cache.h> |
|
|
44 // ... |
|
|
45 // |
|
|
46 // |
|
|
47 //####DESCRIPTIONEND#### |
|
|
48 // |
|
|
49 //============================================================================= |
|
|
50 |
|
|
51 #include <pkgconf/hal.h> |
|
|
52 #include <pkgconf/hal_sparclite.h> |
|
|
53 |
|
|
54 #include <cyg/infra/cyg_type.h> |
|
|
55 |
|
|
56 //----------------------------------------------------------------------------- |
|
|
57 // SPARClite cache macros |
|
|
58 |
|
|
59 // The MB6863x Control Registers are in Address Space 1: |
|
|
60 #define HAL_SPARC_ASI_1_READ( addr, res ) \ |
|
|
61 asm volatile( \ |
|
|
62 "lda [ %1 ] 1, %0" \ |
|
|
63 : "=r"(res) \ |
|
|
64 : "r"(addr) \ |
|
|
65 ); |
|
|
66 |
|
|
67 #define HAL_SPARC_ASI_1_WRITE( addr, val ) \ |
|
|
68 asm volatile( \ |
|
|
69 "sta %0, [ %1 ] 1" \ |
|
|
70 : \ |
|
|
71 : "r"(val),"r"(addr) \ |
|
|
72 ); |
|
|
73 |
|
|
74 #define HAL_SPARC_MMCR_CBIR 0x00 // Cache/BusInterfaceUnit Control |
|
|
75 #define HAL_SPARC_MMCR_LCR 0x04 // Lock Control Register |
|
|
76 #define HAL_SPARC_MMCR_LCSR 0x08 // Lock Control Save Reg |
|
|
77 #define HAL_SPARC_MMCR_CSR 0x0c // Cache Status Reg |
|
|
78 #define HAL_SPARC_MMCR_RLCR 0x10 // Restore Lock Control Register |
|
|
79 |
|
|
80 #define HAL_SPARC_MMCR_CBIR_ICE 0x01 // Instruction Cache Enable |
|
|
81 #define HAL_SPARC_MMCR_CBIR_GICL 0x02 // Global IC Lock |
|
|
82 #define HAL_SPARC_MMCR_CBIR_DCE 0x04 // Data CE |
|
|
83 #define HAL_SPARC_MMCR_CBIR_GDCL 0x08 // G Data CE |
|
|
84 #define HAL_SPARC_MMCR_CBIR_PBE 0x10 // Prefetch Buffer Enable |
|
|
85 #define HAL_SPARC_MMCR_CBIR_WBE 0x20 // Write BE |
|
|
86 |
|
|
87 |
|
|
88 //----------------------------------------------------------------------------- |
|
|
89 // Cache dimensions |
|
|
90 |
|
|
91 // These definitions are suitable for any MB8683x processor: |
|
|
92 // The largest possible cachesize and "ways", |
|
|
93 // the smallest possible line size. |
|
|
94 // This gives values that can correctly manipulate the cache by |
|
|
95 // jumping on memory. |
|
|
96 |
|
|
97 // Data cache |
|
|
98 #define HAL_DCACHE_SIZE 0x2000 // Size of data cache in bytes |
|
|
99 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
|
|
100 #define HAL_DCACHE_WAYS 2 // Associativity of the cache |
|
|
101 |
|
|
102 // Instruction cache |
|
|
103 #define HAL_ICACHE_SIZE 0x2000 // Size of cache in bytes |
|
|
104 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
|
|
105 #define HAL_ICACHE_WAYS 2 // Associativity of the cache |
|
|
106 |
|
|
107 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
|
|
108 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
|
|
109 |
|
|
110 //----------------------------------------------------------------------------- |
|
|
111 // Global control of data cache |
|
|
112 |
|
|
113 // Enable the data cache |
|
|
114 #define HAL_DCACHE_ENABLE() CYG_MACRO_START \ |
|
|
115 int _v_; \ |
|
|
116 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
117 _v_ |= HAL_SPARC_MMCR_CBIR_DCE; \ |
|
|
118 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
119 asm volatile ( "nop; nop; nop; nop;" ); \ |
|
|
120 CYG_MACRO_END |
|
|
121 |
|
|
122 // Disable the data cache |
|
|
123 #define HAL_DCACHE_DISABLE() CYG_MACRO_START \ |
|
|
124 int _v_; \ |
|
|
125 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
126 _v_ &=~ HAL_SPARC_MMCR_CBIR_DCE; \ |
|
|
127 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
128 asm volatile ( "nop; nop; nop; nop;" ); \ |
|
|
129 CYG_MACRO_END |
|
|
130 |
|
|
131 // Invalidate the entire cache |
|
|
132 #define HAL_DCACHE_INVALIDATE_ALL() CYG_MACRO_START \ |
|
|
133 asm volatile ( \ |
|
|
134 "set 3, %%l0;" \ |
|
|
135 "set 0x00001000, %%l1;" \ |
|
|
136 "set 0x80001000, %%l2;" \ |
|
|
137 "sta %%l0, [ %%l1 ] 0x0e;" \ |
|
|
138 "sta %%l0, [ %%l2 ] 0x0e;" \ |
|
|
139 "nop;" \ |
|
|
140 "nop;" \ |
|
|
141 "nop;" \ |
|
|
142 "nop" : : : "l0","l1","l2" ); \ |
|
|
143 CYG_MACRO_END |
|
|
144 |
|
|
145 // Synchronize the contents of the cache with memory. |
|
|
146 #define HAL_DCACHE_SYNC() CYG_MACRO_START \ |
|
|
147 /* read 8k from the ROM; that should do it... */ \ |
|
|
148 volatile cyg_uint32 *_p_ = (cyg_uint32 *)0; \ |
|
|
149 volatile cyg_uint32 *_q_ = (cyg_uint32 *)HAL_DCACHE_SIZE; \ |
|
|
150 volatile cyg_uint32 _tmp_; \ |
|
|
151 for ( ; _p_ < _q_; _p_ ++ ) _tmp_ = *_q_; \ |
|
|
152 CYG_MACRO_END |
|
|
153 |
|
|
154 // Query the state of the data cache |
|
|
155 #define HAL_DCACHE_IS_ENABLED(_state_) CYG_MACRO_START \ |
|
|
156 int _v_; \ |
|
|
157 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
158 (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_DCE)); \ |
|
|
159 CYG_MACRO_END |
|
|
160 |
|
|
161 |
|
|
162 // Set the data cache refill burst size |
|
|
163 //#define HAL_DCACHE_BURST_SIZE(_size_) |
|
|
164 |
|
|
165 // Set the data cache write mode |
|
|
166 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
|
|
167 |
|
|
168 //#define HAL_DCACHE_WRITETHRU_MODE 0 |
|
|
169 //#define HAL_DCACHE_WRITEBACK_MODE 1 |
|
|
170 |
|
|
171 // Load the contents of the given address range into the data cache |
|
|
172 // and then lock the cache so that it stays there. |
|
|
173 //#define HAL_DCACHE_LOCK(_base_, _size_) |
|
|
174 |
|
|
175 // Undo a previous lock operation |
|
|
176 //#define HAL_DCACHE_UNLOCK(_base_, _size_) |
|
|
177 |
|
|
178 // Unlock entire cache |
|
|
179 //#define HAL_DCACHE_UNLOCK_ALL() |
|
|
180 |
|
|
181 //----------------------------------------------------------------------------- |
|
|
182 // Data cache line control |
|
|
183 |
|
|
184 // Allocate cache lines for the given address range without reading its |
|
|
185 // contents from memory. |
|
|
186 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
|
|
187 |
|
|
188 // Write dirty cache lines to memory and invalidate the cache entries |
|
|
189 // for the given address range. |
|
|
190 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
|
|
191 |
|
|
192 // Invalidate cache lines in the given range without writing to memory. |
|
|
193 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
|
|
194 |
|
|
195 // Write dirty cache lines to memory for the given address range. |
|
|
196 //#define HAL_DCACHE_STORE( _base_ , _size_ ) |
|
|
197 |
|
|
198 // Preread the given range into the cache with the intention of reading |
|
|
199 // from it later. |
|
|
200 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
|
|
201 |
|
|
202 // Preread the given range into the cache with the intention of writing |
|
|
203 // to it later. |
|
|
204 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
|
|
205 |
|
|
206 // Allocate and zero the cache lines associated with the given range. |
|
|
207 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
|
|
208 |
|
|
209 //----------------------------------------------------------------------------- |
|
|
210 // Global control of Instruction cache - use Data cache controls since they |
|
|
211 // are not separatable. |
|
|
212 |
|
|
213 // Enable the data cache |
|
|
214 #define HAL_ICACHE_ENABLE() CYG_MACRO_START \ |
|
|
215 int _v_; \ |
|
|
216 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
217 _v_ |= HAL_SPARC_MMCR_CBIR_ICE; \ |
|
|
218 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
219 asm volatile ( "nop; nop; nop; nop;" ); \ |
|
|
220 CYG_MACRO_END |
|
|
221 |
|
|
222 // Disable the data cache |
|
|
223 #define HAL_ICACHE_DISABLE() CYG_MACRO_START \ |
|
|
224 int _v_; \ |
|
|
225 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
226 _v_ &=~ HAL_SPARC_MMCR_CBIR_ICE; \ |
|
|
227 HAL_SPARC_ASI_1_WRITE( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
228 asm volatile ( "nop; nop; nop; nop;" ); \ |
|
|
229 CYG_MACRO_END |
|
|
230 |
|
|
231 // Invalidate the entire cache |
|
|
232 #define HAL_ICACHE_INVALIDATE_ALL() CYG_MACRO_START \ |
|
|
233 asm volatile ( \ |
|
|
234 "set 3, %%l0;" \ |
|
|
235 "set 0x00001000, %%l1;" \ |
|
|
236 "set 0x80001000, %%l2;" \ |
|
|
237 "sta %%l0, [ %%l1 ] 0x0c;" \ |
|
|
238 "sta %%l0, [ %%l2 ] 0x0c;" \ |
|
|
239 "nop;" \ |
|
|
240 "nop;" \ |
|
|
241 "nop;" \ |
|
|
242 "nop" : : : "l0","l1","l2" ); \ |
|
|
243 CYG_MACRO_END |
|
|
244 |
|
|
245 // Synchronize the contents of the cache with memory. |
|
|
246 #define HAL_ICACHE_SYNC() CYG_MACRO_START \ |
|
|
247 HAL_DCACHE_SYNC(); /* Ensure data is in memory */ \ |
|
|
248 HAL_ICACHE_INVALIDATE_ALL(); /* Pick up new memory contents */ \ |
|
|
249 CYG_MACRO_END |
|
|
250 |
|
|
251 // Query the state of the instruction cache |
|
|
252 #define HAL_ICACHE_IS_ENABLED(_state_) CYG_MACRO_START \ |
|
|
253 int _v_; \ |
|
|
254 HAL_SPARC_ASI_1_READ( HAL_SPARC_MMCR_CBIR, _v_ ); \ |
|
|
255 (_state_) = (0 != (_v_ & HAL_SPARC_MMCR_CBIR_ICE)); \ |
|
|
256 CYG_MACRO_END |
|
|
257 |
|
|
258 // Set the instruction cache refill burst size |
|
|
259 //#define HAL_ICACHE_BURST_SIZE(_size_) |
|
|
260 |
|
|
261 // Load the contents of the given address range into the instruction cache |
|
|
262 // and then lock the cache so that it stays there. |
|
|
263 //#define HAL_ICACHE_LOCK(_base_, _size_) |
|
|
264 |
|
|
265 // Undo a previous lock operation |
|
|
266 //#define HAL_ICACHE_UNLOCK(_base_, _size_) |
|
|
267 |
|
|
268 // Unlock entire cache |
|
|
269 //#define HAL_ICACHE_UNLOCK_ALL() |
|
|
270 |
|
|
271 //----------------------------------------------------------------------------- |
|
|
272 // Instruction cache line control |
|
|
273 |
|
|
274 // Invalidate cache lines in the given range without writing to memory. |
|
|
275 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
|
|
276 |
|
|
277 //----------------------------------------------------------------------------- |
|
|
278 #endif // ifndef CYGONCE_HAL_CACHE_H |
|
|
279 // End of hal_cache.h |
