Mercurial > ecos

annotate packages/hal/mips/arch/current/include/mips-regs.h @ 26:4741a3c3496a ecos-sw-1999-07-23

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Merge from eCos master repository on 1999-07-23-05:47:06-BST
author jlarmour
date Fri, 23 Jul 1999 15:20:15 +0000
parents 443894e2e912
children c38311975d4f
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1 /* mips-regs.h - register defines for MIPS processors
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2 *
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3 * Copyright (c) 1998 Cygnus Solutions
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4 *
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5 * The authors hereby grant permission to use, copy, modify, distribute,
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6 * and license this software and its documentation for any purpose, provided
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7 * that existing copyright notices are retained in all copies and that this
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8 * notice is included verbatim in any distributions. No written agreement,
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9 * license, or royalty fee is required for any of the authorized uses.
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10 * Modifications to this software may be copyrighted by their authors
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11 * and need not follow the licensing terms described here, provided that
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12 * the new terms are clearly indicated on the first page of each file where
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13 * they apply.
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14 */
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15
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16 #include <pkgconf/hal.h>
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17
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18 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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19
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20 /* This value must agree with NUMREGS in mips-stub.h. */
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21
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22 #define NUM_REGS 90
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23
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24 #ifdef __mips64
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25 #define REG_SIZE 8
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26 #else
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27 #define REG_SIZE 4
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28 #endif
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29
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30 /* General register names for assembly code. */
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31
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32 #define zero $0
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33 #define at $1 /* assembler temporary */
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34 #define v0 $2 /* value holders */
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35 #define v1 $3
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36 #define a0 $4 /* arguments */
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37 #define a1 $5
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38 #define a2 $6
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39 #define a3 $7
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40 #define t0 $8 /* temporaries */
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41 #define t1 $9
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42 #define t2 $10
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43 #define t3 $11
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44 #define t4 $12
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45 #define t5 $13
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46 #define t6 $14
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47 #define t7 $15
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48 #define s0 $16 /* saved registers */
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49 #define s1 $17
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50 #define s2 $18
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51 #define s3 $19
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52 #define s4 $20
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53 #define s5 $21
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54 #define s6 $22
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55 #define s7 $23
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56 #define t8 $24 /* temporaries */
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57 #define t9 $25
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58 #define k0 $26 /* kernel registers */
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59 #define k1 $27
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60 #define gp $28 /* global pointer */
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61 #define sp $29 /* stack pointer */
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62 #define s8 $30 /* saved register */
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63 #define fp $30 /* frame pointer (obsolete usage) */
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64 #define ra $31 /* return address */
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66 /* MIPS registers, numbered in the order in which gdb expects to see them. */
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67 #define ZERO 0
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68 #define AT 1
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69 #define V0 2
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70 #define V1 3
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71 #define A0 4
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72 #define A1 5
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73 #define A2 6
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74 #define A3 7
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75
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76 #define T0 8
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77 #define T1 9
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78 #define T2 10
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79 #define T3 11
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80 #define T4 12
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81 #define T5 13
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82 #define T6 14
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83 #define T7 15
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84
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85 #define S0 16
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86 #define S1 17
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87 #define S2 18
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88 #define S3 19
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89 #define S4 20
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90 #define S5 21
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91 #define S6 22
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92 #define S7 23
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93
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94 #define T8 24
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95 #define T9 25
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96 #define K0 26
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97 #define K1 27
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98 #define GP 28
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99 #define SP 29
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100 #define S8 30
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101 #define RA 31
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102
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103 #define SR 32
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104 #define LO 33
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105 #define HI 34
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106 #define BAD_VA 35
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107 #define CAUSE 36
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108 #define PC 37
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109
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110 #define F0 38
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111 #define F1 39
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112 #define F2 40
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113 #define F3 41
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114 #define F4 42
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115 #define F5 43
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116 #define F6 44
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117 #define F7 45
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118 #define F8 46
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119 #define F9 47
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120 #define F10 48
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121 #define F11 49
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122 #define F12 50
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123 #define F13 51
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124 #define F14 52
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125 #define F15 53
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126 #define F16 54
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127 #define F17 55
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128 #define F18 56
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129 #define F19 57
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130 #define F20 58
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131 #define F21 59
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132 #define F22 60
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133 #define F23 61
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134 #define F24 62
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135 #define F25 63
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136 #define F26 64
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137 #define F27 65
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138 #define F28 66
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139 #define F29 67
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140 #define F30 68
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141 #define F31 69
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142
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143 #define FCR31 70
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144
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145 /* System Control Coprocessor (CP0) exception processing registers */
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146 #define C0_CONTEXT $4 /* Context */
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147 #define C0_BADVADDR $8 /* Bad Virtual Address */
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148 #define C0_COUNT $9 /* Count */
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149 #define C0_COMPARE $11 /* Compare */
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150 #define C0_STATUS $12 /* Processor Status */
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151 #define C0_CAUSE $13 /* Exception Cause */
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152 #define C0_EPC $14 /* Exception PC */
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153 #define C0_XCONTEXT $20 /* XContext */
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154 #define C0_ECC $26 /* ECC */
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155 #define C0_CACHEERR $27 /* CacheErr */
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156 #define C0_ERROREPC $30 /* ErrorEPC */
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157
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158 /* Status register fields */
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159 #define SR_CUMASK 0xf0000000 /* Coprocessor usable bits */
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160 #define SR_CU3 0x80000000 /* Coprocessor 3 usable */
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161 #define SR_CU2 0x40000000 /* coprocessor 2 usable */
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162 #define SR_CU1 0x20000000 /* Coprocessor 1 usable */
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163 #define SR_CU0 0x10000000 /* Coprocessor 0 usable */
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164
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165 #define SR_FR 0x04000000 /* Enable 32 floating-point registers */
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166 #define SR_RE 0x02000000 /* Reverse Endian in user mode */
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167
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168 #define SR_BEV 0x00400000 /* Bootstrap Exception Vector */
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169 #define SR_TS 0x00200000 /* TLB shutdown (reserved on R4600) */
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170 #define SR_SR 0x00100000 /* Soft Reset */
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171
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172 #define SR_CH 0x00040000 /* Cache Hit */
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173 #define SR_CE 0x00020000 /* ECC register modifies check bits */
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174 #define SR_DE 0x00010000 /* Disable cache errors */
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175
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176 #define SR_IMASK 0x0000ff00 /* Interrupt Mask */
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177 #define SR_IMASK8 0x00000000 /* Interrupt Mask level=8 */
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178 #define SR_IMASK7 0x00008000 /* Interrupt Mask level=7 */
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179 #define SR_IMASK6 0x0000c000 /* Interrupt Mask level=6 */
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180 #define SR_IMASK5 0x0000e000 /* Interrupt Mask level=5 */
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181 #define SR_IMASK4 0x0000f000 /* Interrupt Mask level=4 */
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182 #define SR_IMASK3 0x0000f800 /* Interrupt Mask level=3 */
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183 #define SR_IMASK2 0x0000fc00 /* Interrupt Mask level=2 */
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184 #define SR_IMASK1 0x0000fe00 /* Interrupt Mask level=1 */
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185 #define SR_IMASK0 0x0000ff00 /* Interrupt Mask level=0 */
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186
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187 #define SR_IBIT8 0x00008000 /* (Intr5) */
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188 #define SR_IBIT7 0x00004000 /* (Intr4) */
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189 #define SR_IBIT6 0x00002000 /* (Intr3) */
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190 #define SR_IBIT5 0x00001000 /* (Intr2) */
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191 #define SR_IBIT4 0x00000800 /* (Intr1) */
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192 #define SR_IBIT3 0x00000400 /* (Intr0) */
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193 #define SR_IBIT2 0x00000200 /* (Software Interrupt 1) */
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194 #define SR_IBIT1 0x00000100 /* (Software Interrupt 0) */
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195
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196 #define SR_KX 0x00000080 /* xtlb in kernel mode */
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197 #define SR_SX 0x00000040 /* mips3 & xtlb in supervisor mode */
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198 #define SR_UX 0x00000020 /* mips3 & xtlb in user mode */
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199
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200 #define SR_KSU_MASK 0x00000018 /* ksu mode mask */
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201 #define SR_KSU_USER 0x00000010 /* user mode */
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202 #define SR_KSU_SUPV 0x00000008 /* supervisor mode */
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203 #define SR_KSU_KERN 0x00000000 /* kernel mode */
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204
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205 #define SR_ERL 0x00000004 /* error level */
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206 #define SR_EXL 0x00000002 /* exception level */
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207 #define SR_IE 0x00000001 /* interrupt enable */
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208
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209 /* Floating-point unit control/status register (FCR31) */
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210 #define FCR31_FS 0x01000000 /* Flush denormalized to zero */
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211 #define FCR31_C 0x00800000 /* FP compare result */
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212
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213 #define FCR31_CAUSE_E 0x00020000 /* Cause - unimplemented operation */
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214 #define FCR31_CAUSE_V 0x00010000 /* Cause - invalid operation */
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215 #define FCR31_CAUSE_Z 0x00008000 /* Cause - division by zero */
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216 #define FCR31_CAUSE_O 0x00004000 /* Cause - overflow */
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217 #define FCR31_CAUSE_U 0x00002000 /* Cause - underflow */
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218 #define FCR31_CAUSE_I 0x00001000 /* Cause - inexact operation */
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219
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220 #define FCR31_ENABLES_V 0x00000800 /* Enables - invalid operation */
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221 #define FCR31_ENABLES_Z 0x00000400 /* Enables - division by zero */
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222 #define FCR31_ENABLES_O 0x00000200 /* Enables - overflow */
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223 #define FCR31_ENABLES_U 0x00000100 /* Enables - underflow */
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224 #define FCR31_ENABLES_I 0x00000080 /* Enables - inexact operation */
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225
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226 #define FCR31_FLAGS_V 0x00000040 /* Flags - invalid operation */
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227 #define FCR31_FLAGS_Z 0x00000020 /* Flags - division by zero */
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228 #define FCR31_FLAGS_O 0x00000010 /* Flags - overflow */
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229 #define FCR31_FLAGS_U 0x00000008 /* Flags - underflow */
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230 #define FCR31_FLAGS_I 0x00000004 /* Flags - inexact operation */
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231
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232 #define FCR31_RMMASK 0x00000002 /* Rounding mode mask */
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233 #define FCR31_RM_RN 0 /* Round to nearest */
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234 #define FCR31_RM_RZ 1 /* Round to zero */
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235 #define FCR31_RM_RP 2 /* Round to +infinity */
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236 #define FCR31_RM_RM 3 /* Round to -infinity */
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237
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238
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239 /* Cause register fields */
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240 #define CAUSE_BD 0x80000000 /* Branch Delay */
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241 #define CAUSE_CEMASK 0x30000000 /* Coprocessor Error */
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242 #define CAUSE_CESHIFT 28 /* Right justify CE */
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243 #define CAUSE_IPMASK 0x0000ff00 /* Interrupt Pending */
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244 #define CAUSE_IPSHIFT 8 /* Right justify IP */
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245 #define CAUSE_IP8 0x00008000 /* (Intr5) */
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246 #define CAUSE_IP7 0x00004000 /* (Intr4) */
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247 #define CAUSE_IP6 0x00002000 /* (Intr3) */
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248 #define CAUSE_IP5 0x00001000 /* (Intr2) */
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249 #define CAUSE_IP4 0x00000800 /* (Intr1) */
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250 #define CAUSE_IP3 0x00000400 /* (Intr0) */
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251 #define CAUSE_SW2 0x00000200 /* (Software Interrupt 1) */
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252 #define CAUSE_SW1 0x00000100 /* (Software Interrupt 0) */
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253 #define CAUSE_EXCMASK 0x0000007c /* Exception Code */
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254 #define CAUSE_EXCSHIFT 2 /* Right justify EXC */
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255
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256 /* Exception Codes */
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257 #define EXC_INT 0 /* External interrupt */
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258 #define EXC_MOD 1 /* TLB modification exception */
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259 #define EXC_TLBL 2 /* TLB miss (Load or Ifetch) */
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260 #define EXC_TLBS 3 /* TLB miss (Store) */
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261 #define EXC_ADEL 4 /* Address error (Load or Ifetch) */
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262 #define EXC_ADES 5 /* Address error (Store) */
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263 #define EXC_IBE 6 /* Bus error (Ifetch) */
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264 #define EXC_DBE 7 /* Bus error (data load or store) */
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265 #define EXC_SYS 8 /* System call */
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266 #define EXC_BP 9 /* Break point */
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267 #define EXC_RI 10 /* Reserved instruction */
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268 #define EXC_CPU 11 /* Coprocessor unusable */
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269 #define EXC_OVF 12 /* Arithmetic overflow */
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270 #define EXC_TRAP 13 /* Trap exception */
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271 #define EXC_FPE 15 /* Floating Point Exception */
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272
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273 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS