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annotate packages/kernel/current/tests/kcache1.c @ 84:489eb5632bc3 ecos-sw-2000-04-28

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Merge from eCos master repository on 2000-04-28-18:44:39-BST
author jlarmour
date Fri, 28 Apr 2000 18:18:36 +0000
parents 59d97b6ba612
children 97d9d85b42c0
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1 /*=================================================================
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2 //
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3 // kcache1.c
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4 //
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5 // Cache timing test
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): dsm
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35 // Contributors: dsm, nickg
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36 // Date: 1998-06-18
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37 //####DESCRIPTIONEND####
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38 */
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39
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40 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
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41
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42 #include <cyg/kernel/kapi.h>
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43
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44 #include <cyg/infra/testcase.h>
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45
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46 #include <cyg/hal/hal_cache.h>
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47
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48 #if defined(HAL_DCACHE_SIZE) || defined(HAL_UCACHE_SIZE)
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49 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
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50 #ifdef CYGFUN_KERNEL_API_C
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51
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52 #include <cyg/infra/diag.h>
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53 #include <cyg/hal/hal_intr.h>
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54
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55 // -------------------------------------------------------------------------
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56 // If the HAL does not supply this, we supply our own version
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57
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58 #ifndef HAL_DCACHE_PURGE_ALL
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59 # ifdef HAL_DCACHE_SYNC
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61 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC()
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63 # else
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65 static cyg_uint8 dca[HAL_DCACHE_SIZE + HAL_DCACHE_LINE_SIZE*2];
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66
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67 #define HAL_DCACHE_PURGE_ALL() \
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68 CYG_MACRO_START \
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69 volatile cyg_uint8 *addr = &dca[HAL_DCACHE_LINE_SIZE]; \
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70 volatile cyg_uint8 tmp = 0; \
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71 int i; \
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72 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
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73 { \
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74 tmp = addr[i]; \
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75 } \
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76 CYG_MACRO_END
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77
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78 # endif
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79 #endif
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80
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81 // -------------------------------------------------------------------------
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82
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83 #define NTHREADS 1
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84 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
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85
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86 static cyg_handle_t thread[NTHREADS];
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87
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88 static cyg_thread thread_obj[NTHREADS];
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89 static char stack[NTHREADS][STACKSIZE];
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90
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91 #ifndef MAX_STRIDE
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92 #define MAX_STRIDE 64
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93 #endif
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94
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95 volatile char m[(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE)*MAX_STRIDE];
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96
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97 // -------------------------------------------------------------------------
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98
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99 static void time0(register cyg_uint32 stride)
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100 {
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101 register cyg_uint32 j,k;
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102 cyg_tick_count_t count0, count1;
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103 cyg_ucount32 t;
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104 register char c;
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105
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106 count0 = cyg_current_time();
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107
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108 k = 0;
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109 if ( cyg_test_is_simulator )
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110 k = 3960;
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111
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112 for(; k<4000;k++) {
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113 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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114 c=m[stride*j];
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115 }
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116 }
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117
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118 count1 = cyg_current_time();
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119 t = count1 - count0;
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120 diag_printf("stride=%d, time=%d\n", stride, t);
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121 }
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122
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123 // -------------------------------------------------------------------------
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124
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125 void time1(void)
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126 {
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127 cyg_uint32 i;
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128
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129 for(i=1; i<=MAX_STRIDE; i+=i) {
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130 time0(i);
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131 }
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132 }
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133
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134 // -------------------------------------------------------------------------
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135 // With an ICache invalidate in the middle:
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136 #ifdef HAL_ICACHE_INVALIDATE_ALL
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137 static void time0II(register cyg_uint32 stride)
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138 {
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139 register cyg_uint32 j,k;
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140 cyg_tick_count_t count0, count1;
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141 cyg_ucount32 t;
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142 register char c;
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143
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144 count0 = cyg_current_time();
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145
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146 k = 0;
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147 if ( cyg_test_is_simulator )
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148 k = 3960;
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149
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150 for(; k<4000;k++) {
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151 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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152 HAL_ICACHE_INVALIDATE_ALL();
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153 c=m[stride*j];
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154 }
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155 }
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156
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157 count1 = cyg_current_time();
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158 t = count1 - count0;
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159 diag_printf("stride=%d, time=%d\n", stride, t);
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160 }
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161
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162 // -------------------------------------------------------------------------
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163
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164 void time1II(void)
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165 {
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166 cyg_uint32 i;
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167
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168 for(i=1; i<=MAX_STRIDE; i+=i) {
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169 time0II(i);
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170 }
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171 }
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172 #endif
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173 // -------------------------------------------------------------------------
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174 // With a DCache invalidate in the middle:
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175 #ifdef HAL_DCACHE_INVALIDATE_ALL
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176 static void time0DI(register cyg_uint32 stride)
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177 {
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178 register cyg_uint32 j,k;
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179 volatile cyg_tick_count_t count0;
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180 cyg_tick_count_t count1;
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181 cyg_ucount32 t;
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182 register char c;
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183
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184 count0 = cyg_current_time();
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185
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186 HAL_DCACHE_SYNC();
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187
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188 k = 0;
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189 if ( cyg_test_is_simulator )
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190 k = 3960;
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191
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192 for(; k<4000;k++) {
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193 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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194 HAL_DCACHE_INVALIDATE_ALL();
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195 c=m[stride*j];
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196 }
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197 }
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198
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199 count1 = cyg_current_time();
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200 t = count1 - count0;
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201 diag_printf("stride=%d, time=%d\n", stride, t);
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202 }
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203
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204 // -------------------------------------------------------------------------
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205
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206 void time1DI(void)
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207 {
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208 cyg_uint32 i;
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209
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210 for(i=1; i<=MAX_STRIDE; i+=i) {
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211 time0DI(i);
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212 }
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213 }
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214 #endif
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215 // -------------------------------------------------------------------------
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216 // This test could be improved by counting number of passes possible
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217 // in a given number of ticks.
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218
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219 static void entry0( cyg_addrword_t data )
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220 {
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221 register CYG_INTERRUPT_STATE oldints;
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222
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223 #ifdef HAL_CACHE_UNIFIED
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224
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225 HAL_DISABLE_INTERRUPTS(oldints);
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226 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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227 HAL_UCACHE_INVALIDATE_ALL();
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228 HAL_UCACHE_DISABLE();
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229 HAL_RESTORE_INTERRUPTS(oldints);
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230 CYG_TEST_INFO("Cache off");
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231 time1();
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232
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233 HAL_DISABLE_INTERRUPTS(oldints);
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234 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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235 HAL_UCACHE_INVALIDATE_ALL();
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236 HAL_UCACHE_ENABLE();
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237 HAL_RESTORE_INTERRUPTS(oldints);
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238 CYG_TEST_INFO("Cache on");
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239 time1();
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240
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241 #ifdef HAL_DCACHE_INVALIDATE_ALL
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242 HAL_DISABLE_INTERRUPTS(oldints);
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243 HAL_DCACHE_PURGE_ALL();
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244 HAL_UCACHE_INVALIDATE_ALL();
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245 HAL_UCACHE_ENABLE();
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246 HAL_RESTORE_INTERRUPTS(oldints);
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247 CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus times)");
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248 time1DI();
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249 #endif
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250
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251 #else // HAL_CACHE_UNIFIED
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252
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253 HAL_DISABLE_INTERRUPTS(oldints);
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254 HAL_DCACHE_PURGE_ALL();
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255 HAL_ICACHE_INVALIDATE_ALL();
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256 HAL_DCACHE_INVALIDATE_ALL();
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257 HAL_ICACHE_DISABLE();
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258 HAL_DCACHE_DISABLE();
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259 HAL_RESTORE_INTERRUPTS(oldints);
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260 CYG_TEST_INFO("Dcache off Icache off");
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261 time1();
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262
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263 HAL_DISABLE_INTERRUPTS(oldints);
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264 HAL_DCACHE_PURGE_ALL();
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265 HAL_ICACHE_INVALIDATE_ALL();
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266 HAL_DCACHE_INVALIDATE_ALL();
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267 HAL_ICACHE_DISABLE();
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268 HAL_DCACHE_ENABLE();
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269 HAL_RESTORE_INTERRUPTS(oldints);
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270 CYG_TEST_INFO("Dcache on Icache off");
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271 time1();
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272
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273 HAL_DISABLE_INTERRUPTS(oldints);
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274 HAL_DCACHE_PURGE_ALL();
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275 HAL_ICACHE_INVALIDATE_ALL();
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276 HAL_DCACHE_INVALIDATE_ALL();
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277 HAL_ICACHE_ENABLE();
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278 HAL_DCACHE_DISABLE();
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279 HAL_RESTORE_INTERRUPTS(oldints);
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280 CYG_TEST_INFO("Dcache off Icache on");
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281 time1();
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282
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283 HAL_DISABLE_INTERRUPTS(oldints);
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284 HAL_DCACHE_PURGE_ALL();
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285 HAL_ICACHE_INVALIDATE_ALL();
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286 HAL_DCACHE_INVALIDATE_ALL();
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287 HAL_ICACHE_ENABLE();
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288 HAL_DCACHE_ENABLE();
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289 HAL_RESTORE_INTERRUPTS(oldints);
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290 CYG_TEST_INFO("Dcache on Icache on");
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291 time1();
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292
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293
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294 HAL_DISABLE_INTERRUPTS(oldints);
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295 HAL_DCACHE_PURGE_ALL();
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296 HAL_ICACHE_INVALIDATE_ALL();
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297 HAL_DCACHE_INVALIDATE_ALL();
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298 HAL_ICACHE_DISABLE();
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299 HAL_DCACHE_DISABLE();
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300 HAL_RESTORE_INTERRUPTS(oldints);
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301 CYG_TEST_INFO("Dcache off Icache off (again)");
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302 time1();
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303
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304 #if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
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305 HAL_DISABLE_INTERRUPTS(oldints);
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306 HAL_DCACHE_PURGE_ALL();
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307 HAL_ICACHE_INVALIDATE_ALL();
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308 HAL_DCACHE_INVALIDATE_ALL();
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309 HAL_ICACHE_ENABLE();
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310 HAL_DCACHE_ENABLE();
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311 HAL_RESTORE_INTERRUPTS(oldints);
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312 CYG_TEST_INFO("Dcache on Icache on (again)");
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313 time1();
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314
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315 #if defined(CYGPKG_HAL_MIPS)
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316 // In some architectures, the time taken for the next two tests is
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317 // very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
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318 // with a loop over the cache. Hence these tests take longer than the
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319 // testing infrastructure is prepared to wait. The simplest way to get
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320 // these tests to run quickly is to make them think they are running
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321 // under a simulator.
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322 // If the target actually is a simulator, skip the below - it's very
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323 // slow on the simulator, even with reduced loop counts.
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324 if (cyg_test_is_simulator)
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325 CYG_TEST_PASS_FINISH("End of test");
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326
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327 cyg_test_is_simulator = 1;
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328 #endif
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329 #ifdef HAL_ICACHE_INVALIDATE_ALL
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330 HAL_DISABLE_INTERRUPTS(oldints);
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331 HAL_DCACHE_PURGE_ALL();
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332 HAL_ICACHE_INVALIDATE_ALL();
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333 HAL_DCACHE_INVALIDATE_ALL();
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334 HAL_ICACHE_ENABLE();
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335 HAL_DCACHE_ENABLE();
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336 HAL_RESTORE_INTERRUPTS(oldints);
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337 CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
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338 time1II();
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339 #endif
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340 #ifdef HAL_DCACHE_INVALIDATE_ALL
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341 HAL_DISABLE_INTERRUPTS(oldints);
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342 HAL_DCACHE_PURGE_ALL();
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343 HAL_ICACHE_INVALIDATE_ALL();
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344 HAL_DCACHE_INVALIDATE_ALL();
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345 HAL_ICACHE_ENABLE();
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346 HAL_DCACHE_ENABLE();
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347 HAL_RESTORE_INTERRUPTS(oldints);
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348 CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
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349 time1DI();
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350 #endif
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351 #endif // either INVALIDATE_ALL macro
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352
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353 #endif // HAL_CACHE_UNIFIED
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354
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355 CYG_TEST_PASS_FINISH("End of test");
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356 }
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357
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358 // -------------------------------------------------------------------------
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359
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360 void kcache2_main( void )
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361 {
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362 CYG_TEST_INIT();
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363
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364 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache1",
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365 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
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366 cyg_thread_resume(thread[0]);
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367
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368 cyg_scheduler_start();
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369 }
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370
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371 // -------------------------------------------------------------------------
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372
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373 externC void
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374 cyg_start( void )
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375 {
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376 kcache2_main();
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377 }
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378
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379 // -------------------------------------------------------------------------
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380
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381 #else // def CYGFUN_KERNEL_API_C
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382 #define N_A_MSG "Kernel C API layer disabled"
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383 #endif // def CYGFUN_KERNEL_API_C
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384 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
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385 #define N_A_MSG "Kernel real-time clock disabled"
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386 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
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387 #else // def HAL_DCACHE_SIZE
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388 #define N_A_MSG "No caches defined"
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389 #endif // def HAL_DCACHE_SIZE
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390
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391 #ifdef N_A_MSG
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392 externC void
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393 cyg_start( void )
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394 {
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395 CYG_TEST_INIT();
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396 CYG_TEST_NA( N_A_MSG );
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397 }
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398 #endif // N_A_MSG
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399
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400 // -------------------------------------------------------------------------
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401 /* EOF kcache1.c */