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Merge from eCos master repository on 2001-05-18-01:30:05-BST
author jlarmour
date Fri, 18 May 2001 06:32:28 +0000
parents
children d63db767121d
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1 //==========================================================================
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2 //
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3 // dev/if_fec.c
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4 //
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5 // Fast ethernet device driver for PowerPC MPC8xxT boards
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 2001-01-21
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37 // Purpose:
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38 // Description: hardware driver for MPC8xxT FEC
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39 //
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //==========================================================================
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44
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45 // Ethernet device driver for MPC8xx FEC
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46
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47 #include <pkgconf/system.h>
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48 #include <pkgconf/devs_eth_powerpc_fec.h>
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49
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50 #ifdef CYGPKG_NET
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51 #include <pkgconf/net.h>
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52 #endif
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53
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54 #include <cyg/infra/cyg_type.h>
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55 #include <cyg/infra/diag.h>
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56
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57 #include <cyg/hal/hal_arch.h>
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58 #include <cyg/hal/hal_cache.h>
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59 #include <cyg/hal/hal_intr.h>
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60 #include <cyg/hal/drv_api.h>
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61 #include <cyg/hal/hal_if.h>
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62
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63 #include <netdev.h>
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64 #include <eth_drv.h>
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65
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66 #include "fec.h"
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67
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68 static unsigned char fec_eth_rxbufs[CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM+1]
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69 [CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE];
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70 static struct fec_bd fec_eth_rxring[CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM];
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71 static unsigned char fec_eth_txbufs[CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM+1]
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72 [CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE];
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73 static struct fec_bd fec_eth_txring[CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM];
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74
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75 static struct fec_eth_info fec_eth0_info;
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76 static unsigned char _default_enaddr[] = { 0x08, 0x00, 0x3E, 0x28, 0x7A, 0xBA};
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77 static unsigned char enaddr[6];
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78 #ifdef CYGPKG_REDBOOT
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79 #include <pkgconf/redboot.h>
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80 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
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81 #include <redboot.h>
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82 #include <flash_config.h>
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83 RedBoot_config_option("Network hardware address [MAC]",
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84 fec_esa,
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85 ALWAYS_ENABLED, true,
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86 CONFIG_ESA, 0
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87 );
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88 #endif
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89 #endif
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90
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91 #ifdef CYGPKG_REDBOOT
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92 #define os_printf printf
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93 #else
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94 #define os_printf diag_printf
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95 #endif
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96
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97 // For fetching the ESA from RedBoot
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98 #include <cyg/hal/hal_if.h>
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99 #ifndef CONFIG_ESA
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100 #define CONFIG_ESA 6
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101 #endif
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102
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103 ETH_DRV_SC(fec_eth0_sc,
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104 &fec_eth0_info, // Driver specific data
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105 "eth0", // Name for this interface
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106 fec_eth_start,
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107 fec_eth_stop,
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108 fec_eth_control,
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109 fec_eth_can_send,
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110 fec_eth_send,
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111 fec_eth_recv,
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112 fec_eth_deliver,
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113 fec_eth_int,
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114 fec_eth_int_vector);
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115
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116 NETDEVTAB_ENTRY(fec_netdev,
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117 "fec_eth",
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118 fec_eth_init,
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119 &fec_eth0_sc);
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120
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121 #ifdef CYGPKG_NET
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122 static cyg_interrupt fec_eth_interrupt;
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123 static cyg_handle_t fec_eth_interrupt_handle;
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124 #endif
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125 static void fec_eth_int(struct eth_drv_sc *data);
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126
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127 #define FEC_ETH_INT CYGNUM_HAL_INTERRUPT_SIU_LVL1
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128
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129 #ifdef CYGPKG_NET
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130 // This ISR is called when the ethernet interrupt occurs
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131 static int
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132 fec_eth_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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133 {
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134 cyg_drv_interrupt_mask(FEC_ETH_INT);
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135 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Run the DSR
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136 }
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137 #endif
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138
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139 // Deliver function (ex-DSR) handles the ethernet [logical] processing
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140 static void
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141 fec_eth_deliver(struct eth_drv_sc * sc)
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142 {
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143 fec_eth_int(sc);
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144 #ifdef CYGPKG_NET
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145 // Allow interrupts to happen again
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146 cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
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147 cyg_drv_interrupt_unmask(FEC_ETH_INT);
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148 #endif
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149 }
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150
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151 //
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152 // PHY unit access (via MII channel)
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153 //
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154 static void
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155 phy_write(int reg, int addr, unsigned short data)
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156 {
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157 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
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158 volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
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159
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160 fec->iEvent = iEvent_MII;
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161 fec->MiiData = MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data;
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162 while (!(fec->iEvent & iEvent_MII)) ;
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163 }
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164
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165 static unsigned short
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166 phy_read(int reg, int addr)
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167 {
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168 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
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169 volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
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170
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171 fec->iEvent = iEvent_MII;
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172 fec->MiiData = MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA;
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173 while (!(fec->iEvent & iEvent_MII)) ;
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174 return fec->MiiData & 0x0000FFFF;
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175 }
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176
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177 //
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178 // Initialize the interface - performed at system startup
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179 // This function must set up the interface, including arranging to
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180 // handle interrupts, etc, so that it may be "started" cheaply later.
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181 //
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182 static bool
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183 fec_eth_init(struct cyg_netdevtab_entry *tab)
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184 {
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185 struct eth_drv_sc *sc = (struct eth_drv_sc *)tab->device_instance;
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186 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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187 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
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188 volatile struct fec *fec = (volatile struct fec *)((unsigned char *)eppc + FEC_OFFSET);
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189 struct fec_bd *rxbd, *txbd;
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190 unsigned char *RxBUF, *TxBUF;
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191 unsigned short phy_state = 0;
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192 int cache_state;
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193 int i;
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194 unsigned long proc_rev;
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195 bool esa_ok;
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196
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197 // Ensure consistent state between cache and what the FEC sees
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198 HAL_DCACHE_IS_ENABLED(cache_state);
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199 HAL_DCACHE_SYNC();
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200 HAL_DCACHE_DISABLE();
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201
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202 qi->fec = fec;
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203
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204 #ifdef CYGPKG_NET
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205 // Set up to handle interrupts
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206 cyg_drv_interrupt_create(FEC_ETH_INT,
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207 CYGARC_SIU_PRIORITY_HIGH,
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208 (cyg_addrword_t)sc, // Data item passed to interrupt handler
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209 (cyg_ISR_t *)fec_eth_isr,
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210 (cyg_DSR_t *)eth_drv_dsr,
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211 &fec_eth_interrupt_handle,
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212 &fec_eth_interrupt);
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213 cyg_drv_interrupt_attach(fec_eth_interrupt_handle);
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214 cyg_drv_interrupt_acknowledge(FEC_ETH_INT);
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215 cyg_drv_interrupt_unmask(FEC_ETH_INT);
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216 #endif
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217
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218 // Shut down ethernet, in case it is already running
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219 fec->eControl = eControl_RESET;
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220 eppc->pip_pbdat &= ~0x00004000; // Reset PHY chip
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221 CYGACC_CALL_IF_DELAY_US(1000); // 1ms
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222 eppc->pip_pbdat |= 0x00004000; // Enable PHY chip
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223
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224 fec->iMask = 0x0000000; // Disables all interrupts
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225 fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
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226 fec->iVector = (1<<29); // Caution - must match FEC_ETH_INT above
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227
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228 txbd = fec_eth_txring;
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229 rxbd = fec_eth_rxring;
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230 qi->tbase = txbd;
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231 qi->txbd = txbd;
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232 qi->tnext = txbd;
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233 qi->rbase = rxbd;
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234 qi->rxbd = rxbd;
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235 qi->rnext = rxbd;
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236
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237 #define ROUNDUP(b,s) (((unsigned long)(b) + (s-1)) & ~(s-1))
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238 RxBUF = (unsigned char *)ROUNDUP(&fec_eth_rxbufs[0][0], 32);
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239 TxBUF = (unsigned char *)ROUNDUP(&fec_eth_txbufs[0][0], 32);
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240
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241 // setup buffer descriptors
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242 for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_RxNUM; i++) {
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243 rxbd->length = 0;
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244 rxbd->buffer = RxBUF;
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245 rxbd->ctrl = FEC_BD_Rx_Empty;
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246 RxBUF += CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
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247 rxbd++;
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248 }
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249 rxbd--;
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250 rxbd->ctrl |= FEC_BD_Rx_Wrap; // Last buffer
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251 for (i = 0; i < CYGNUM_DEVS_ETH_POWERPC_FEC_TxNUM; i++) {
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252 txbd->length = 0;
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253 txbd->buffer = TxBUF;
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254 txbd->ctrl = 0;
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255 TxBUF += CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
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256 txbd++;
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257 }
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258 txbd--;
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259 txbd->ctrl |= FEC_BD_Tx_Wrap; // Last buffer
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260
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261 // Set up parallel port for connection to ethernet tranceiver
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262 eppc->pio_pdpar = 0x1FFF;
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263 asm volatile ("mfspr %0,638 \n\t" : "=r" (proc_rev) : );
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264 #define PROC_REVB 0x0020
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265 if ((proc_rev & 0x0000FFFF) == PROC_REVB) {
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266 eppc->pio_pddir = 0x1C58;
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267 } else {
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268 eppc->pio_pddir = 0x1FFF;
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269 }
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270
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271 // Reset interrupts
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272 fec->iMask = 0x00000000; // No interrupts enabled
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273 fec->iEvent = 0xFFFFFFFF; // Clear all interrupts
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274
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275 // Initialize shared PRAM
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276 fec->RxRing = fec_eth_rxring;
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277 fec->TxRing = fec_eth_txring;
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278
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279 // Size of receive buffers
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280 fec->RxBufSize = CYGNUM_DEVS_ETH_POWERPC_FEC_BUFSIZE;
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281
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282 // Receiver control
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283 fec->RxControl = RxControl_MII | RxControl_DRT;
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284 // fec->RxControl = RxControl_MII | RxControl_LOOP | RxControl_PROM;
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285 fec->RxHash = IEEE_8023_MAX_FRAME; // Largest possible ethernet frame
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286
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287 // Transmit control
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288 fec->TxControl = 0;
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289
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290 // Use largest possible Tx FIFO
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291 fec->TxWater = 3;
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292
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293 // DMA control
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294 fec->FunCode = ((2<<29) | (2<<27) | (0<<24));
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295
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296 // MII speed control (50MHz)
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297 fec->MiiSpeed = 0x14;
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298
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299 // Group address hash
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300 fec->hash[0] = 0;
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301 fec->hash[1] = 0;
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302
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303 // Device physical address
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304 #ifdef CYGPKG_REDBOOT
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305 esa_ok = flash_get_config("fec_esa", enaddr, CONFIG_ESA);
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306 #else
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307 esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
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308 "fec_esa", enaddr, CONFIG_ESA);
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309 #endif
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310 if (!esa_ok) {
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311 // Can't figure out ESA
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312 diag_printf("FEC_ETH - Warning! ESA unknown\n");
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313 memcpy(&enaddr, &_default_enaddr, sizeof(enaddr));
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314 }
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315 memcpy((void *)&fec->addr[0], &enaddr[0], sizeof(enaddr));
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316 // os_printf("FEC ESA = %08x/%08x\n", fec->addr[0], fec->addr[1]);
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317
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318 // Enable device
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319 fec->eControl = eControl_EN | eControl_MUX;
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320
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321 // Enable transceiver (PHY)
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322 phy_write(PHY_BMCR, 0, PHY_BMCR_RESET);
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323 for (i = 0; i < 10; i++) {
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324 phy_state = phy_read(PHY_BMCR, 0);
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325 if (!(phy_state & PHY_BMCR_RESET)) break;
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326 }
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327 if (phy_state & PHY_BMCR_RESET) {
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328 os_printf("FEC: Can't get PHY unit to reset: %x\n", phy_state);
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329 return false;
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330 }
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331 phy_write(PHY_BMCR, 0, PHY_BMCR_AUTO_NEG);
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332 // os_printf("MII: %x/%x\n", phy_state, phy_read(PHY_BMCR, 0));
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333
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334 #ifdef CYGPKG_NET
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335 // Set up for interrupts
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336 fec->iMask = iEvent_all & ~iEvent_MII;
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337 #endif
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338
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339 if (cache_state)
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340 HAL_DCACHE_ENABLE();
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341
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342 // Initialize upper level driver
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343 (sc->funs->eth_drv->init)(sc, (unsigned char *)&enaddr);
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344
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345 return true;
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346 }
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347
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348 //
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349 // This function is called to shut down the interface.
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350 //
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351 static void
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352 fec_eth_stop(struct eth_drv_sc *sc)
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353 {
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354 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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355
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356 // Disable the device!
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357 qi->fec->eControl &= ~eControl_EN;
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358 }
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359
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360 //
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361 // This function is called to "start up" the interface. It may be called
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362 // multiple times, even when the hardware is already running. It will be
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363 // called whenever something "hardware oriented" changes and should leave
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364 // the hardware ready to send/receive packets.
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365 //
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366 static void
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367 fec_eth_start(struct eth_drv_sc *sc, unsigned char *enaddr, int flags)
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368 {
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369 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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370
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371 // Enable the device!
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372 qi->fec->eControl |= eControl_EN;
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373 qi->fec->RxUpdate = 0x0F0F0F0F; // Any write tells machine to look for work
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374 }
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375
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376 //
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377 // This function is called for low level "control" operations
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378 //
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379 static int
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380 fec_eth_control(struct eth_drv_sc *sc, unsigned long key,
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381 void *data, int length)
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382 {
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383 switch (key) {
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384 case ETH_DRV_SET_MAC_ADDRESS:
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385 return 0;
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386 break;
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387 default:
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388 return 1;
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389 break;
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390 }
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391 }
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392
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393 //
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394 // This function is called to see if another packet can be sent.
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395 // It should return the number of packets which can be handled.
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396 // Zero should be returned if the interface is busy and can not send any more.
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397 //
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398 static int
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399 fec_eth_can_send(struct eth_drv_sc *sc)
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400 {
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401 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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402 volatile struct fec_bd *txbd = qi->txbd;
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403
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404 return ((txbd->ctrl & FEC_BD_Tx_Ready) == 0);
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405 }
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406
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407 //
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408 // This routine is called to send data to the hardware.
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409 static void
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410 fec_eth_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len,
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411 int total_len, unsigned long key)
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412 {
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413 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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414 volatile struct fec_bd *txbd, *txfirst;
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415 volatile char *bp;
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416 int i, txindex, cache_state;
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417
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418 // Find a free buffer
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419 txbd = txfirst = qi->txbd;
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420 while (txbd->ctrl & FEC_BD_Tx_Ready) {
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421 // This buffer is busy, move to next one
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422 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
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423 txbd = qi->tbase;
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424 } else {
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425 txbd++;
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426 }
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427 if (txbd == txfirst) {
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428 #ifdef CYGPKG_NET
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429 panic ("No free xmit buffers");
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430 #else
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431 os_printf("FEC Ethernet: No free xmit buffers\n");
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432 #endif
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433 }
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434 }
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435 // Remember the next buffer to try
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436 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
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437 qi->txbd = qi->tbase;
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438 } else {
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439 qi->txbd = txbd+1;
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440 }
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441 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
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442 qi->txkey[txindex] = key;
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443 // Set up buffer
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444 txbd->length = total_len;
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445 bp = txbd->buffer;
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446 for (i = 0; i < sg_len; i++) {
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447 memcpy((void *)bp, (void *)sg_list[i].buf, sg_list[i].len);
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448 bp += sg_list[i].len;
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449 }
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450 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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451 HAL_DCACHE_IS_ENABLED(cache_state);
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452 if (cache_state) {
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453 HAL_DCACHE_FLUSH(txbd->buffer, txbd->length); // Make sure no stale data
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454 }
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455 // Send it on it's way
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456 txbd->ctrl |= FEC_BD_Tx_Ready | FEC_BD_Tx_Last | FEC_BD_Tx_TC;
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457 if (cache_state) {
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458 HAL_DCACHE_FLUSH(fec_eth_txring, sizeof(fec_eth_txring)); // Make sure no stale data
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459 }
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460 qi->fec->TxUpdate = 0x0F0F0F0F; // Any write tells machine to look for work
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461 }
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462
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463 //
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464 // This function is called when a packet has been received. It's job is
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465 // to prepare to unload the packet from the hardware. Once the length of
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466 // the packet is known, the upper layer of the driver can be told. When
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467 // the upper layer is ready to unload the packet, the internal function
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468 // 'fec_eth_recv' will be called to actually fetch it from the hardware.
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469 //
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470 static void
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471 fec_eth_RxEvent(struct eth_drv_sc *sc)
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472 {
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473 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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474 volatile struct fec_bd *rxbd;
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475 int cache_state;
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476
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477 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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478 HAL_DCACHE_IS_ENABLED(cache_state);
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479 if (cache_state) {
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480 HAL_DCACHE_FLUSH(fec_eth_rxring, sizeof(fec_eth_rxring)); // Make sure no stale data
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481 }
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482 rxbd = qi->rnext;
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483 while ((rxbd->ctrl & FEC_BD_Rx_Empty) == 0) {
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484 qi->rxbd = rxbd; // Save for callback
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485 (sc->funs->eth_drv->recv)(sc, rxbd->length);
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486 rxbd->ctrl |= FEC_BD_Rx_Empty;
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487 if (rxbd->ctrl & FEC_BD_Rx_Wrap) {
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488 rxbd = qi->rbase;
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489 } else {
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490 rxbd++;
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491 }
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492 }
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493 // Remember where we left off
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494 qi->rnext = (struct fec_bd *)rxbd;
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495 if (cache_state) {
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496 HAL_DCACHE_FLUSH(fec_eth_rxring, sizeof(fec_eth_rxring)); // Make sure no stale data
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497 }
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498 qi->fec->RxUpdate = 0x0F0F0F0F; // Any write tells machine to look for work
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499 }
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500
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501 //
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502 // This function is called as a result of the "eth_drv_recv()" call above.
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503 // It's job is to actually fetch data for a packet from the hardware once
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504 // memory buffers have been allocated for the packet. Note that the buffers
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505 // may come in pieces, using a scatter-gather list. This allows for more
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506 // efficient processing in the upper layers of the stack.
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507 //
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508 static void
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509 fec_eth_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
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510 {
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511 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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512 unsigned char *bp;
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513 int i, cache_state;
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514
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515 bp = (unsigned char *)qi->rxbd->buffer;
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516 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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517 HAL_DCACHE_IS_ENABLED(cache_state);
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518 if (cache_state) {
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519 HAL_DCACHE_INVALIDATE(qi->rxbd->buffer, qi->rxbd->length); // Make sure no stale data
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520 }
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521 for (i = 0; i < sg_len; i++) {
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522 if (sg_list[i].buf != 0) {
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523 memcpy((void *)sg_list[i].buf, bp, sg_list[i].len);
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524 bp += sg_list[i].len;
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525 }
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526 }
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527 }
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528
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529 static void
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530 fec_eth_TxEvent(struct eth_drv_sc *sc, int stat)
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531 {
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532 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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533 volatile struct fec_bd *txbd;
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534 int txindex, cache_state;
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535
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536 HAL_DCACHE_IS_ENABLED(cache_state);
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537 if (cache_state) {
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538 HAL_DCACHE_FLUSH(fec_eth_txring, sizeof(fec_eth_txring)); // Make sure no stale data
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539 }
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540 txbd = qi->tnext;
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541 // Note: TC field is used to indicate the buffer has/had data in it
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542 while ((txbd->ctrl & (FEC_BD_Tx_Ready|FEC_BD_Tx_TC)) == FEC_BD_Tx_TC) {
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543 txindex = ((unsigned long)txbd - (unsigned long)qi->tbase) / sizeof(*txbd);
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544 (sc->funs->eth_drv->tx_done)(sc, qi->txkey[txindex], 0);
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545 txbd->ctrl &= ~FEC_BD_Tx_TC;
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546 if (txbd->ctrl & FEC_BD_Tx_Wrap) {
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547 txbd = qi->tbase;
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548 } else {
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549 txbd++;
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550 }
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551 }
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552 // Remember where we left off
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553 qi->tnext = (struct fec_bd *)txbd;
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554 if (cache_state) {
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555 HAL_DCACHE_FLUSH(fec_eth_txring, sizeof(fec_eth_txring)); // Make sure no stale data
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556 }
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557 }
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558
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559 //
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560 // Interrupt processing
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561 //
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562 static void
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563 fec_eth_int(struct eth_drv_sc *sc)
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564 {
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565 struct fec_eth_info *qi = (struct fec_eth_info *)sc->driver_private;
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566 unsigned long event;
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567
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568 while ((event = qi->fec->iEvent) != 0) {
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569 if ((event & iEvent_TFINT) != 0) {
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570 fec_eth_TxEvent(sc, event);
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571 }
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572 if ((event & iEvent_RFINT) != 0) {
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573 fec_eth_RxEvent(sc);
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574 }
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575 qi->fec->iEvent = event; // Reset the bits we handled
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576 }
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577 }
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578
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579 //
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580 // Interrupt vector
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581 //
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582 static int
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583 fec_eth_int_vector(struct eth_drv_sc *sc)
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584 {
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585 return (FEC_ETH_INT);
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586 }
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587