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annotate packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.h @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
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children e0c0827131d1
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1 #ifndef CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
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2 #define CYGONCE_POWERPC_QUICC_SMC_SERIAL_H
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3
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4 // ====================================================================
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5 //
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6 // quicc_smc_serial.h
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7 //
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8 // Device I/O - Description of PowerPC QUICC/SMC serial hardware
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9 //
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10 // ====================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 // ====================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): gthomas
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38 // Contributors: gthomas
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39 // Date: 1999-06-21
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40 // Purpose: Internal interfaces for serial I/O drivers
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41 // Description:
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42 //
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43 //####DESCRIPTIONEND####
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44 //
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45 // ====================================================================
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46
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47 // Description of serial ports using QUICC/SMC
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48
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49 #include <cyg/hal/quicc/ppc8xx.h> // QUICC structure definitions
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50
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51 static unsigned int select_word_length[] = {
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52 QUICC_SMCMR_CLEN(5), // 5 bits / word (char)
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53 QUICC_SMCMR_CLEN(6),
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54 QUICC_SMCMR_CLEN(7),
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55 QUICC_SMCMR_CLEN(8)
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56 };
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57
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58 static unsigned int select_stop_bits[] = {
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59 0,
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60 QUICC_SMCMR_SB(1), // 1 stop bit
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61 QUICC_SMCMR_SB(1), // 1.5 stop bit
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62 QUICC_SMCMR_SB(2) // 2 stop bits
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63 };
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64
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65 static unsigned int select_parity[] = {
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66 QUICC_SMCMR_PE(0), // No parity
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67 QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(1), // Even parity
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68 QUICC_SMCMR_PE(1)|QUICC_SMCMR_PM(0), // Odd parity
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69 0, // Mark parity
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70 0, // Space parity
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71 };
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72
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73 // Baud rate values, based on board clock
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74
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75 static cyg_int32 select_baud[] = {
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76 0, // Unused
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77 50, // 50
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78 75, // 75
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79 110, // 110
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80 0, // 134.5
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81 150, // 150
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82 200, // 200
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83 300, // 300
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84 600, // 600
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85 1200, // 1200
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86 1800, // 1800
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87 2400, // 2400
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88 3600, // 3600
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89 4800, // 4800
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90 7200, // 7200
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91 9600, // 9600
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92 14400, // 14400
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93 19200, // 19200
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94 38400, // 38400
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95 57600, // 57600
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96 115200, // 115200
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97 0, // 230400
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98 };
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99
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100 #define UART_BITRATE(n) (((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/16)/n)
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101 #define UART_SLOW_BITRATE(n) ((CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000)/n))
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102
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103 #endif // CYGONCE_POWERPC_QUICC_SMC_SERIAL_H