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annotate packages/hal/sh/arch/current/include/sh3_scif.inl @ 82:6736c52df507 ecos-sw-2000-04-14

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Merge from eCos master repository on 2000-04-14-13:35:46-BST
author jlarmour
date Tue, 18 Apr 2000 21:51:55 +0000
parents 2085233a121a
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1 #ifndef CYGONCE_HAL_SH3_SCIF_H
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2 #define CYGONCE_HAL_SH3_SCIF_H
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3 //=============================================================================
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4 //
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5 // sh3_scif.inl
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6 //
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7 // Simple driver for the SH3 Serial Communication Interface with FIFO
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8 //
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9 //=============================================================================
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10 //####COPYRIGHTBEGIN####
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11 //
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12 // -------------------------------------------
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13 // The contents of this file are subject to the Red Hat eCos Public License
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14 // Version 1.1 (the "License"); you may not use this file except in
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15 // compliance with the License. You may obtain a copy of the License at
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16 // http://www.redhat.com/
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17 //
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18 // Software distributed under the License is distributed on an "AS IS"
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19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 // License for the specific language governing rights and limitations under
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21 // the License.
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22 //
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23 // The Original Code is eCos - Embedded Configurable Operating System,
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24 // released September 30, 1998.
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25 //
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26 // The Initial Developer of the Original Code is Red Hat.
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27 // Portions created by Red Hat are
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28 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 // All Rights Reserved.
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30 // -------------------------------------------
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31 //
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32 //####COPYRIGHTEND####
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33 //=============================================================================
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34 //#####DESCRIPTIONBEGIN####
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35 //
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36 // Author(s): jskov
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37 // Contributors:jskov
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38 // Date: 2000-03-30
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39 // Description: Simple driver for the SH Serial Communication Interface
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40 // The driver can be used for either the SCIF or the IRDA
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41 // modules (the latter can act as the former).
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42 // Clients of this file can configure the behavior with:
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43 // CYG_SCIF_IRDA: if used for IrDA instead of SCIF
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44 // CYG_SCIF_PUBLIC: define to export init, get, and put functions.
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45 // CYG_SCIF_STUB: define to get extra stub functions
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46 // CYG_SCIF_NAME_PREFIX: Function prefix. Default is hal_sci_
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47 // Using different prefixes can be required
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48 // if both serial ports are used from the
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49 // same source file.
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50 //####DESCRIPTIONEND####
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51 //
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52 //=============================================================================
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53
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54 #include <pkgconf/hal.h>
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55
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56 #include <cyg/hal/hal_io.h> // IO macros
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57 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
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58 #include <cyg/hal/sh_regs.h> // serial register definitions
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59
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60 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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61 #include <cyg/hal/sh_stub.h> // target_register_t
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62 #endif
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63
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64 // Unless explicitly asked to export functions, keep them local.
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65 #ifndef CYG_SCIF_PUBLIC
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66 #define CYG_SCIF_PUBLIC static
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67 #endif
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68
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69 // Function names are prefix with hal_sci_ unless something else is specified.
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70 #ifndef CYG_SCIF_NAME_PREFIX
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71 #define CYG_SCIF_NAME_PREFIX hal_scif_
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72 #endif
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73
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74 //-----------------------------------------------------------------------------
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75 // Register base.
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76 // Can be used to drive either the IrDA controller or the SCIF controller
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77 #ifdef CYG_SCIF_IRDA
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78 # define SC_BASE (CYGARC_REG_SCSMR1)
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79 #else
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80 # define SC_BASE (CYGARC_REG_SCSMR2)
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81 #endif
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82
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83 #define _SCSMR (SC_BASE+0)
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84 #define _SCBRR (SC_BASE+2)
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85 #define _SCSCR (SC_BASE+4)
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86 #define _SCFTDR (SC_BASE+6)
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87 #define _SCSSR (SC_BASE+8)
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88 #define _SCFRDR (SC_BASE+10)
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89 #define _SCFCR (SC_BASE+12)
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90 #define _SCFDR (SC_BASE+14)
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91
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92 //-----------------------------------------------------------------------------
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93 // Name Conversion magic.
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94 #define Str(x, y) x ## y
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95 #define Xstr(x, y) Str(x, y)
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96 #define NC(_name) Xstr(CYG_SCIF_NAME_PREFIX, _name)
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97
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98 //-----------------------------------------------------------------------------
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99 // The exported functions.
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100 // Base:
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101 CYG_SCIF_PUBLIC void NC(init_serial)( void );
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102 CYG_SCIF_PUBLIC int NC(get_char)( void );
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103 CYG_SCIF_PUBLIC void NC(put_char)( int c );
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104 // GDB BREAK support:
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105 #if defined(CYG_SCIF_STUB) && defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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106 int NC(interruptible)( int state );
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107 void NC(init_break_irq)( void );
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108 int cyg_hal_gdb_isr( target_register_t pc ); // called from vectors.S
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109 #endif
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110
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111 //-----------------------------------------------------------------------------
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112 // The minimal init, get and put functions. All by polling.
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113
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114 CYG_SCIF_PUBLIC void NC(init_serial)( void )
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115 {
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116 cyg_uint16 sr;
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117
80
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118 // Disable interrupts.
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119 #ifdef CYG_SCIF_IRDA
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120 // Note: This affects out all IRDA sources, not only RXI1.
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121 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_IRDA_RXI1);
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122 #else
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123 // Note: This affects out all SCIF sources, not only RXI2.
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124 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SCIF_RXI2);
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125 #endif
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126
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127 // Disable everything.
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128 HAL_WRITE_UINT8(_SCSCR, 0);
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129
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130 // Reset FIFO.
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131 HAL_WRITE_UINT8(_SCFCR, CYGARC_REG_SCFCR2_TFRST|CYGARC_REG_SCFCR2_RFRST);
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132
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133 #ifdef CYG_SCIF_IRDA
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134 // 8-1-no parity, clear IRMOD.
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135 HAL_WRITE_UINT8(_SCSMR, 0);
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136 #else
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137 // 8-1-no parity.
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138 HAL_WRITE_UINT8(_SCSMR, 0);
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139 #endif
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140
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141 #ifndef CYG_HAL_STARTUP_RAM
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142 {
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143 // Set speed to 38400 - but only if configured for ROM; if
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144 // configured for RAM, we could be hosted by either the eCos
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145 // stub (running 38400, already initialized) or the Hitachi
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146 // ROM (running 9600 - reinitializing to 38400 would cause GDB
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147 // to lose the connection).
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148 cyg_uint8 tmp;
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149 HAL_READ_UINT8(_SCSMR, tmp);
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150 tmp &= ~CYGARC_REG_SCSMR2_CKSx_MASK;
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151 tmp |= CYGARC_SCBRR2_CKSx(38400);
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152 HAL_WRITE_UINT8(_SCSMR, tmp);
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153 HAL_WRITE_UINT8(_SCBRR, CYGARC_SCBRR2_N(38400));
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154 }
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155 #endif
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156
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157 // Let things settle: Here we should should wait the equivalent of
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158 // one bit interval, i.e. 1/38400 second, but until we have
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159 // something like the Linux jiffies, it's hard to do reliably. So
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160 // just move on and hope for the best (this is unlikely to cause
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161 // problems since the CPU has just come out of reset anyway).
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162
82
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163 // Clear status register (read back first).
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164 HAL_READ_UINT16(_SCSSR, sr);
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165 HAL_WRITE_UINT16(_SCSSR, 0);
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166
80
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167 // Bring FIFO out of reset and set to trigger on every char in
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168 // FIFO (or C-c input would not be processed).
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169 HAL_WRITE_UINT8(_SCFCR, CYGARC_REG_SCFCR2_RTRG_1|CYGARC_REG_SCFCR2_TTRG_1);
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170
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171 // Leave Tx/Rx interrupts disabled, but enable Tx/Rx
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172 HAL_WRITE_UINT8(_SCSCR, CYGARC_REG_SCSCR2_TE|CYGARC_REG_SCSCR2_RE);
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173 }
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174
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175 CYG_SCIF_PUBLIC int NC(get_char)( void )
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176 {
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177 cyg_uint8 c;
82
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178 cyg_uint16 fdr, sr;
80
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179
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180 do {
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181 HAL_READ_UINT16(_SCFDR, fdr);
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182 } while ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) == 0);
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183
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184 HAL_READ_UINT8(_SCFRDR, c);
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185
82
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186 // Clear FIFO full flag (read before clearing)
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187 HAL_READ_UINT16(_SCSSR, sr);
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188 HAL_WRITE_UINT16(_SCSSR,
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189 CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF);
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190
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191 return c;
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192 }
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193
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194 CYG_SCIF_PUBLIC void NC(put_char)( int c )
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195 {
82
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196 cyg_uint16 fdr, sr;
80
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197
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198 do {
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199 HAL_READ_UINT16(_SCFDR, fdr);
82
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200 } while (((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) >> CYGARC_REG_SCFDR2_TCOUNT_shift) == 16);
80
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201
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202 HAL_WRITE_UINT8(_SCFTDR, c);
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203
82
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204 // Clear FIFO-empty/transmit end flags (read back SR first)
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205 HAL_READ_UINT16(_SCSSR, sr);
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206 HAL_WRITE_UINT16(_SCSSR, CYGARC_REG_SCSSR2_CLEARMASK
80
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207 & ~(CYGARC_REG_SCSSR2_TDFE | CYGARC_REG_SCSSR2_TEND ));
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208
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209 // Hang around until the character has been safely sent.
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210 do {
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211 HAL_READ_UINT16(_SCFDR, fdr);
82
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212 } while ((fdr & CYGARC_REG_SCFDR2_TCOUNT_MASK) != 0);
80
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213 }
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214
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215
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216 //-----------------------------------------------------------------------------
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217 // Additional functions required to provide GDB BREAK support.
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218
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219 #if defined(CYG_SCIF_STUB) && defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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220 int NC(interruptible)( int state )
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221 {
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222 if (state) {
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223 #ifdef CYG_SCIF_IRDA
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224 // Note: This affects out all IRDA sources, not only RXI1.
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225 HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_IRDA_RXI1);
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226 #else
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227 // Note: This affects out all SCIF sources, not only RXI2.
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228 HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SCIF_RXI2);
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229 #endif
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230 } else {
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231 #ifdef CYG_SCIF_IRDA
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232 // Note: This affects out all IRDA sources, not only RXI1.
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233 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_IRDA_RXI1);
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234 #else
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235 // Note: This affects out all SCIF sources, not only RXI2.
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236 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SCIF_RXI2);
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237 #endif
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238 }
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239
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240 return 0;
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241 }
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242
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243 void NC(init_break_irq)( void )
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244 {
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245 cyg_uint8 scr;
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246
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247 NC(interruptible)(0);
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248
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249 // Enable serial receive interrupts.
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250
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251 // Enable Rx interrupts
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252 HAL_READ_UINT8(_SCSCR, scr);
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253 scr |= CYGARC_REG_SCSCR2_RIE;
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254 HAL_WRITE_UINT8(_SCSCR, scr);
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255 HAL_ENABLE_INTERRUPTS();
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256
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257 NC(interruptible)(1);
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258 }
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259
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260 // This ISR is called from the interrupt handler.
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261 int cyg_hal_gdb_isr( target_register_t pc )
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262 {
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263 cyg_uint8 c;
82
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264 cyg_uint16 fdr, sr;
80
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265
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266 HAL_READ_UINT16(_SCFDR, fdr);
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267 if ((fdr & CYGARC_REG_SCFDR2_RCOUNT_MASK) != 0) {
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268 HAL_READ_UINT8(_SCFRDR, c);
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269
82
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270 // Clear buffer full flag (read back first).
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271 HAL_READ_UINT16(_SCSSR, sr);
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272 HAL_WRITE_UINT16(_SCSSR,
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273 CYGARC_REG_SCSSR2_CLEARMASK & ~CYGARC_REG_SCSSR2_RDF);
80
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274
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275 if ( 3 == c )
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276 {
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277 // Ctrl-C: set a breakpoint at PC so GDB will display the
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278 // correct program context when stopping rather than the
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279 // interrupt handler.
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280 cyg_hal_gdb_interrupt( pc );
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281 }
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282
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283 // Interrupt handled. Don't call ISR proper. At return
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284 // from the VSR, execution will stop at the breakpoint
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285 // just set.
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286 return 0;
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287 }
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288
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289 // Not caused by GDB. Call ISR proper.
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290 return 1;
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291 }
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292
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293 #endif
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294
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295 //-----------------------------------------------------------------------------
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296 // Undefine all macros used in this file.
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297 #undef CYG_SCIF_IRDA
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298 #undef CYG_SCIF_PUBLIC
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299 #undef CYG_SCIF_STUB
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300 #undef CYG_SCIF_NAME_PREFIX
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301 #undef NC
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302 #undef Str
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303 #undef Xstr
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304
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305 //-----------------------------------------------------------------------------
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306 // end of sh3_scif.inl
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307 #endif // CYGONCE_HAL_SH3_SCIF_INL