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Merge from eCos master repository on 2001-10-19-06:43:02-BST
author jlarmour
date Fri, 19 Oct 2001 07:02:26 +0000
parents 0d2b193a635f
children e0c0827131d1
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1 //==========================================================================
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2 //
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3 // devs_eth_cf.inl
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4 //
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5 // CF (PCMCIA) ethernet I/O definitions.
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors:jskov
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36 // Date: 2001-06-15
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37 // Purpose: PCMCIA ethernet defintions
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38 //
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39 //####DESCRIPTIONEND####
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40 //==========================================================================
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41
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42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
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43 #include <cyg/hal/hal_if.h>
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44 #include <cyg/infra/cyg_type.h>
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45 #include <cyg/io/pcmcia.h>
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46
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47 #ifdef __WANT_CONFIG
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48
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49 #undef CYGHWR_NS_DP83902A_PLF_INT_CLEAR
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50 #define CYGHWR_NS_DP83902A_PLF_INT_CLEAR(_dp_) \
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51 CYG_MACRO_START \
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52 struct cf_slot* slot = (struct cf_slot*) (_dp_)->plf_priv; \
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53 cf_clear_interrupt(slot); \
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54 CYG_MACRO_END
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55
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56 #endif // __WANT_CONFIG
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57
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58 #ifdef __WANT_DEVS
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59
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60 externC int cyg_sc_lpe_int_vector(struct eth_drv_sc *sc);
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61 externC bool cyg_sc_lpe_init(struct cyg_netdevtab_entry *tab);
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62
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63 #ifdef CYGPKG_DEVS_ETH_CF_ETH0
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64
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65 static dp83902a_priv_data_t dp83902a_eth0_priv_data = {
191
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66 tx_buf1: 0x40,
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67 tx_buf2: 0x48,
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68 rx_buf_start: 0x50,
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69 rx_buf_end: 0x80,
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70 #ifdef CYGSEM_DEVS_ETH_CF_ETH0_SET_ESA
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71 esa : CYGDAT_DEVS_ETH_CF_ETH0_ESA,
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72 hardwired_esa : true,
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73 #else
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74 hardwired_esa : false,
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75 #endif
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76 };
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77
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78 ETH_DRV_SC(dp83902a_sc,
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79 &dp83902a_eth0_priv_data, // Driver specific data
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80 CYGDAT_DEVS_ETH_CF_ETH0_NAME,
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81 dp83902a_start,
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82 dp83902a_stop,
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83 dp83902a_control,
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84 dp83902a_can_send,
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85 dp83902a_send,
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86 dp83902a_recv,
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87 dp83902a_deliver, // "pseudoDSR" called from fast net thread
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88 dp83902a_poll, // poll function, encapsulates ISR and DSR
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89 cyg_sc_lpe_int_vector);
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90
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91 NETDEVTAB_ENTRY(dp83902a_netdev,
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92 "dp83902a_" CYGDAT_DEVS_ETH_CF_ETH0_NAME,
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93 cyg_sc_lpe_init,
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94 &dp83902a_sc);
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95 #endif // CYGPKG_DEVS_ETH_CF_ETH0
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96
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97 #endif // __WANT_DEVS
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98
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99 // EOF devs_eth_cf.inl