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annotate packages/devs/serial/powerpc/quicc/current/src/quicc_smc_serial.c @ 143:6b5f480c6929 ecos-sw-2000-12-08

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Merge from eCos master repository on 2000-12-08-02:09:36-GMT
author jlarmour
date Fri, 08 Dec 2000 03:30:06 +0000
parents 0ae0bc38e387
children 2e9a636d9de9
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1 //==========================================================================
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2 //
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3 // io/serial/powerpc/quicc_smc_serial.c
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4 //
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5 // PowerPC QUICC (SMC) Serial I/O Interface Module (interrupt driven)
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-06-20
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37 // Purpose: QUICC SMC Serial I/O module (interrupt driven version)
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38 // Description:
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //==========================================================================
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43
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44 #include <pkgconf/system.h>
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45 #include <pkgconf/io_serial.h>
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46 #include <pkgconf/io.h>
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47 #include <cyg/io/io.h>
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48 #include <cyg/hal/hal_intr.h>
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49 #include <cyg/io/devtab.h>
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50 #include <cyg/io/serial.h>
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51 #include <cyg/infra/diag.h>
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52 #include <cyg/hal/hal_cache.h>
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53 #include CYGBLD_HAL_PLATFORM_H
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54
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55 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
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56
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57 // Buffer descriptor control bits
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58 #define QUICC_BD_CTL_Ready 0x8000 // Buffer contains data (tx) or is empty (rx)
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59 #define QUICC_BD_CTL_Wrap 0x2000 // Last buffer in list
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60 #define QUICC_BD_CTL_Int 0x1000 // Generate interrupt when empty (tx) or full (rx)
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61 #define QUICC_BD_CTL_MASK 0xB000 // User settable bits
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62
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63 // SMC Mode Register
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64 #define QUICC_SMCMR_CLEN(n) ((n+1)<<11) // Character length
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65 #define QUICC_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
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66 #define QUICC_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
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67 #define QUICC_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
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68 #define QUICC_SMCMR_UART (2<<4) // UART mode
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69 #define QUICC_SMCMR_TEN (1<<1) // Enable transmitter
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70 #define QUICC_SMCMR_REN (1<<0) // Enable receiver
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71
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72 // SMC Events (interrupts)
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73 #define QUICC_SMCE_BRK 0x10 // Break received
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74 #define QUICC_SMCE_BSY 0x04 // Busy - receive buffer overrun
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75 #define QUICC_SMCE_TX 0x02 // Tx interrupt
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76 #define QUICC_SMCE_RX 0x01 // Rx interrupt
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77
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78 // SMC Commands
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79 #define QUICC_SMC_CMD_InitTxRx (0<<8)
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80 #define QUICC_SMC_CMD_InitTx (1<<8)
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81 #define QUICC_SMC_CMD_InitRx (2<<8)
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82 #define QUICC_SMC_CMD_StopTx (4<<8)
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83 #define QUICC_SMC_CMD_RestartTx (6<<8)
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84 #define QUICC_SMC_CMD_Reset 0x8000
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85 #define QUICC_SMC_CMD_Go 0x0001
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86
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87 #include "quicc_smc_serial.h"
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88
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89 typedef struct quicc_smc_serial_info {
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90 CYG_ADDRWORD channel; // Which channel SMC1/SMC2
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91 CYG_WORD int_num; // Interrupt number
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92 cyg_uint32 *brg; // Which baud rate generator
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93 volatile struct smc_uart_pram *pram; // Parameter RAM pointer
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94 volatile struct smc_regs *ctl; // SMC control registers
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95 volatile struct cp_bufdesc *txbd, *rxbd; // Next Tx,Rx descriptor to use
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96 struct cp_bufdesc *tbase, *rbase; // First Tx,Rx descriptor
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97 int txsize, rxsize; // Length of individual buffers
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98 cyg_interrupt serial_interrupt;
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99 cyg_handle_t serial_interrupt_handle;
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100 } quicc_smc_serial_info;
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101
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102 static bool quicc_smc_serial_init(struct cyg_devtab_entry *tab);
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103 static bool quicc_smc_serial_putc(serial_channel *chan, unsigned char c);
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104 static Cyg_ErrNo quicc_smc_serial_lookup(struct cyg_devtab_entry **tab,
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105 struct cyg_devtab_entry *sub_tab,
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106 const char *name);
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107 static unsigned char quicc_smc_serial_getc(serial_channel *chan);
115
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108 static Cyg_ErrNo quicc_smc_serial_set_config(serial_channel *chan,
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109 cyg_uint32 key, const void *xbuf,
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110 cyg_uint32 *len);
82
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111 static void quicc_smc_serial_start_xmit(serial_channel *chan);
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112 static void quicc_smc_serial_stop_xmit(serial_channel *chan);
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113
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114 static cyg_uint32 quicc_smc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data);
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115 static void quicc_smc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
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116
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117 static SERIAL_FUNS(quicc_smc_serial_funs,
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118 quicc_smc_serial_putc,
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119 quicc_smc_serial_getc,
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120 quicc_smc_serial_set_config,
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121 quicc_smc_serial_start_xmit,
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122 quicc_smc_serial_stop_xmit
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123 );
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124
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125 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1
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126 static quicc_smc_serial_info quicc_smc_serial_info1 = {
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127 0x90, // Channel indicator
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128 CYGNUM_HAL_INTERRUPT_CPM_SMC1 // interrupt
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129 };
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130 #if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE > 0
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131 static unsigned char quicc_smc_serial_out_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE];
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132 static unsigned char quicc_smc_serial_in_buf1[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BUFSIZE];
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133
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134 static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_smc_serial_channel1,
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135 quicc_smc_serial_funs,
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136 quicc_smc_serial_info1,
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137 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD),
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138 CYG_SERIAL_STOP_DEFAULT,
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139 CYG_SERIAL_PARITY_DEFAULT,
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140 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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141 CYG_SERIAL_FLAGS_DEFAULT,
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142 &quicc_smc_serial_out_buf1[0], sizeof(quicc_smc_serial_out_buf1),
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143 &quicc_smc_serial_in_buf1[0], sizeof(quicc_smc_serial_in_buf1)
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144 );
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145 #else
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146 static SERIAL_CHANNEL(quicc_smc_serial_channel1,
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147 quicc_smc_serial_funs,
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148 quicc_smc_serial_info1,
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149 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BAUD),
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150 CYG_SERIAL_STOP_DEFAULT,
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151 CYG_SERIAL_PARITY_DEFAULT,
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152 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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153 CYG_SERIAL_FLAGS_DEFAULT
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154 );
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155 #endif
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156
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157 static unsigned char quicc_smc1_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE];
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158 static unsigned char quicc_smc1_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE];
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159
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160 DEVTAB_ENTRY(quicc_smc_serial_io1,
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161 CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_NAME,
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162 0, // Does not depend on a lower level interface
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163 &cyg_io_serial_devio,
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164 quicc_smc_serial_init,
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165 quicc_smc_serial_lookup, // Serial driver may need initializing
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166 &quicc_smc_serial_channel1
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167 );
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168 #endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1
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169
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170 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
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171 static quicc_smc_serial_info quicc_smc_serial_info2 = {
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172 0xD0, // Channel indicator
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173 CYGNUM_HAL_INTERRUPT_CPM_SMC2_PIP // interrupt
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174 };
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175 #if CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE > 0
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176 static unsigned char quicc_smc_serial_out_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE];
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177 static unsigned char quicc_smc_serial_in_buf2[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BUFSIZE];
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178
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179 static SERIAL_CHANNEL_USING_INTERRUPTS(quicc_smc_serial_channel2,
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180 quicc_smc_serial_funs,
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181 quicc_smc_serial_info2,
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182 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD),
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183 CYG_SERIAL_STOP_DEFAULT,
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184 CYG_SERIAL_PARITY_DEFAULT,
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185 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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186 CYG_SERIAL_FLAGS_DEFAULT,
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187 &quicc_smc_serial_out_buf2[0], sizeof(quicc_smc_serial_out_buf2),
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188 &quicc_smc_serial_in_buf2[0], sizeof(quicc_smc_serial_in_buf2)
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189 );
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190 #else
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191 static SERIAL_CHANNEL(quicc_smc_serial_channel2,
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192 quicc_smc_serial_funs,
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193 quicc_smc_serial_info2,
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194 CYG_SERIAL_BAUD_RATE(CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BAUD),
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195 CYG_SERIAL_STOP_DEFAULT,
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196 CYG_SERIAL_PARITY_DEFAULT,
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197 CYG_SERIAL_WORD_LENGTH_DEFAULT,
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198 CYG_SERIAL_FLAGS_DEFAULT
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199 );
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200 #endif
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201 static unsigned char quicc_smc2_txbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE];
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202 static unsigned char quicc_smc2_rxbuf[CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM][CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE];
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203
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204 DEVTAB_ENTRY(quicc_smc_serial_io2,
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205 CYGDAT_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_NAME,
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206 0, // Does not depend on a lower level interface
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207 &cyg_io_serial_devio,
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208 quicc_smc_serial_init,
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209 quicc_smc_serial_lookup, // Serial driver may need initializing
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210 &quicc_smc_serial_channel2
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211 );
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212 #endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
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213
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214 #ifdef CYGDBG_DIAG_BUF
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215 extern int enable_diag_uart;
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216 #endif // CYGDBG_DIAG_BUF
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217
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218 // Internal function to actually configure the hardware to desired baud rate, etc.
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219 static bool
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220 quicc_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
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221 {
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222 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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223 unsigned int baud_divisor = select_baud[new_config->baud];
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224 cyg_uint32 _lcr;
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225 EPPC *eppc = eppc_base();
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226 if (baud_divisor == 0) return false;
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227 // Disable channel during setup
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228 smc_chan->ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
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229 // Disable port interrupts while changing hardware
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230 _lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
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231 select_stop_bits[new_config->stop] |
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232 select_parity[new_config->parity];
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233 // Stop transmitter while changing baud rate
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234 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
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235 // Set baud rate generator
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236 *smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
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237 #ifdef XX_CYGDBG_DIAG_BUF
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238 enable_diag_uart = 0;
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239 diag_printf("Set BAUD RATE[%x], %d = %x, tstate = %x\n", smc_chan->brg, baud_divisor, *smc_chan->brg, smc_chan->pram->tstate);
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240 enable_diag_uart = 1;
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241 #endif // CYGDBG_DIAG_BUF
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242
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243 // Enable channel with new configuration
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244 smc_chan->ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
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245 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
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246 if (new_config != &chan->config) {
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247 chan->config = *new_config;
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248 }
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249 return true;
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250 }
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251
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252 // Function to set up internal tables for device.
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253 static void
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254 quicc_smc_serial_init_info(quicc_smc_serial_info *smc_chan,
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255 volatile struct smc_uart_pram *uart_pram,
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256 volatile struct smc_regs *ctl,
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257 int TxBD, int TxNUM, int TxSIZE,
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258 cyg_uint8 *TxBUF,
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259 int RxBD, int RxNUM, int RxSIZE,
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260 cyg_uint8 *RxBUF,
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261 int portBmask,
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262 int BRG, int SIpos)
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263 {
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264 EPPC *eppc = eppc_base();
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265 struct cp_bufdesc *txbd, *rxbd;
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266 cyg_uint32 simode = 0;
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267 int i;
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268
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269 // Disable channel during setup
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270 ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
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271 smc_chan->pram = uart_pram;
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272 smc_chan->ctl = ctl;
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273 /*
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274 * SDMA & LCD bus request level 5
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275 * (Section 16.10.2.1)
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276 */
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277 eppc->dma_sdcr = 1;
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278 switch (BRG) {
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279 case 1:
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280 smc_chan->brg = (cyg_uint32 *)&eppc->brgc1;
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281 simode = 0;
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282 break;
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283 case 2:
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284 smc_chan->brg = (cyg_uint32 *)&eppc->brgc2;
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285 simode = 1;
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286 break;
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287 case 3:
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288 smc_chan->brg = (cyg_uint32 *)&eppc->brgc3;
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289 simode = 2;
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290 break;
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291 case 4:
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292 smc_chan->brg = (cyg_uint32 *)&eppc->brgc4;
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293 simode = 3;
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294 break;
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295 }
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296 // NMSI mode, BRGn to SMCm (Section 16.12.5.2)
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297 eppc->si_simode = (eppc->si_simode & ~(0xF<<SIpos)) | (simode<<SIpos);
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298 /*
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299 * Set up the PortB pins for UART operation.
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300 * Set PAR and DIR to allow SMCTXDx and SMRXDx
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301 * (Table 16-39)
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302 */
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303 eppc->pip_pbpar |= portBmask;
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304 eppc->pip_pbdir &= ~portBmask;
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305 /*
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306 * Reset Rx & Tx params
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307 */
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308 eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_InitTxRx;
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309 /*
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310 * SDMA & LCD bus request level 5
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311 * (Section 16.10.2.1)
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312 */
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313 eppc->dma_sdcr = 1;
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314 /*
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315 * Set Rx and Tx function code
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316 * (Section 16.15.4.2)
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317 */
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318 uart_pram->rfcr = 0x18;
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319 uart_pram->tfcr = 0x18;
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320 /*
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321 * Set pointers to buffer descriptors.
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322 * (Sections 16.15.4.1, 16.15.7.12, and 16.15.7.13)
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323 */
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324 uart_pram->rbase = RxBD;
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325 uart_pram->tbase = TxBD;
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326 /* tx and rx buffer descriptors */
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327 txbd = (struct cp_bufdesc *)((char *)eppc + TxBD);
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328 rxbd = (struct cp_bufdesc *)((char *)eppc + RxBD);
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329 smc_chan->txbd = txbd;
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330 smc_chan->tbase = txbd;
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331 smc_chan->txsize = TxSIZE;
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332 smc_chan->rxbd = rxbd;
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333 smc_chan->rbase = rxbd;
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334 smc_chan->rxsize = RxSIZE;
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335 /* max receive buffer length */
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336 uart_pram->mrblr = RxSIZE;
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337 /* set max_idle feature - generate interrupt after 4 chars idle period */
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338 uart_pram->max_idl = 4;
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339 /* no last brk char received */
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340 uart_pram->brkln = 0;
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341 /* no break condition occurred */
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342 uart_pram->brkec = 0;
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343 /* 1 break char sent on top XMIT */
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344 uart_pram->brkcr = 1;
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345 /* setup RX buffer descriptors */
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346 for (i = 0; i < RxNUM; i++) {
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347 rxbd->length = 0;
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348 rxbd->buffer = RxBUF;
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349 rxbd->ctrl = QUICC_BD_CTL_Ready | QUICC_BD_CTL_Int;
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350 if (i == (RxNUM-1)) rxbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
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351 RxBUF += RxSIZE;
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352 rxbd++;
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353 }
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354 /* setup TX buffer descriptors */
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355 for (i = 0; i < TxNUM; i++) {
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356 txbd->length = 0;
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357 txbd->buffer = TxBUF;
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358 txbd->ctrl = 0;
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359 if (i == (TxNUM-1)) txbd->ctrl |= QUICC_BD_CTL_Wrap; // Last buffer
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360 TxBUF += TxSIZE;
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361 txbd++;
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362 }
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363 /*
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364 * Clear any previous events. Enable interrupts.
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365 * (Section 16.15.7.14 and 16.15.7.15)
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366 */
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367 ctl->smc_smce = 0xFF;
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368 ctl->smc_smcm = QUICC_SMCE_BSY|QUICC_SMCE_TX|QUICC_SMCE_RX;
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369 }
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370
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371 // Function to initialize the device. Called at bootstrap time.
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372 static bool
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373 quicc_smc_serial_init(struct cyg_devtab_entry *tab)
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374 {
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375 serial_channel *chan = (serial_channel *)tab->priv;
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376 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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377 volatile EPPC *eppc = (volatile EPPC *)eppc_base();
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378 int TxBD, RxBD;
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379 static int first_init = 1;
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380 int cache_state;
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381 HAL_DCACHE_IS_ENABLED(cache_state);
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382 HAL_DCACHE_SYNC();
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383 HAL_DCACHE_DISABLE();
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384 #ifdef CYGDBG_IO_INIT
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385 diag_printf("QUICC_SMC SERIAL init - dev: %x.%d\n", smc_chan->channel, smc_chan->int_num);
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386 #endif
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387 if (first_init) {
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388 // Set up tables since many fields are dynamic [computed at runtime]
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389 first_init = 0;
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390 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC1
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391 eppc->cp_cr = QUICC_SMC_CMD_Reset | QUICC_SMC_CMD_Go; // Totally reset CP
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392 while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ;
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393 TxBD = 0x2800; // Note: this should be configurable
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394 RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM*8;
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395 quicc_smc_serial_init_info(&quicc_smc_serial_info1,
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396 &eppc->pram[2].scc.pothers.smc_modem.psmc.u, // PRAM
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397 &eppc->smc_regs[0], // Control registers
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398 TxBD,
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399 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM,
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400 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxSIZE,
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401 &quicc_smc1_txbuf[0][0],
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402 RxBD,
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403 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM,
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404 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxSIZE,
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405 &quicc_smc1_rxbuf[0][0],
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406 0xC0, // PortB mask
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diff changeset
407 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_BRG,
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408 12 // SI mask position
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409 );
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410 TxBD = RxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_RxNUM*8;
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411 #else
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412 #ifdef CYGPKG_HAL_POWERPC_MBX
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413 // Ensure the SMC1 side is initialized first and use shared mem
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414 // above where it plays:
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415 diag_init(); // (pull in constructor that inits diag channel)
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416 TxBD = 0x2830; // Note: this should be inferred from the chip state
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417 #else
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418 // there is no diag device wanting to use the QUICC, so prepare it
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419 // for SMC2 use only.
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420 eppc->cp_cr = QUICC_SMC_CMD_Reset | QUICC_SMC_CMD_Go; // Totally reset CP
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421 while (eppc->cp_cr & QUICC_SMC_CMD_Reset) ;
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422 TxBD = 0x2800; // Note: this should be configurable
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423 #endif
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424 #endif
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diff changeset
425 #ifdef CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC_SMC2
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426 RxBD = TxBD + CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM*8;
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427 quicc_smc_serial_init_info(&quicc_smc_serial_info2,
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428 &eppc->pram[3].scc.pothers.smc_modem.psmc.u, // PRAM
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429 &eppc->smc_regs[1], // Control registers
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430 TxBD,
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431 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxNUM,
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432 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_TxSIZE,
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433 &quicc_smc2_txbuf[0][0],
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434 RxBD,
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diff changeset
435 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxNUM,
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436 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_RxSIZE,
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jlarmour
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437 &quicc_smc2_rxbuf[0][0],
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438 0xC00, // PortB mask
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diff changeset
439 CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC2_BRG,
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440 28 // SI mask position
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441 );
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442 #endif
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443 }
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444 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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445 if (chan->out_cbuf.len != 0) {
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446 cyg_drv_interrupt_create(smc_chan->int_num,
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447 CYGARC_SIU_PRIORITY_HIGH, // Priority - unused (but asserted)
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448 (cyg_addrword_t)chan, // Data item passed to interrupt handler
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449 quicc_smc_serial_ISR,
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diff changeset
450 quicc_smc_serial_DSR,
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diff changeset
451 &smc_chan->serial_interrupt_handle,
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452 &smc_chan->serial_interrupt);
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diff changeset
453 cyg_drv_interrupt_attach(smc_chan->serial_interrupt_handle);
143
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diff changeset
454 cyg_drv_interrupt_unmask(smc_chan->int_num);
82
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455 }
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456 quicc_smc_serial_config_port(chan, &chan->config, true);
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457 if (cache_state)
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458 HAL_DCACHE_ENABLE();
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459 return true;
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460 }
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461
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462 // This routine is called when the device is "looked" up (i.e. attached)
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463 static Cyg_ErrNo
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464 quicc_smc_serial_lookup(struct cyg_devtab_entry **tab,
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465 struct cyg_devtab_entry *sub_tab,
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466 const char *name)
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467 {
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468 serial_channel *chan = (serial_channel *)(*tab)->priv;
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469 (chan->callbacks->serial_init)(chan); // Really only required for interrupt driven devices
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470 return ENOERR;
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471 }
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diff changeset
472
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jlarmour
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diff changeset
473 // Force the current transmit buffer to be sent
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474 static void
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475 quicc_smc_serial_flush(quicc_smc_serial_info *smc_chan)
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476 {
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477 volatile struct cp_bufdesc *txbd = smc_chan->txbd;
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478 if ((txbd->length > 0) && ((txbd->ctrl & QUICC_BD_CTL_Ready) == 0)) {
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479 txbd->ctrl |= QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int; // Signal buffer ready
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diff changeset
480 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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481 txbd = smc_chan->tbase;
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diff changeset
482 } else {
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483 txbd++;
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484 }
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485 smc_chan->txbd = txbd;
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486 }
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487 }
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diff changeset
488
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jlarmour
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diff changeset
489 // Send a character to the device output buffer.
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490 // Return 'true' if character is sent to device
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491 static bool
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492 quicc_smc_serial_putc(serial_channel *chan, unsigned char c)
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493 {
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494 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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495 volatile struct cp_bufdesc *txbd, *txfirst;
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496 EPPC *eppc = eppc_base();
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diff changeset
497 bool res;
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diff changeset
498 cyg_drv_dsr_lock(); // Avoid race condition testing pointers
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diff changeset
499 txbd = (struct cp_bufdesc *)((char *)eppc + smc_chan->pram->tbptr);
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500 txfirst = txbd;
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jlarmour
parents:
diff changeset
501 // Scan for a non-busy buffer
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diff changeset
502 while (txbd->ctrl & QUICC_BD_CTL_Ready) {
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jlarmour
parents:
diff changeset
503 // This buffer is busy, move to next one
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diff changeset
504 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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505 txbd = smc_chan->tbase;
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506 } else {
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507 txbd++;
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508 }
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509 if (txbd == txfirst) break; // Went all the way around
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diff changeset
510 }
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511 smc_chan->txbd = txbd;
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512 if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == 0) {
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diff changeset
513 // Transmit buffer is not full/busy
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514 txbd->buffer[txbd->length++] = c;
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515 if (txbd->length == smc_chan->txsize) {
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diff changeset
516 // This buffer is now full, tell SMC to start processing it
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517 quicc_smc_serial_flush(smc_chan);
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518 }
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519 res = true;
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520 } else {
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jlarmour
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521 // No space
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522 res = false;
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523 }
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524 cyg_drv_dsr_unlock();
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525 return res;
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526 }
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diff changeset
527
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528 // Fetch a character from the device input buffer, waiting if necessary
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diff changeset
529 static unsigned char
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530 quicc_smc_serial_getc(serial_channel *chan)
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531 {
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532 unsigned char c;
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533 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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534 volatile struct cp_bufdesc *rxbd = smc_chan->rxbd;
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535 while ((rxbd->ctrl & QUICC_BD_CTL_Ready) != 0) ;
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536 c = rxbd->buffer[0];
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537 rxbd->length = smc_chan->rxsize;
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538 rxbd->ctrl |= QUICC_BD_CTL_Ready;
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diff changeset
539 if (rxbd->ctrl & QUICC_BD_CTL_Wrap) {
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540 rxbd = smc_chan->rbase;
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diff changeset
541 } else {
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diff changeset
542 rxbd++;
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parents:
diff changeset
543 }
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parents:
diff changeset
544 smc_chan->rxbd = (struct cp_bufdesc *)rxbd;
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parents:
diff changeset
545 return c;
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jlarmour
parents:
diff changeset
546 }
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jlarmour
parents:
diff changeset
547
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jlarmour
parents:
diff changeset
548 // Set up the device characteristics; baud rate, etc.
115
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parents: 82
diff changeset
549 static Cyg_ErrNo
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parents: 82
diff changeset
550 quicc_smc_serial_set_config(serial_channel *chan, cyg_uint32 key,
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parents: 82
diff changeset
551 const void *xbuf, cyg_uint32 *len)
82
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parents:
diff changeset
552 {
115
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parents: 82
diff changeset
553 switch (key) {
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parents: 82
diff changeset
554 case CYG_IO_SET_CONFIG_SERIAL_INFO:
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parents: 82
diff changeset
555 {
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parents: 82
diff changeset
556 // FIXME - The documentation says that you can't change the baud rate
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parents: 82
diff changeset
557 // again until at least two BRG input clocks have occurred.
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diff changeset
558 cyg_serial_info_t *config = (cyg_serial_info_t *)xbuf;
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parents: 82
diff changeset
559 if ( *len < sizeof(cyg_serial_info_t) ) {
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diff changeset
560 return -EINVAL;
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parents: 82
diff changeset
561 }
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diff changeset
562 *len = sizeof(cyg_serial_info_t);
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diff changeset
563 if ( true != quicc_smc_serial_config_port(chan, config, false) )
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parents: 82
diff changeset
564 return -EINVAL;
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parents: 82
diff changeset
565 }
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diff changeset
566 break;
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diff changeset
567 default:
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diff changeset
568 return -EINVAL;
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parents: 82
diff changeset
569 }
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570 return ENOERR;
82
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parents:
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571 }
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parents:
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572
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parents:
diff changeset
573 // Enable the transmitter (interrupt) on the device
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diff changeset
574 static void
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diff changeset
575 quicc_smc_serial_start_xmit(serial_channel *chan)
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576 {
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577 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
143
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diff changeset
578 cyg_drv_dsr_lock();
82
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diff changeset
579 if (smc_chan->txbd->length == 0) {
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jlarmour
parents:
diff changeset
580 // See if there is anything to put in this buffer, just to get it going
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diff changeset
581 (chan->callbacks->xmt_char)(chan);
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582 }
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jlarmour
parents:
diff changeset
583 if (smc_chan->txbd->length != 0) {
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jlarmour
parents:
diff changeset
584 // Make sure it gets started
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parents:
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585 quicc_smc_serial_flush(smc_chan);
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parents:
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586 }
143
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diff changeset
587 cyg_drv_dsr_unlock();
82
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parents:
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588 }
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589
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jlarmour
parents:
diff changeset
590 // Disable the transmitter on the device
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parents:
diff changeset
591 static void
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diff changeset
592 quicc_smc_serial_stop_xmit(serial_channel *chan)
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593 {
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594 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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diff changeset
595 // If anything is in the last buffer, need to get it started
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diff changeset
596 if (smc_chan->txbd->length != 0) {
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parents:
diff changeset
597 quicc_smc_serial_flush(smc_chan);
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diff changeset
598 }
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599 }
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diff changeset
600
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jlarmour
parents:
diff changeset
601 // Serial I/O - low level interrupt handler (ISR)
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diff changeset
602 static cyg_uint32
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diff changeset
603 quicc_smc_serial_ISR(cyg_vector_t vector, cyg_addrword_t data)
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diff changeset
604 {
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diff changeset
605 serial_channel *chan = (serial_channel *)data;
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diff changeset
606 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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607 cyg_drv_interrupt_mask(smc_chan->int_num);
132
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diff changeset
608 return (CYG_ISR_HANDLED|CYG_ISR_CALL_DSR); // Cause DSR to be run
82
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parents:
diff changeset
609 }
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jlarmour
parents:
diff changeset
610
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jlarmour
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diff changeset
611 // Serial I/O - high level interrupt handler (DSR)
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diff changeset
612 static void
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diff changeset
613 quicc_smc_serial_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
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parents:
diff changeset
614 {
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diff changeset
615 serial_channel *chan = (serial_channel *)data;
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diff changeset
616 quicc_smc_serial_info *smc_chan = (quicc_smc_serial_info *)chan->dev_priv;
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617 volatile struct smc_regs *ctl = smc_chan->ctl;
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618 volatile struct cp_bufdesc *txbd;
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diff changeset
619 volatile struct cp_bufdesc *rxbd = smc_chan->rxbd;
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620 struct cp_bufdesc *rxlast;
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diff changeset
621 int i, cache_state;
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diff changeset
622 #ifdef CYGDBG_DIAG_BUF
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diff changeset
623 int _time, _stime;
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diff changeset
624 externC cyg_tick_count_t cyg_current_time(void);
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diff changeset
625 cyg_drv_isr_lock();
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diff changeset
626 enable_diag_uart = 0;
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diff changeset
627 HAL_CLOCK_READ(&_time);
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628 _stime = (int)cyg_current_time();
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diff changeset
629 diag_printf("DSR start - CE: %x, time: %x.%x\n", ctl->smc_smce, _stime, _time);
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diff changeset
630 enable_diag_uart = 1;
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jlarmour
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diff changeset
631 #endif // CYGDBG_DIAG_BUF
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diff changeset
632 if (ctl->smc_smce & QUICC_SMCE_TX) {
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jlarmour
parents:
diff changeset
633 #ifdef XX_CYGDBG_DIAG_BUF
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diff changeset
634 enable_diag_uart = 0;
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diff changeset
635 txbd = smc_chan->tbase;
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diff changeset
636 for (i = 0; i < CYGNUM_IO_SERIAL_POWERPC_QUICC_SMC_SMC1_TxNUM; i++, txbd++) {
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parents:
diff changeset
637 diag_printf("Tx BD: %x, length: %d, ctl: %x\n", txbd, txbd->length, txbd->ctrl);
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diff changeset
638 }
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diff changeset
639 enable_diag_uart = 1;
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jlarmour
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diff changeset
640 #endif // CYGDBG_DIAG_BUF
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jlarmour
parents:
diff changeset
641 // Transmit interrupt
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jlarmour
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diff changeset
642 ctl->smc_smce = QUICC_SMCE_TX; // Reset interrupt state;
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diff changeset
643 txbd = smc_chan->tbase; // First buffer
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diff changeset
644 while (true) {
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diff changeset
645 if ((txbd->ctrl & (QUICC_BD_CTL_Ready|QUICC_BD_CTL_Int)) == QUICC_BD_CTL_Int) {
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jlarmour
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diff changeset
646 #ifdef XX_CYGDBG_DIAG_BUF
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diff changeset
647 enable_diag_uart = 0;
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diff changeset
648 HAL_CLOCK_READ(&_time);
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649 _stime = (int)cyg_current_time();
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diff changeset
650 diag_printf("TX Done - Tx: %x, length: %d, time: %x.%x\n", txbd, txbd->length, _stime, _time);
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diff changeset
651 enable_diag_uart = 1;
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diff changeset
652 #endif // CYGDBG_DIAG_BUF
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653 txbd->length = 0;
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diff changeset
654 txbd->ctrl &= ~QUICC_BD_CTL_Int; // Reset interrupt bit
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diff changeset
655 }
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656 if (txbd->ctrl & QUICC_BD_CTL_Wrap) {
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diff changeset
657 txbd = smc_chan->tbase;
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diff changeset
658 break;
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diff changeset
659 } else {
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diff changeset
660 txbd++;
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661 }
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diff changeset
662 }
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diff changeset
663 (chan->callbacks->xmt_char)(chan);
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diff changeset
664 }
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jlarmour
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665 while (ctl->smc_smce & QUICC_SMCE_RX) {
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diff changeset
666 // Receive interrupt
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diff changeset
667 ctl->smc_smce = QUICC_SMCE_RX; // Reset interrupt state;
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diff changeset
668 rxlast = (struct cp_bufdesc *) (
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jlarmour
parents:
diff changeset
669 (char *)eppc_base() + smc_chan->pram->rbptr );
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diff changeset
670 #ifdef CYGDBG_DIAG_BUF
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diff changeset
671 enable_diag_uart = 0;
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672 HAL_CLOCK_READ(&_time);
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jlarmour
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673 _stime = (int)cyg_current_time();
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674 diag_printf("Scan RX - rxbd: %x, rbptr: %x, time: %x.%x\n", rxbd, rxlast, _stime, _time);
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jlarmour
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diff changeset
675 #endif // CYGDBG_DIAG_BUF
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jlarmour
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diff changeset
676 while (rxbd != rxlast) {
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jlarmour
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diff changeset
677 if ((rxbd->ctrl & QUICC_BD_CTL_Ready) == 0) {
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678 #ifdef CYGDBG_DIAG_BUF
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jlarmour
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679 diag_printf("rxbuf: %x, flags: %x, length: %d\n", rxbd, rxbd->ctrl, rxbd->length);
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680 diag_dump_buf(rxbd->buffer, rxbd->length);
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681 #endif // CYGDBG_DIAG_BUF
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682 for (i = 0; i < rxbd->length; i++) {
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683 (chan->callbacks->rcv_char)(chan, rxbd->buffer[i]);
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684 }
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685 // Note: the MBX860 does not seem to snoop/invalidate the data cache properly!
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686 HAL_DCACHE_IS_ENABLED(cache_state);
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687 if (cache_state) {
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688 HAL_DCACHE_INVALIDATE(rxbd->buffer, smc_chan->rxsize); // Make sure no stale data
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689 }
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690 rxbd->length = 0;
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691 rxbd->ctrl |= QUICC_BD_CTL_Ready;
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692 }
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693 if (rxbd->ctrl & QUICC_BD_CTL_Wrap) {
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694 rxbd = smc_chan->rbase;
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695 } else {
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696 rxbd++;
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697 }
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698 }
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699 #ifdef CYGDBG_DIAG_BUF
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700 enable_diag_uart = 1;
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701 #endif // CYGDBG_DIAG_BUF
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702 smc_chan->rxbd = (struct cp_bufdesc *)rxbd;
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703 }
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704 if (ctl->smc_smce & QUICC_SMCE_BSY) {
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705 #ifdef CYGDBG_DIAG_BUF
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706 enable_diag_uart = 0;
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707 diag_printf("RX BUSY interrupt\n");
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708 enable_diag_uart = 1;
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709 #endif // CYGDBG_DIAG_BUF
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710 ctl->smc_smce = QUICC_SMCE_BSY; // Reset interrupt state;
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711 }
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712 #ifdef CYGDBG_DIAG_BUF
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713 enable_diag_uart = 0;
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714 HAL_CLOCK_READ(&_time);
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715 _stime = (int)cyg_current_time();
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716 diag_printf("DSR done - CE: %x, time: %x.%x\n", ctl->smc_smce, _stime, _time);
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717 enable_diag_uart = 1;
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718 #endif // CYGDBG_DIAG_BUF
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719 cyg_drv_interrupt_acknowledge(smc_chan->int_num);
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720 cyg_drv_interrupt_unmask(smc_chan->int_num);
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721 #ifdef CYGDBG_DIAG_BUF
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722 cyg_drv_isr_unlock();
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723 #endif // CYGDBG_DIAG_BUF
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724 }
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725
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726 void
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727 show_rxbd(int dump_all)
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728 {
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729 #ifdef CYGDBG_DIAG_BUF
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730 EPPC *eppc = eppc_base();
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731 struct smc_uart_pram *pram = &eppc->pram[2].scc.pothers.smc_modem.psmc.u;
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732 struct cp_bufdesc *rxbd = (struct cp_bufdesc *)((char *)eppc+pram->rbase);
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733 int _enable = enable_diag_uart;
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734 enable_diag_uart = 0;
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735 #if 1
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736 diag_printf("SMC Mask: %x, Events: %x, Rbase: %x, Rbptr: %x\n",
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737 eppc->smc_regs[0].smc_smcm, eppc->smc_regs[0].smc_smce,
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738 pram->rbase, pram->rbptr);
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739 while (true) {
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740 diag_printf("Rx BD: %x, ctl: %x, length: %d\n", rxbd, rxbd->ctrl, rxbd->length);
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741 if (rxbd->ctrl & QUICC_BD_CTL_Wrap) break;
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742 rxbd++;
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743 }
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744 #endif
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745 enable_diag_uart = _enable;
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746 if (dump_all) dump_diag_buf();
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747 #endif // CYGDBG_DIAG_BUF
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748 }
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749 #endif // CYGPKG_IO_SERIAL_POWERPC_QUICC_SMC
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750
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751 // ------------------------------------------------------------------------
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752 // EOF powerpc/quicc_smc_serial.c