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annotate packages/hal/mips/arch/current/include/arch.inc @ 18:7253dcc42a09 ecos-sw-1999-06-25

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Merge from eCos master repository on 1999-06-25-15:31:50-BST
author jlarmour
date Fri, 25 Jun 1999 08:28:05 +0000
parents ece80412419a
children 306eee292492
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1 #ifndef CYGONCE_HAL_ARCH_INC
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2 #define CYGONCE_HAL_ARCH_INC
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3 ##=============================================================================
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4 ##
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5 ## arch.inc
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6 ##
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7 ## MIPS assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Cygnus eCos Public License
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14 # Version 1.0 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://sourceware.cygnus.com/ecos
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Cygnus Operating System, released
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24 # September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Cygnus. Portions created
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27 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 ##=============================================================================
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32 #######DESCRIPTIONBEGIN####
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33 ##
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34 ## Author(s): nickg
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35 ## Contributors: nickg
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36 ## Date: 1997-10-16
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37 ## Purpose: Architecture definitions.
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38 ## Description: This file contains various definitions and macros that are
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39 ## useful for writing assembly code for the MIPS CPU family.
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40 ## Usage:
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41 ## #include <cyg/hal/arch.inc>
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42 ## ...
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43 ##
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44 ##
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45 ######DESCRIPTIONEND####
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46 ##
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47 ##=============================================================================
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48
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49 #include <cyg/hal/mips.inc>
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50
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51 #include <cyg/hal/variant.inc>
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52
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53 ##-----------------------------------------------------------------------------
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54 ## Set up the value for the initial status register
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55
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56 #ifndef INITIAL_SR
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57
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58 #if defined(CYG_HAL_STARTUP_RAM)
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59 # if defined(CYG_HAL_MIPS_SIM) || !defined(CYG_HAL_USE_ROM_MONITOR)
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60 # define INITIAL_SR 0x1000ff00 /* CP0 usable, Ints enabled */
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61 # else
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62 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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63 # endif
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64 #elif defined(CYG_HAL_STARTUP_ROM)
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65 # define INITIAL_SR 0x1040ff00 /* as above + ROM vectors used */
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66 #endif
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67
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68 #endif
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69
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70 ##-----------------------------------------------------------------------------
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71 ## Setup the initial value for the config0 register
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72
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73 #ifndef INITIAL_CONFIG0
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74
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75 #define INITIAL_CONFIG0 0x00000002
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76
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77 #endif
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78
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79 ##-----------------------------------------------------------------------------
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80 ## MIPS thread and interrupt saved state. This must match the layout of the
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81 ## HAL_SavedRegisters in hal_arch.h. Do not change this without changing the
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82 ## layout there, or viceversa.
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83
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84 #ifdef CYGHWR_HAL_MIPS_64BIT
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85 # define mips_regsize 8
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86 #else
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87 # define mips_regsize 4
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88 #endif
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89
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90 #if defined(CYGHWR_HAL_MIPS_FPU)
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91 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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92 # define mips_fpuregsize 8
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93 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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94 # define mips_fpuregsize 4
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95 # else
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96 # error MIPS FPU register size not defined
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97 # endif
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98 #endif
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99
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100
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101 #define mipsreg_regs 0
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102 #define mipsreg_hi (mips_regsize*32)
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103 #define mipsreg_lo (mipsreg_hi+mips_regsize)
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104 #ifdef CYGHWR_HAL_MIPS_FPU
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105 # define mipsreg_fpureg (mipsreg_lo+mips_regsize)
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106 # define mipsreg_fcr31 (mipsreg_fpureg+(mips_fpuregsize*32))
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107 # define mipsreg_fppad (mipsreg_fcr31+mips_regsize)
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108 # define mipsreg_vector (mipsreg_fppad+mips_regsize)
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109 #else
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110 # define mipsreg_vector (mipsreg_lo+mips_regsize)
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111 #endif
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112 #define mipsreg_pc (mipsreg_vector+mips_regsize)
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113 #define mipsreg_sr (mipsreg_pc+mips_regsize)
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114 #define mipsreg_cache (mipsreg_sr+mips_regsize)
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115 #define mipsreg_cause (mipsreg_cache+mips_regsize)
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116 #define mipsreg_badvr (mipsreg_cause+mips_regsize)
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117 #define mipsreg_prid (mipsreg_badvr+mips_regsize)
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118 #define mipsreg_config (mipsreg_prid+mips_regsize)
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119 #define mipsreg_size (mipsreg_config+mips_regsize)
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120
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121 #define mips_exception_decrement (mipsreg_size*2)
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122
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123 ##-----------------------------------------------------------------------------
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124 ## Minimal stack frame size uses to call functions from asm.
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125
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126 #define mips_stack_frame_size 32 // 4 (64 bit) args worth
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127
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128 ##-----------------------------------------------------------------------------
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129 ## Load Address and Relocate. This macro is used in code that may be linked
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130 ## to execute out of RAM but is actually executed from ROM. If that is the
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131 ## case a suitable version of this macro will have been defined elsewhere.
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132 ## This is just a default version for use when that does not happen.
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133
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134 #ifndef CYGPKG_HAL_MIPS_LAR_DEFINED
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135
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136 .macro lar reg,addr
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137 la \reg,\addr
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138 .endm
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139
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140 #define CYGPKG_HAL_MIPS_LAR_DEFINED
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141
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142 #endif
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143
6
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144 ##-----------------------------------------------------------------------------
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145 ## CPU specific macros. These provide a common assembler interface to
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146 ## operations that may have CPU specific implementations on different
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147 ## variants of the architecture.
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148
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149 # Initialize CPU
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150 .macro hal_cpu_init
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151 mtc0 zero,cause # zero cause reg
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152 nop
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153 la v0,INITIAL_SR # initialize status register
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154 mtc0 v0,status
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155 nop
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156 nop
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157 nop
8
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158 la v0,INITIAL_CONFIG0
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159 mtc0 v0,config0
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160 nop
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161 nop
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162 nop
6
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163 .endm
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164
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165 # Enable interrupts
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166 #ifdef CYG_HAL_MIPS_R3900
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167 .macro hal_cpu_int_enable
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168 mfc0 v0,status
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169 nop
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170 nop
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171 ori v0,v0,0x0001 # set IE bit
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172 mtc0 v0,status
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173 nop
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174 nop
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175 nop
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176 .endm
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177 #else
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178 .macro hal_cpu_int_enable
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179 mfc0 v0,status
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180 la v1,0xFFFFFFF9
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181 and v0,v0,v1 # clear EXL and ERL bits
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182 ori v0,v0,0x0001 # set IE bit
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183 mtc0 v0,status
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184 nop
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185 nop
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186 nop
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187 .endm
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188 #endif
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189
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190
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191 # Disable interrupts
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192 .macro hal_cpu_int_disable
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193 mfc0 v0,status
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194 la v1,0xFFFFFFFE
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195 and v0,v0,v1
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196 mtc0 v0,status
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197 nop
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198 nop
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199 nop
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200 .endm
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201
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202 # Merge the interrupt enable state of the status register in
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203 # \sr with the current sr.
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204 #ifdef CYG_HAL_MIPS_R3900
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205 #define HAL_SR_INT_MASK 0x00000001 // IEc only
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206 #else
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207 #define HAL_SR_INT_MASK 0x00000007 // IE, EXL, ERL
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208 #endif
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209 .macro hal_cpu_int_merge sr
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210 mfc0 v0,status # V0 = current SR
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211 la v1,HAL_SR_INT_MASK # V1 = SR interrupt bits mask
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212 and \sr,\sr,v1 # Isolate interrupt bits of \sr
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213 nor v1,v1,zero # Invert mask
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214 and v0,v0,v1 # V0 = current SR except int bits
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215 or v0,v0,\sr # V0 = New SR
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216 mtc0 v0,status # Return to SR
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217 .endm
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218
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219 # Enable further exception processing, and disable
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220 # interrupt processing.
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221 #ifdef CYG_HAL_MIPS_R3900
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222 .macro hal_cpu_except_enable
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223 hal_cpu_int_disable
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224 .endm
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225 #else
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226 .macro hal_cpu_except_enable
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227 mfc0 v0,status
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228 la v1,0xFFFFFFF0
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229 and v0,v0,v1 # clear EXL, ERL and IE bits
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230 mtc0 v0,status
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231 nop
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232 nop
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233 nop
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234 .endm
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235 #endif
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236
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237 # Return from exception.
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238 #ifdef CYG_HAL_MIPS_R3900
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239 .macro hal_cpu_eret pc,sr
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240 mtc0 \sr,status # Load status register
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241 nop
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242 nop
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243 nop
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244 sync # settle things down
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245 jr \pc # jump back to interrupted code
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246 rfe # restore state (delay slot)
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247 .endm
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248 #else
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249 .macro hal_cpu_eret pc,sr
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250 mtc0 \pc,epc # put PC in EPC
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251 nop
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252 nop
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253 nop
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254 mtc0 \sr,status # put SR back
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255 nop
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256 nop
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257 nop
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258 sync # settle things down
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259 eret # return
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260 nop # just to be safe
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261 .endm
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262 #endif
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263
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264 ##-----------------------------------------------------------------------------
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265 # Default MIPS interrupt decoding macros. This uses the basic interrupt
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266 # support provided by CP0 in the cause and status registers. If there is
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267 # a more complex external interrupt controller, or the default stuff is
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268 # interpreted differently (as in the TX3904) then these macros will be
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269 # overridden and CYGPKG_HAL_MIPS_INTC_DEFINED will be defined.
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270
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271 #ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
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272
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273 #ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
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274 # initialize all interrupts to disabled
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275 .macro hal_intc_init
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276 mfc0 v0,status
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277 nop
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278 lui v1,0xFFFF
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279 ori v1,v1,0x00FF
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280 and v0,v0,v1 # clear the IntMask bits
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281 mtc0 v0,status
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282 nop
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283 nop
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284 nop
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285 .endm
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286 #endif
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287
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288 .macro hal_intc_decode vnum
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289 mfc0 v0,cause # get cause register
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290 nop # delay slot
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291 srl v0,v0,10 # shift interrupt bits down
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292 andi v0,v0,0x7f # isolate 6 interrupt bits
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293 la v1,hal_intc_translation_table
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294 add v0,v0,v1 # index into table
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295 lb \vnum,0(v0) # pick up vector number
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296 .endm
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297
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298 .macro hal_intc_decode_data
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299 hal_intc_translation_table:
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300 .byte 0, 0, 1, 0
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301 .byte 2, 0, 1, 0
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302 .byte 3, 0, 1, 0
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303 .byte 2, 0, 1, 0
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304 .byte 4, 0, 1, 0
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305 .byte 2, 0, 1, 0
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306 .byte 3, 0, 1, 0
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307 .byte 2, 0, 1, 0
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308 .byte 5, 0, 1, 0
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309 .byte 2, 0, 1, 0
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310 .byte 3, 0, 1, 0
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311 .byte 2, 0, 1, 0
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312 .byte 4, 0, 1, 0
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313 .byte 2, 0, 1, 0
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314 .byte 3, 0, 1, 0
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315 .byte 2, 0, 1, 0
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316 .endm
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317 #endif
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318
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319 #------------------------------------------------------------------------------
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320 # FPU macros.
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321 # The MIPS floating point unit essentially operates in two modes. In the first
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322 # it supplies 32 32bit FP registers that may be paired into 16 64 bit registers.
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323 # In the second it supplies 32 64bit registers. Which mode is to be used depends
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324 # not only on the specific implementation in use, but also on the setting of the
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325 # FR bit in the status register (if it is implemented) and on the expectations of
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326 # the toolchain.
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327
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328 #ifndef CYGPKG_HAL_MIPS_FPU_DEFINED
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329
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330 #ifdef CYGHWR_HAL_MIPS_FPU
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331
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332 #if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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333 #define sfpr sdc1
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334 #define lfpr ldc1
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335 #define CYG_HAL_MIPS_FPU_SR_INIT 0x24000000
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336 #elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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337 #define sfpr swc1
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338 #define lfpr lwc1
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339 #define CYG_HAL_MIPS_FPU_SR_INIT 0x20000000
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340 #else
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341 #error MIPS FPU register size not defined
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342 #endif
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343
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344 #ifndef CYG_HAL_MIPS_FSR_INIT
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345 #define CYG_HAL_MIPS_FSR_INIT 0
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346 #endif
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347
6
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348 .macro hal_fpu_init
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349 mfc0 v0,status # Get sr
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350 la v1,0xDBFFFFFF # Clear bits to be changed
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351 and v0,v0,v1
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352 la v1,CYG_HAL_MIPS_FPU_SR_INIT # Set the bits we want
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353 or v0,v0,v1 # Set sr to required value
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354 mtc0 v0,status # return to sr
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355 nop
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356 nop
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357 nop
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358 la v0,CYG_HAL_MIPS_FSR_INIT # Get initial value for FSR
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359 ctc1 v0,$31 # set Fp control reg
6
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360 nop
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361 .endm
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362
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363 # Save the caller-saved registers as defined by the ABI.
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364 # These only really need saving during interrupts.
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365 .macro hal_fpu_save_caller regs
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366 sfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
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367 sfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
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368 sfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
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369 sfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
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370 sfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
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371 sfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
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372 sfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
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373 sfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
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374 sfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
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375 sfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
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376 sfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
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377 sfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
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378 sfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
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379 sfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
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380 sfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
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381 sfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
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382 sfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
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383 sfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
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384 sfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
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385 sfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
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386 sfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
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387 cfc1 v0,$31
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388 sw v0,mipsreg_fcr31(\regs)
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389 .endm
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390
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391 # Save the callee-saved registers as defined by the ABI.
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392 # These are the only registers that need to be saved
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393 # across thread switches.
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394 .macro hal_fpu_save_callee regs
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395 sfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
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396 sfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
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397 sfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
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398 sfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
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399 sfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
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400 sfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
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401 sfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
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402 sfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
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403 sfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
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404 sfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
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405 sfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
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406 .endm
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407
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408 # General macro to save everything
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409 .macro hal_fpu_save regs
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410 hal_fpu_save_callee \regs
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411 hal_fpu_save_caller \regs
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412 .endm
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413
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414 # Reload the caller-saved registers.
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415 .macro hal_fpu_load_caller regs
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416 lw v0,mipsreg_fcr31(\regs)
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417 ctc1 v0,$31
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418 lfpr f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
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419 lfpr f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
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420 lfpr f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
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421 lfpr f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
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422 lfpr f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
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423 lfpr f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
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424 lfpr f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
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425 lfpr f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
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426 lfpr f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
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427 lfpr f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
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428 lfpr f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
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429 lfpr f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
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430 lfpr f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
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431 lfpr f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
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432 lfpr f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
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433 lfpr f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
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434 lfpr f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
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435 lfpr f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
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436 lfpr f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
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437 lfpr f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
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438 lfpr f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
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439 .endm
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440
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441 # Reload the callee-saved registers.
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442 .macro hal_fpu_load_callee regs
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443 lfpr f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
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444 lfpr f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
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445 lfpr f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
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446 lfpr f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
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447 lfpr f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
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448 lfpr f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
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449 lfpr f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
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450 lfpr f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
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451 lfpr f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
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452 lfpr f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
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453 lfpr f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
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454 .endm
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455
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456 # Reload everything.
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457 .macro hal_fpu_load regs
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458 hal_fpu_load_caller \regs
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459 hal_fpu_load_callee \regs
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460 .endm
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461 #else
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462
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463 # Default macros for non-fpu implementations
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464
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465 .macro hal_fpu_init
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466 .endm
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467
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468 .macro hal_fpu_save regs
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469 .endm
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470
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471 .macro hal_fpu_save_caller regs
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472 .endm
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473
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474 .macro hal_fpu_save_callee regs
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475 .endm
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476
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477 .macro hal_fpu_load_caller regs
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478 .endm
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479
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480 .macro hal_fpu_load_callee regs
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481 .endm
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482
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483 .macro hal_fpu_load regs
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484 .endm
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485
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486 #endif
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487
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488 #endif
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489
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490 #------------------------------------------------------------------------------
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491 # MMU macros.
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492
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493 #ifndef CYGPKG_HAL_MIPS_MMU_DEFINED
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494
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495 .macro hal_mmu_init
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496 .endm
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497
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498 #endif
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499
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500 #------------------------------------------------------------------------------
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501 # MEMC macros.
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502
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503 #ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
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504
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505 .macro hal_memc_init
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506 .endm
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507
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508 #endif
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509
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510 #------------------------------------------------------------------------------
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511 # Cache macros.
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512
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513 #ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
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514
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515 #ifdef CYG_HAL_MIPS_R3900
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516 .macro hal_cache_init
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517 mfc0 v0,config # disable cache in config register
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518 nop
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519 nop
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520 la v1,0xffffffcf
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521 and v0,v0,v1
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522 mtc0 v0,config
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523 nop
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524 nop
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525 nop
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526 .endm
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527 #else
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528 .macro hal_cache_init
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529 mfc0 v0,config0 # disable Kseg0 caching in config0 register
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530 nop
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531 nop
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532 la v1,0xfffffff8
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533 and v0,v0,v1
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534 ori v0,v0,2
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535 mtc0 v0,config0
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536 nop
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537 nop
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538 nop
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539 .endm
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540 #endif
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541
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542 #endif
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543
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544 #------------------------------------------------------------------------------
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545 # Diagnostics macros.
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546
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547 #ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
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548
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549 .macro hal_diag_init
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550 .endm
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551
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552 .macro hal_diag_excpt_start
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553 .endm
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554
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555 .macro hal_diag_intr_start
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556 .endm
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557
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558 .macro hal_diag_restore
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559 .endm
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560 #endif
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561
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562 #------------------------------------------------------------------------------
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563 # Timer initialization.
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564
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565 #ifndef CYGPKG_HAL_MIPS_TIMER_DEFINED
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566
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567 .macro hal_timer_init
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568 .endm
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569
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570 #endif
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571
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572 #------------------------------------------------------------------------------
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573 # Monitor initialization.
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574
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575 #ifndef CYGPKG_HAL_MIPS_MON_DEFINED
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576
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577 .macro hal_mon_init
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578 .endm
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579
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580 #endif
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581
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582 #------------------------------------------------------------------------------
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583 #endif // ifndef CYGONCE_HAL_ARCH_INC
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584 # end of arch.inc