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annotate packages/hal/mips/tx39/current/include/variant.inc @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## TX39 family assembler header file
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8 ##
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9 ##=============================================================================
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10 ## ####ECOSGPLCOPYRIGHTBEGIN####
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11 ## -------------------------------------------
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12 ## This file is part of eCos, the Embedded Configurable Operating System.
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13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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14 ##
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15 ## eCos is free software; you can redistribute it and/or modify it under
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16 ## the terms of the GNU General Public License as published by the Free
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17 ## Software Foundation; either version 2 or (at your option) any later
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18 ## version.
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19 ##
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20 ## eCos is distributed in the hope that it will be useful, but WITHOUT
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21 ## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 ## for more details.
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24 ##
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25 ## You should have received a copy of the GNU General Public License
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26 ## along with eCos; if not, write to the Free Software Foundation, Inc.,
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27 ## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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28 ##
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29 ## As a special exception, if other files instantiate templates or use
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30 ## macros or inline functions from this file, or you compile this file
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31 ## and link it with other works to produce a work based on this file,
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32 ## this file does not by itself cause the resulting work to be covered by
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33 ## the GNU General Public License. However the source code for this file
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34 ## must still be made available in accordance with section (3) of the GNU
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35 ## General Public License v2.
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36 ##
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37 ## This exception does not invalidate any other reasons why a work based
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38 ## on this file might be covered by the GNU General Public License.
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39 ## -------------------------------------------
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40 ## ####ECOSGPLCOPYRIGHTEND####
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41 ##=============================================================================
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42 #######DESCRIPTIONBEGIN####
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43 ##
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44 ## Author(s): nickg
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45 ## Contributors: nickg
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46 ## Date: 1999-04-06
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47 ## Purpose: TX39 family definitions.
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48 ## Description: This file contains various definitions and macros that are
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49 ## useful for writing assembly code for the TX39 CPU family.
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50 ## Usage:
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51 ## #include <cyg/hal/variant.inc>
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52 ## ...
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53 ##
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54 ##
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55 ######DESCRIPTIONEND####
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56 ##
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57 ##=============================================================================
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58
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59 #include <pkgconf/hal.h>
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60
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61 #include <cyg/hal/mips.inc>
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62
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63 #include <cyg/hal/platform.inc>
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64
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65 ##-----------------------------------------------------------------------------
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66 ## Define CPU variant for architecture HAL.
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67
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68 #define CYG_HAL_MIPS_R3000A
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69 #define CYG_HAL_MIPS_R3900
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70
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71 ##-----------------------------------------------------------------------------
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72 ## Indicate that the ISR tables are defined in variant.S
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73
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74 #define CYG_HAL_MIPS_ISR_TABLES_DEFINED
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75
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76 ##-----------------------------------------------------------------------------
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77 ## TX39 Memory controller.
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78
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79 #ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
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80
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81 ## ROM timing characteristics are dependent on the clock speed.
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82
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83 #if (CYGHWR_HAL_MIPS_CPU_FREQ == 50)
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84 #define ROM_CCR0_INIT 0x00000420
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85 #define DRAM_DREFC_INIT 0x00000180
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86 #define DRAM_DWR0_INIT 0x00111111
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87 #elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66)
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88 #define ROM_CCR0_INIT 0x00000520
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89 #define DRAM_DREFC_INIT 0x00000200
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90 #define DRAM_DWR0_INIT 0x00332222
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91 #else
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92 #error Unsupported clock frequency
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93 #endif
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94
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95 ## DRAM configuration is dependent on the DRAM device used.
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96 ## for 16MByte (4MBit (x4bit) x 8) 0x08024030
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97 ## for 4MByte (1MBit (x4bit) x 8) 0x08013020
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98 ## for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020
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99
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100 #if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
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101 #define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
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102 #else
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103 #define DRAM_CONFIG_INIT 0x08024030
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104 #endif
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105
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106 ## Enabling timeout exceptions can result in bogus exceptions under the
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107 ## following conditions:
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108 ## o half speed bus mode (JMR board uses this mode)
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109 ## o code resides on 0 wait SRAM
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110 ## o I- and D- caches are enabled
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111 ## o a very narrow timing condition of cache refill cycle (not
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112 ## descibed here)
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113 ## The simple solution is to configure 1 cycle wait state SRAM rather
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114 ## than zero.
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115
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116 #ifdef CYGHWR_HAL_MIPS_TX39_JMR3904_ENABLE_TOE
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117 #define SRAM_WAIT_INIT 0x00000100
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118 #else
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119 #define SRAM_WAIT_INIT 0x00000000
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120 #endif
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121
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122 .macro hal_memc_init
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123
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124 # These mappings need to be set up before we
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125 # can use the stack and make calls to other
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126 # functions
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127
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128 # If we have been started from Cygmon, it should have
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129 # already done a lot of this, but it should do no harm
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130 # to reinitialize the following registers.
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131
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132 # SCS0,1 base addr of ISA & PCI
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133 la v0,0xffffe010
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134 la v1,0x20201410
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135 sw v1,0(v0)
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136
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137 la v0,0xffffe014
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138 la v1,0xfffffcfc
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139 sw v1,0(v0)
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140
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141 # ROM configuration
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142 .set at
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143 la v0,0xffff9000
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144 lw v1,0(v0)
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145 and v1,v1,0xffff0004 # keep hardware defaults
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146 or v1,ROM_CCR0_INIT # install our values
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147 sw v1,0(v0)
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148 .set noat
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149
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150 # SRAM config
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151 la v0,0xffff9100
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152 la v1,SRAM_WAIT_INIT
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153 sw v1,0(v0)
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154
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155 # ISA bus setup
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156 la v0,0xb2100000
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157 la v1,4
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158 sb v1,0(v0)
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159
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160 # Clear IMR (to cope with JMON)
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161 la v0,0xffffc004
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162 la v1,0x00000000
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163 sw v1,0(v0)
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164
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165 hal_memc_init_dram
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166
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167 .endm
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168
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169
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170 .macro hal_memc_init_dram
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171 # DRAM Configuration
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172 la v0, 0xffff8000
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173 la v1, DRAM_CONFIG_INIT
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174 sw v1, 0(v0)
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175
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176 # DBMR0
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177 la v0, 0xffff8004
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178 la v1, 0x00000000
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179 sw v1, 0(v0)
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180
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181 # DWR0
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182 la v0, 0xffff8008
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183 la v1, DRAM_DWR0_INIT
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184 sw v1, 0(v0)
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185
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186 # DREFC - Depends on clock requency
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187 la v0, 0xffff8800
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188 la v1, DRAM_DREFC_INIT
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189 sw v1, 0(v0)
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190 .endm
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191
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192 #define CYGPKG_HAL_MIPS_MEMC_DEFINED
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193
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194 #endif
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195
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196 ##-----------------------------------------------------------------------------
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197 ## TX39 interrupt handling.
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198
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199 #ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
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200
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201 #ifdef CYGPKG_HAL_MIPS_TX3904
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202
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203 # Set all ILRX registers to 0, masking all external interrupts.
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204 .macro hal_intc_init
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205
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206 #ifndef CYG_HAL_STARTUP_RAM
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207 la v0,0xFFFFC010
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208 move v1,zero
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209 sw v1,0(v0)
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210 sw v1,4(v0)
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211 sw v1,8(v0)
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212 sw v1,12(v0)
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213 #endif
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214 .endm
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215
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216 .macro hal_intc_decode vnum
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217 mfc0 v1,cause # get cause register
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218 nop
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219 srl v1,v1,10 # shift IP bits to ls bits
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220 andi v1,v1,0x7F # isolate IP bits
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221 la v0,hal_intc_translation_table # address of translation table
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222 add v0,v0,v1 # offset of index byte
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223 lb \vnum,0(v0) # load it
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224 .endm
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225
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226 #ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
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227 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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228 .macro hal_intc_translate inum,vnum
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229 move \vnum,zero # Just vector zero is supported
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230 .endm
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231 #else
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232 .macro hal_intc_translate inum,vnum
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233 move \vnum,\inum # Vector == interrupt number
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234 .endm
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235 #endif
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236 #endif
6
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237
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238 # This table translates from the 6 bit value supplied in the IP bits
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239 # of the cause register into a 0..16 offset into the ISR tables.
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240 .macro hal_intc_decode_data
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241 hal_intc_translation_table:
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242 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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243 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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244 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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245 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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246 .endm
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247
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248 #define CYGPKG_HAL_MIPS_INTC_DEFINED
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249
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250 #else
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251
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252 #error Unknown TX39 variant
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253
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254 #endif
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255
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256 #endif
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257
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258 #------------------------------------------------------------------------------
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259 # Diagnostics macros.
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260
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261 #if 0
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262 #ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
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263
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264 # Set up PIO0 for debugging output
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265 .macro hal_diag_init
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266 la v0,0xfffff500
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267 la v1,0xff
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268 sb v1,0(v0)
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269 la v1,0
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270 sb v1,4(v0)
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271 .endm
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272
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273 #define CYGPKG_HAL_MIPS_DIAG_DEFINED
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274
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275 #endif
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276 #endif
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277
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278 #------------------------------------------------------------------------------
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279 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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280 # end of variant.inc