ecos: packages/kernel/current/include/intr.hxx annotate

annotate packages/kernel/current/include/intr.hxx @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

Update all copyright banners to reflect FSF ownership; fix and improve licence text.

author	jlarmour
date	Thu, 29 Jan 2009 17:47:46 +0000
parents	13625e7b9d1f
children

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_KERNEL_INTR_HXX
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_KERNEL_INTR_HXX
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //==========================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // intr.hxx
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // Interrupt class declaration(s)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //==========================================================================
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	11 // ####ECOSGPLCOPYRIGHTBEGIN####
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	12 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	13 // This file is part of eCos, the Embedded Configurable Operating System.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	15 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	16 // eCos is free software; you can redistribute it and/or modify it under
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	17 // the terms of the GNU General Public License as published by the Free
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	18 // Software Foundation; either version 2 or (at your option) any later
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	19 // version.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	20 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	21 // eCos is distributed in the hope that it will be useful, but WITHOUT
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	24 // for more details.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	25 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	26 // You should have received a copy of the GNU General Public License
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	29 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	30 // As a special exception, if other files instantiate templates or use
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	31 // macros or inline functions from this file, or you compile this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	32 // and link it with other works to produce a work based on this file,
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	33 // this file does not by itself cause the resulting work to be covered by
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	34 // the GNU General Public License. However the source code for this file
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	35 // must still be made available in accordance with section (3) of the GNU
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	36 // General Public License v2.
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	37 //
2729 74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	38 // This exception does not invalidate any other reasons why a work based
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	39 // on this file might be covered by the GNU General Public License.
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	40 // -------------------------------------------
74dbf4c3f2e1 Update all copyright banners to reflect FSF ownership; fix and improve licence text. jlarmour parents: 2266 diff changeset	41 // ####ECOSGPLCOPYRIGHTEND####
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 //==========================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	45 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	47 // Date: 1997-09-09
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	48 // Purpose: Define Interrupt class interfaces
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	49 // Description: The classes defined here provide the APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	50 // interrupts.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 // Usage: #include "intr.hxx"
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	55 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56 //==========================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58 #include <cyg/kernel/ktypes.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	60 #include <cyg/kernel/smp.hxx>
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	61
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	62 // -------------------------------------------------------------------------
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	63 // Default definitions
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	64
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	65 // Some HALs define the ISR table to be a different size to the number
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	66 // of ISR vectors. These HALs will define CYGNUM_HAL_ISR_TABLE_SIZE. All
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	67 // other HALs will have the table size equal to the number of vectors.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	68
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	69 #ifndef CYGNUM_HAL_ISR_TABLE_SIZE
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	70 # define CYGNUM_HAL_ISR_TABLE_SIZE CYGNUM_HAL_ISR_COUNT
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	71 #endif
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	72
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	73 // -------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	74 // Function prototype typedefs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77 // VSR = Vector Service Routine. This is the code attached directly to an
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78 // interrupt vector. It is very architecture/platform specific and usually
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79 // must be written in assembler.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	81 typedef void cyg_VSR();
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83 // ISR = Interrupt Service Routine. This is called from the default
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 // VSR in response to an interrupt. It may access shared data but may
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 // not call kernel routines. The return value may be
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86 // Cyg_Interrupt::HANDLED and/or Cyg_Interrupt::CALL_DSR.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 typedef cyg_uint32 cyg_ISR(cyg_vector vector, CYG_ADDRWORD data);
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90 // DSR = Deferred Service Routine. This is called if the ISR returns
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91 // the Cyg_Interrupt::CALL_DSR bit. It is called at a "safe" point in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 // the kernel where it may make calls on kernel routines. The count
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 // argument indicates how many times the ISR has asked for the DSR to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94 // be posted since the last time the DSR ran.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 typedef void cyg_DSR(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data);
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 // -------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99 // Include HAL definitions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	101 class Cyg_Interrupt;
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	102
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	103 #include <cyg/hal/hal_arch.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	104
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	105 #include <cyg/hal/hal_intr.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	107 #ifndef HAL_INTERRUPT_STACK_CALL_PENDING_DSRS
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	108 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	109 Cyg_Interrupt::call_pending_DSRs_inner()
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	110 #endif
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	111
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	112 externC void interrupt_end(
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	113 cyg_uint32 isr_ret,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	114 Cyg_Interrupt *intr,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115 HAL_SavedRegisters *ctx
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	116 );
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	117
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	118 externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	119 externC void cyg_interrupt_call_pending_DSRs( void );
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	120
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	121 // -------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	122 // Interrupt class. This both represents each interrupt and provides a static
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	123 // interface for controlling the interrupt hardware.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	124
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	125 class Cyg_Interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	126 {
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	127
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	128 friend class Cyg_Scheduler;
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129 friend void interrupt_end( cyg_uint32,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 Cyg_Interrupt *,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 HAL_SavedRegisters *);
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	132 friend void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	133 friend void cyg_interrupt_call_pending_DSRs( void );
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135 cyg_vector vector; // Interrupt vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 cyg_priority priority; // Queuing priority
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 cyg_ISR *isr; // Pointer to ISR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	140
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	141 cyg_DSR *dsr; // Pointer to DSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	143 CYG_ADDRWORD data; // Data pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	145
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	146
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	147 // DSR handling interface called by the scheduler
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	148
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	149 // Check for pending DSRs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	150 static cyg_bool DSRs_pending();
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	151
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	152 // Call any pending DSRs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	153 static void call_pending_DSRs();
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	154 static void call_pending_DSRs_inner();
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	155
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	156 // DSR handling interface called by the scheduler and HAL
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	157 // interrupt arbiters.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	158
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	159 void post_dsr(); // Post the DSR for this interrupt
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	160
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	161
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163 // Data structures for handling DSR calls. We implement two DSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164 // handling mechanisms, a list based one and a table based
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	165 // one. The list based mechanism is safe with respect to temporary
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166 // overloads and will not run out of resource. However it requires
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	167 // extra data per interrupt object, and interrupts must be turned
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168 // off briefly when delivering the DSR. The table based mechanism
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169 // does not need unnecessary interrupt switching, but may be prone
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	170 // to overflow on overload. However, since a correctly programmed
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	171 // real time application should not experience such a condition,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	172 // the table based mechanism is more efficient for real use. The
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	173 // list based mechainsm is enabled by default since it is safer to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174 // use during development.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	175
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	178 static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_CPU_MAX]
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	179 [CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	180 CYGBLD_ANNOTATE_VARIABLE_INTR;
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	181
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	182 static cyg_ucount32 dsr_table_head[CYGNUM_KERNEL_CPU_MAX]
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	183 CYGBLD_ANNOTATE_VARIABLE_INTR;
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	184
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	185 static volatile cyg_ucount32 dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	186 CYGBLD_ANNOTATE_VARIABLE_INTR;
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	187
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	188 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	189 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	190
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	191 // Number of DSR posts made
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	192 volatile cyg_ucount32 dsr_count CYGBLD_ANNOTATE_VARIABLE_INTR;
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	193
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	194 // next DSR in list
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	195 Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	196
2266 13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	197 // head of static list of pending DSRs
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	198 static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	199 CYGBLD_ANNOTATE_VARIABLE_INTR;
2266 13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	200
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	201 # ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	202 // tail of static list of pending DSRs
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	203 static Cyg_Interrupt* volatile dsr_list_tail[CYGNUM_KERNEL_CPU_MAX]
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	204 CYGBLD_ANNOTATE_VARIABLE_INTR;
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	205 # endif
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	206
13625e7b9d1f Implement FIFO variant of scheduling of DSRs and make it the nickg parents: 210 diff changeset	207 #endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	208
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	209 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	210
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	211 // The default mechanism for handling interrupts is to attach just
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	212 // one Interrupt object to each vector. In some cases, and on some
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	213 // hardware, this is not possible, and each vector must carry a chain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	214 // of interrupts.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	215
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	216 Cyg_Interrupt *next; // Next Interrupt in list
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	217
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 // Chaining ISR inserted in HAL vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 static cyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data);
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 // Table of interrupt chains
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	222 static Cyg_Interrupt *chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	225
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	226 // Interrupt disable data. Interrupt disable can be nested. On
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	227 // each CPU this is controlled by disable_counter[cpu]. When the
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	228 // counter is first incremented from zero to one, the
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	229 // interrupt_disable_spinlock is claimed using spin_intsave(), the
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	230 // original interrupt enable state being saved in
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	231 // interrupt_disable_state[cpu]. When the counter is decremented
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	232 // back to zero the spinlock is cleared using clear_intsave().
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	233
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	234 // The spinlock is necessary in SMP systems since a thread
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	235 // accessing data shared with an ISR may be scheduled on a
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	236 // different CPU to the one that handles the interrupt. So, merely
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	237 // blocking local interrupts would be ineffective. SMP aware
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	238 // device drivers should either use their own spinlocks to protect
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	239 // data, or use the API supported by this class, via
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	240 // cyg_drv_isr_lock()/_unlock(). Note that it now becomes
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	241 // essential that ISRs do this if they are to be SMP-compatible.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	242
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	243 // In a single CPU system, this mechanism reduces to just
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	244 // disabling/enabling interrupts.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	245
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	246 // Disable level counter. This counts the number of times
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	247 // interrupts have been disabled.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	248 static volatile cyg_int32 disable_counter[CYGNUM_KERNEL_CPU_MAX]
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	249 CYGBLD_ANNOTATE_VARIABLE_INTR;
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	250
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	251 // Interrupt disable spinlock. This is claimed by any CPU that has
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	252 // disabled interrupts via the Cyg_Interrupt API.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	253 static Cyg_SpinLock interrupt_disable_spinlock CYGBLD_ANNOTATE_VARIABLE_INTR;
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	254
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	255 // Saved interrupt state. When each CPU first disables interrupts
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	256 // the original state of the interrupts are saved here to be
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	257 // restored later.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	258 static CYG_INTERRUPT_STATE interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	259 CYGBLD_ANNOTATE_VARIABLE_INTR;
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	260
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	262 public:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	263
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	264 Cyg_Interrupt // Initialize interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	265 (
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266 cyg_vector vector, // Vector to attach to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 cyg_priority priority, // Queue priority
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 CYG_ADDRWORD data, // Data pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269 cyg_ISR *isr, // Interrupt Service Routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	270 cyg_DSR *dsr // Deferred Service Routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	271 );
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	272
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	273 ~Cyg_Interrupt();
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	274
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	275 // ISR return values
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	276 enum {
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	277 HANDLED = 1, // Interrupt was handled
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	278 CALL_DSR = 2 // Schedule DSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279 };
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281 // Interrupt management
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283 void attach(); // Attach to vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 void detach(); // Detach from vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 // Static Interrupt management functions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	291 // Get the current service routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	292 static void get_vsr(cyg_vector vector, cyg_VSR **vsr);
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	293
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	294 // Install a vector service routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	295 static void set_vsr(
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	296 cyg_vector vector, // hardware vector to replace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	297 cyg_VSR *vsr, // my new service routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	298 cyg_VSR **old = NULL // pointer to old vsr, if required
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299 );
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302 // Static interrupt masking functions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304 // Disable interrupts at the CPU
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	305 static void disable_interrupts();
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	306
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	307 // Re-enable CPU interrupts
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308 static void enable_interrupts();
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	309
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	310 // Are interrupts enabled at the CPU?
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	311 static inline cyg_bool interrupts_enabled()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	312 {
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	313 return (0 == disable_counter[CYG_KERNEL_CPU_THIS()]);
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	314 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 // Get the vector for the following calls
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317 inline cyg_vector get_vector()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318 {
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	319 return vector;
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	320 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 // Static PIC control functions
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324 // Mask a specific interrupt in a PIC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325 static void mask_interrupt(cyg_vector vector);
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	326 // The same but not interrupt safe
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	327 static void mask_interrupt_intunsafe(cyg_vector vector);
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	328
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	329 // Clear PIC mask
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	330 static void unmask_interrupt(cyg_vector vector);
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	331 // The same but not interrupt safe
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 182 diff changeset	332 static void unmask_interrupt_intunsafe(cyg_vector vector);
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	333
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	334 // Acknowledge interrupt at PIC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	335 static void acknowledge_interrupt(cyg_vector vector);
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	336
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	337 // Change interrupt detection at PIC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	338 static void configure_interrupt(
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	339 cyg_vector vector, // vector to control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	340 cyg_bool level, // level or edge triggered
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	341 cyg_bool up // hi/lo level, rising/falling edge
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	342 );
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	343
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	344 #ifdef CYGPKG_KERNEL_SMP_SUPPORT
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	345
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	346 // SMP support for associating an interrupt with a specific CPU.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	347
177 4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	348 static void set_cpu( cyg_vector, HAL_SMP_CPU_TYPE cpu );
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	349 static HAL_SMP_CPU_TYPE get_cpu( cyg_vector );
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	350
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST jlarmour parents: 130 diff changeset	351 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	352 };
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	353
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	354 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	355 // -------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	356 // Check for pending DSRs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	357
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	358 inline cyg_bool Cyg_Interrupt::DSRs_pending()
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	359 {
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	360 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	361 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	362
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	363 return dsr_table_head[cpu] != dsr_table_tail[cpu];
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	366 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	367
182 f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST jlarmour parents: 177 diff changeset	368 return dsr_list[cpu] != NULL;
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	369
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	370 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 };
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372 #endif // CYGIMP_KERNEL_INTERRUPTS_DSRS
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	373
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374 // -------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 #endif // ifndef CYGONCE_KERNEL_INTR_HXX
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	376 // EOF intr.hxx

Mercurial > ecos

annotate packages/kernel/current/include/intr.hxx @ 2729:74dbf4c3f2e1 after-copyright-change-20090129