Mercurial > ecos
annotate packages/hal/sparclite/sleb/current/include/halboot.si @ 46:797268ecc331 ecos-sw-1999-10-19
Merge from eCos master repository on 1999-10-19-18:55:31-BST
| author | jlarmour |
|---|---|
| date | Tue, 19 Oct 1999 19:19:52 +0000 |
| parents | 443894e2e912 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */ |
| 2 #define CYGONCE_HAL_HALBOOT_SI | |
| 3 // ==================================================================== | |
| 4 // | |
| 5 // <platform>/halboot.si | |
| 6 // | |
| 7 // HAL bootup platform-oriented code (assembler) | |
| 8 // | |
| 9 // ==================================================================== | |
| 10 //####COPYRIGHTBEGIN#### | |
| 11 // | |
| 12 // ------------------------------------------- | |
| 13 // The contents of this file are subject to the Cygnus eCos Public License | |
| 14 // Version 1.0 (the "License"); you may not use this file except in | |
| 15 // compliance with the License. You may obtain a copy of the License at | |
| 16 // http://sourceware.cygnus.com/ecos | |
| 17 // | |
| 18 // Software distributed under the License is distributed on an "AS IS" | |
| 19 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 20 // License for the specific language governing rights and limitations under | |
| 21 // the License. | |
| 22 // | |
| 23 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 24 // September 30, 1998. | |
| 25 // | |
| 26 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 27 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 28 // ------------------------------------------- | |
| 29 // | |
| 30 //####COPYRIGHTEND#### | |
| 31 // ==================================================================== | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 34 // Author(s): hmt | |
| 35 // Contributors: hmt | |
| 36 // Date: 1999-02-01 | |
| 37 // Purpose: Bootup code, platform oriented. | |
| 38 // Description: | |
| 39 // | |
| 40 //####DESCRIPTIONEND#### | |
| 41 // | |
| 42 // ==================================================================== | |
| 43 | |
| 44 // External Platform Initial Setup | |
| 45 // | |
| 46 // This should set up RAM and caches, and calm down any external | |
| 47 // interrupt sources. | |
| 48 // | |
| 49 // It is just plain included in vectors.S | |
| 50 // | |
| 51 // RAM has not yet been touched at all; in fact all you have is a | |
| 52 // register window selected. | |
| 53 | |
| 54 | |
| 55 #ifdef CYG_HAL_STARTUP_RAM | |
|
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56 ! Hit the entry point instructions in situ |
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57 #ifndef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
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58 ! *unless* we are going to copy into a different RAM area anyway: |
| 2 | 59 ! copy the real instructions into the vector: |
| 60 rd %tbr, %g1 | |
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61 andn %g1, 0xfff, %g1 ! clear non-address bits |
| 2 | 62 set real_vector_instructions, %l0 |
| 63 ld [ %l0 ], %l1 | |
| 64 st %l1, [ %g1 ] ! into the vector | |
| 65 ld [ %l0 + 4 ], %l1 | |
| 66 st %l1, [ %g1 + 4 ] ! into the vector | |
| 67 ! then invalidate the instruction cache: | |
| 68 set 3, %l0 | |
| 69 set 0x00001000, %l1 | |
| 70 set 0x80001000, %l2 | |
| 71 sta %l0, [ %l1 ] 0x0c | |
| 72 sta %l0, [ %l2 ] 0x0c | |
| 73 ! and the data cache | |
| 74 sta %l0, [ %l1 ] 0x0e | |
| 75 sta %l0, [ %l2 ] 0x0e | |
| 76 nop | |
| 77 nop | |
| 78 nop | |
| 79 nop ! should be enough | |
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80 #endif // !CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
| 2 | 81 #endif // CYG_HAL_STARTUP_RAM |
| 82 | |
| 83 | |
| 84 #include <cyg/hal/hal_cpu.h> // a copy of CygMon~s cpu.h | |
| 85 | |
| 86 | |
| 87 /* Address of clock switch */ | |
| 88 #define CLKSW_ADDR 0x01000003 | |
| 89 | |
| 90 /* Address of SW1 */ | |
| 91 #define SW1_ADDR 0x02000003 | |
| 92 | |
| 93 /* Address of LED bank */ | |
| 94 #define LED_ADDR 0x02000003 | |
| 95 | |
| 96 #define SRAM_BASE 0x30000000 | |
| 97 #define SRAM_END 0x30080000 | |
| 98 | |
| 99 | |
| 100 #define DRAM_BASE 0x04000000 /* base of system DRAM */ | |
| 101 #define CS3_BASE 0x00000000 /* base of internal resource regs */ | |
| 102 #define CS3_ASI 7 /* ASI of internal resource regs */ | |
| 103 | |
| 104 // DRAM_BASE2 is defined so that we run the same RAM-sizing code in both | |
| 105 // RAM and ROM startup versions; but the RAM startup one starts RAM sizing | |
| 106 // at 0x043ff000 ie. 4k down from the top of the 4M available. | |
| 107 | |
| 108 #ifdef CYG_HAL_STARTUP_RAM | |
| 109 #define DRAM_BASE2 DRAM_BASE + 0x00400000 - 0x1000 | |
| 110 #else | |
| 111 #define DRAM_BASE2 DRAM_BASE | |
| 112 #endif | |
| 113 | |
| 114 .macro led val | |
| 115 sethi %hi(LED_ADDR),%l7 | |
| 116 set \val,%l6 | |
| 117 not %l6, %l6 | |
| 118 stb %l6,[%l7 + %lo(LED_ADDR)] | |
| 119 .endm | |
| 120 | |
| 121 /* | |
| 122 * First, setup chip selects. | |
| 123 * | |
| 124 * NB: The AMR_VAL macro actually inverts the mask bits. For me, it is | |
| 125 * more natural to write a 1 bit where I want the address compared. | |
| 126 * The sparc registers use 0 bits, instead. | |
| 127 */ | |
| 128 | |
| 129 /* -CS0 ADDR_MASK:0xfc000000 ASI_MASK:0xfc */ | |
| 130 set AMR_VAL(0xfc,0xfc000000),%l0 | |
| 131 mov AMR0,%l1 | |
| 132 sta %l0,[%l1] 1 | |
| 133 | |
| 134 /* -CS1 BASE:0x10000000 ASI:4 */ | |
| 135 set ARSR_VAL(4,0x10000000),%l0 | |
| 136 mov ARSR1,%l1 | |
| 137 sta %l0,[%l1] 1 | |
| 138 /* -CS1 ADDR MASK:0xf0000000 ASI MASK:0x7 */ | |
| 139 set AMR_VAL(7,0xf0000000),%l0 | |
| 140 mov AMR1,%l1 | |
| 141 sta %l0,[%l1] 1 | |
| 142 | |
| 143 /* -CS2 BASE:0x20000000 ASI:4 */ | |
| 144 set ARSR_VAL(4,0x20000000), %l0 | |
| 145 mov ARSR2,%l1 | |
| 146 sta %l0,[%l1] 1 | |
| 147 /* -CS2 ADDR MASK:0xf0000000 ASI MASK:0x7 */ | |
| 148 set AMR_VAL(7,0xf0000000),%l0 | |
| 149 mov AMR2,%l1 | |
| 150 sta %l0,[%l1] 1 | |
| 151 | |
| 152 /* -CS3 BASE:CS3_BASE ASI:CS3_ASI */ | |
| 153 set ARSR_VAL(CS3_ASI,CS3_BASE),%l0 | |
| 154 mov ARSR3,%l1 | |
| 155 sta %l0,[%l1] 1 | |
| 156 /* -CS3 ADDR MASK:0xffff0000 ASI MASK:0x7 */ | |
| 157 set AMR_VAL(7,0xffff0000),%l0 | |
| 158 mov AMR3,%l1 | |
| 159 sta %l0,[%l1] 1 | |
| 160 | |
| 161 /* -CS4 BASE: DRAM_BASE ASI:0xb */ | |
| 162 set ARSR_VAL(0xb,DRAM_BASE),%l0 | |
| 163 mov ARSR4,%l1 | |
| 164 sta %l0,[%l1] 1 | |
| 165 /* -CS4 ADDR MASK:0xfc000000 ASI MASK:0xfc */ | |
| 166 set AMR_VAL(0xfc,0xfc000000),%l0 | |
| 167 mov AMR4,%l1 | |
| 168 sta %l0,[%l1] 1 | |
| 169 | |
| 170 /* -CS5 BASE:0x30000000 ASI:0xb */ | |
| 171 set ARSR_VAL(0xb,0x30000000),%l0 | |
| 172 mov ARSR5,%l1 | |
| 173 sta %l0,[%l1] 1 | |
| 174 /* -CS5 ADDR MASK:0xfff80000 ASI MASK:0xfc */ | |
| 175 set AMR_VAL(0xfc,0xfff80000),%l0 | |
| 176 mov AMR5,%l1 | |
| 177 sta %l0,[%l1] 1 | |
| 178 | |
| 179 | |
| 180 /* | |
| 181 * Setup wait states. Each wait state register sets the wait states for | |
| 182 * a pair of chip selects. The lower bits hold the wait state info for | |
| 183 * the lower numbered chip select. | |
| 184 */ | |
| 185 | |
| 186 /* -CS0: 5 wait states, -CS1: 7 wait states */ | |
| 187 // set WSSR_VAL(7,7,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 | |
| 188 // set WSSR_VAL(4,4,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // FOUR -> CS1 | |
| 189 set WSSR_VAL(10,10,WSSR_WAITEN,5,5,WSSR_WAITEN),%l0 // TEN -> CS1 | |
| 190 mov WSSR0,%l1 | |
| 191 sta %l0,[%l1] 1 | |
| 192 | |
| 193 /* -CS2: wait states disabled, -CS3: wait states disabled */ | |
| 194 set WSSR_VAL(0,0,0,0,0,0),%l0 | |
| 195 mov WSSR1,%l1 | |
| 196 sta %l0,[%l1] 1 | |
| 197 | |
| 198 /* -CS4: wait states disabled, -CS5: 0 wait states */ | |
| 199 set WSSR_VAL(0,0,WSSR_WAITEN|WSSR_OVERRIDE,0,0,0),%l0 | |
| 200 mov WSSR2,%l1 | |
| 201 sta %l0,[%l1] 1 | |
| 202 | |
| 203 led 0x10 | |
| 204 | |
| 205 /* clear cache/BIU control register */ | |
| 206 mov CBIR,%l1 | |
| 207 sta %g0,[%l1] 1 | |
| 208 | |
| 209 /* Read clock switch to determine the value of the refresh timer */ | |
| 210 sethi %hi(CLKSW_ADDR),%l1 | |
| 211 ldub [%l1 + %lo(CLKSW_ADDR)],%l0 | |
| 212 btst 0x80,%l0 | |
| 213 bne,a 1f | |
| 214 mov 10,%l0 /* force to 10MHz if CLKSW-8 is ON */ | |
| 215 1: | |
| 216 umul %l0,15,%l0 | |
| 217 mov DRLD,%l1 | |
| 218 sta %l0,[%l1] 1 | |
| 219 mov REFTMR,%l1 | |
| 220 sta %l0,[%l1] 1 | |
| 221 | |
| 222 /* read SW1 to get DRAM page size */ | |
| 223 sethi %hi(SW1_ADDR),%l1 | |
| 224 ldub [%l1 + %lo(SW1_ADDR)],%l0 | |
| 225 btst 0x10,%l0 | |
| 226 be,a 1f | |
| 227 mov 0x0e,%l0 /* 1K page if branch taken (SW1-5 is OFF) */ | |
| 228 mov 0x06,%l0 /* 2K page (SW1-5 is OFF) */ | |
| 229 1: | |
| 230 mov SPGMR,%l1 | |
| 231 sta %l0,[%l1] 1 | |
| 232 | |
| 233 led 0x20 | |
| 234 | |
| 235 #ifdef CYG_HAL_STARTUP_ROM | |
| 236 /* Turn on all system services */ | |
| 237 mov SSCR_TIMER|SSCR_WAIT|SSCR_CS|SSCR_SAMEPG,%l0 | |
| 238 mov SSCR,%l1 | |
| 239 sta %l0,[%l1] 1 | |
| 240 nop | |
| 241 nop | |
| 242 nop | |
| 243 nop | |
| 244 | |
| 245 #endif | |
| 246 | |
| 247 led 0x30 | |
| 248 | |
| 249 /* | |
| 250 * Initialize caches. | |
| 251 */ | |
| 252 sethi %hi(0x1000),%l0 /* bank 1 invalidate */ | |
| 253 sethi %hi(0x80000000),%l1 /* bank 2 invalidate */ | |
| 254 mov 3,%l2 /* clear lock, lru, and valid bits */ | |
| 255 sta %l2,[%l0] 0xc /* do it - icache bank 1 */ | |
| 256 sta %l2,[%l0] 0xe /* do it - dcache bank 1 */ | |
| 257 sta %l2,[%l0 + %l1] 0xc /* do it - icache bank 2 */ | |
| 258 sta %l2,[%l0 + %l1] 0xe /* do it - dcache bank 2 */ | |
| 259 | |
| 260 /* now, enable caches and buffers */ | |
| 261 mov CBIR_ICEN|CBIR_DCEN|CBIR_PBEN|CBIR_WBEN,%l0 | |
| 262 mov CBIR,%l1 | |
| 263 sta %l0,[%l1] 1 | |
| 264 nop | |
| 265 nop | |
| 266 nop | |
| 267 nop | |
| 268 | |
| 269 /* enable data and insn bursts */ | |
| 270 mov BCR_IBE|BCR_DBE,%l0 | |
| 271 mov BCR,%l1 | |
| 272 sta %l0,[%l1] 1 | |
| 273 nop | |
| 274 nop | |
| 275 nop | |
| 276 nop | |
| 277 | |
| 278 /* | |
| 279 * DRAM setup/test. | |
| 280 */ | |
| 281 led 0x40 | |
| 282 | |
| 283 /* | |
| 284 * Test SW1-7 to determine normal or EDO mode. | |
| 285 * SW1-7 ON = EDO | |
| 286 * SW1-7 OFF = Normal. | |
| 287 */ | |
| 288 sethi %hi(SW1_ADDR),%l1 | |
| 289 ldub [%l1 + %lo(SW1_ADDR)],%l7 | |
| 290 mov DBANKR_SA04,%l0 /* DRAM starts at 0x04000000 */ | |
| 291 btst 0x40,%l7 | |
| 292 bne 1f /* branch if SW1-7 is OFF */ | |
| 293 mov SSCR_DRAM,%l1 | |
| 294 /* EDO DRAM, enable burst in SSCR and EDO in DBANKR */ | |
| 295 or %l1,SSCR_BURST,%l1 | |
| 296 or %l0,DBANKR_EDO,%l0 | |
| 297 1: | |
| 298 /* | |
| 299 * Now, test SW1 to get DRAM page and bank size. | |
| 300 * SW1-5 ON = 2k page, 16MB bank. (up to 64MB total) | |
| 301 * SW1-5 OFF = 1k page, 4MB bank. (up to 16MB total) | |
| 302 */ | |
| 303 btst 0x10,%l7 | |
| 304 bne,a 1f /* branch if OFF */ | |
| 305 or %l0,DBANKR_4M|DBANKR_CA10,%l0 /* 1K page */ | |
| 306 or %l0,DBANKR_16M|DBANKR_CA11,%l0 /* 2K page */ | |
| 307 1: | |
| 308 mov CS3_BASE+DBANKR,%l2 | |
| 309 sta %l0,[%l2] CS3_ASI | |
| 310 | |
| 311 mov DTIMR_RPS2|DTIMR_CBR3|DTIMR_CAS2|DTIMR_RP2,%l0 | |
| 312 mov CS3_BASE+DTIMR,%l2 | |
| 313 sta %l0,[%l2] CS3_ASI | |
| 314 | |
| 315 mov SSCR,%l2 | |
| 316 lda [%l2] 1, %l0 | |
| 317 or %l0,%l1,%l0 | |
| 318 sta %l0,[%l2] 1 | |
| 319 | |
| 320 /* | |
| 321 * Test SW1 to get potential DRAM limit. | |
| 322 * SW1-5 ON = 2k page, up to 64MB total | |
| 323 * SW1-5 OFF = 1k page, up to 16MB total | |
| 324 */ | |
| 325 btst 0x10,%l7 | |
| 326 bne,a 1f /* branch if OFF */ | |
| 327 sethi %hi(DRAM_BASE + 16*1024*1024),%l0 | |
| 328 sethi %hi(DRAM_BASE + 64*1024*1024),%l0 | |
| 329 1: | |
| 330 | |
| 331 /* subtract 4 to get last valid DRAM address */ | |
| 332 add %l0,-4,%l0 | |
| 333 | |
| 334 /* Assume maximim memory and fill with pattern */ | |
| 335 set DRAM_BASE2,%l2 | |
| 336 set 0xaaaaaaaa,%l3 | |
| 337 1: | |
| 338 st %l3,[%l2] | |
| 339 cmp %l2,%l0 | |
| 340 blt 1b | |
| 341 add %l2,4,%l2 | |
| 342 | |
| 343 /* | |
| 344 * Go back, read data and compare with written data. | |
| 345 * Fill in with zero as we go along. | |
| 346 */ | |
| 347 set DRAM_BASE2,%l2 | |
| 348 1: | |
| 349 ld [%l2],%l4 | |
| 350 cmp %l4,%l3 | |
| 351 bne 2f | |
| 352 st %g0,[%l2] | |
| 353 cmp %l2,%l0 | |
| 354 blt,a 1b | |
| 355 add %l2,4,%l2 | |
| 356 2: | |
| 357 led 0x50 | |
| 358 | |
| 359 sub %l2,64,%i6 | |
| 360 sethi %hi(DRAM_BASE),%l1 | |
| 361 sub %l2,%l1,%l0 | |
| 362 st %l0,[%i6] | |
| 363 | |
| 364 // NOTE that here, the frame pointer is set up to the top of RAM minus a | |
| 365 // little bit with the size of RAM at %fp (%i6) | |
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366 #ifdef CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM |
| 2 | 367 |
| 368 led 0x58 | |
| 369 | |
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370 ! copy the trampoline code into the base of RAM (__ram_vectors_start) |
| 2 | 371 ! including the two ~rogue~ instructions... |
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372 |
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373 .extern __ram_vectors_start |
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374 ! Using the true address here for the copy makes a badly-aligned |
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375 ! __ram_vectors less likely to hide as an obscure failure: |
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376 set __ram_vectors_start, %l0 ! get the start of RAM |
| 2 | 377 set rom_vectors, %l1 ! get the start of the trampoline |
| 378 set rom_vectors_end, %l2 ! ...and its end. | |
| 379 33: | |
| 380 ldd [ %l1 ], %l4 ! also uses %l5 | |
| 381 std %l4, [ %l0 ] | |
| 382 inc 8, %l1 | |
| 383 inc 8, %l0 | |
| 384 cmp %l1, %l2 | |
| 385 bl 33b | |
| 386 nop | |
| 387 | |
| 388 led 0x59 | |
| 389 | |
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390 sethi %hi(__ram_vectors_start), %g1 ! get the start of RAM |
| 2 | 391 andn %g1, 0xfff, %g1 |
| 392 set real_vector_instructions, %l0 | |
| 393 ld [ %l0 ], %l1 | |
| 394 st %l1, [ %g1 ] ! into the vector | |
| 395 ld [ %l0 + 4 ], %l1 | |
| 396 st %l1, [ %g1 + 4 ] ! into the vector | |
| 397 | |
| 398 led 0x5a | |
| 399 | |
| 400 ! then invalidate the instruction cache: | |
| 401 set 3, %l0 | |
| 402 set 0x00001000, %l1 | |
| 403 set 0x80001000, %l2 | |
| 404 sta %l0, [ %l1 ] 0x0c | |
| 405 sta %l0, [ %l2 ] 0x0c | |
| 406 | |
| 407 led 0x5b | |
| 408 | |
| 409 ! and the data cache | |
| 410 sta %l0, [ %l1 ] 0x0e | |
| 411 sta %l0, [ %l2 ] 0x0e | |
| 412 nop | |
| 413 nop | |
| 414 nop | |
| 415 nop ! should be enough | |
| 416 | |
| 417 led 0x5c | |
| 418 | |
| 419 ! and (re)set the tbr, finally. | |
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420 sethi %hi(__ram_vectors_start), %g1 |
| 2 | 421 andn %g1, 0xfff, %g1 |
| 422 wr %g1, %tbr ! Traps are at RAM start | |
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423 nop ! (__ram_vectors_start) |
| 2 | 424 nop |
| 425 nop | |
| 426 | |
| 427 led 0x5d | |
| 428 | |
| 429 #else | |
| 430 | |
| 431 led 0x5f | |
| 432 | |
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433 #endif // CYGIMP_HAL_SPARCLITE_COPY_VECTORS_TO_RAM (was CYG_HAL_STARTUP_ROM) |
| 2 | 434 |
| 435 ! turn on caches - copied from the book | |
| 436 #define set_size 64 | |
| 437 #define ini_tag 0 | |
| 438 #define adr1 0x00000000 | |
| 439 #define adr2 0x80000000 | |
| 440 #define step 16 | |
| 441 #define CTL_BITS 0x35 | |
| 442 | |
| 443 set set_size, %l7 | |
| 444 set adr1, %o1 | |
| 445 set adr2, %o2 | |
| 446 set ini_tag, %l0 | |
| 447 10: | |
| 448 sta %l0, [ %o1 ] 0x0c | |
| 449 sta %l0, [ %o1 ] 0x0e | |
| 450 sta %l0, [ %o2 ] 0x0c | |
| 451 sta %l0, [ %o2 ] 0x0e | |
| 452 add %o1, step, %o1 | |
| 453 subcc %l7, 1, %l7 | |
| 454 bne 10b | |
| 455 add %o2, step, %o2 | |
| 456 | |
| 457 set 0, %l1 | |
| 458 set CTL_BITS, %l2 | |
| 459 sta %l2, [ %l1 ] 0x01 | |
| 460 nop | |
| 461 nop | |
| 462 nop | |
| 463 nop ! delay to let caches stabilize | |
| 464 | |
| 465 led 0x60 | |
| 466 | |
| 467 // Now set up the 86940 | |
| 468 | |
| 469 #define TRGM0 0 | |
| 470 #define TRGM1 4 | |
| 471 #define REQSNS 8 | |
| 472 #define REQCLR 12 | |
| 473 #define IMASK 16 | |
| 474 #define IRLAT 20 | |
| 475 #define IMODE 24 | |
| 476 | |
| 477 sethi %hi( 0x10000000 ), %l1 ! base address of the 86940 companion | |
| 478 | |
| 479 set 0xfffe0000, %l4 ! mask all intrs | |
| 480 add %l1, IMASK, %l3 | |
| 481 sta %l4, [ %l3 ] 4 | |
| 482 | |
| 483 set 0x11400000, %l6 ! Channels 14,12,11 into Active Low | |
| 484 add %l1, TRGM0, %l3 | |
| 485 sta %l6, [ %l3 ] 4 | |
| 486 | |
| 487 set 0x05100000, %l6 ! Channels 5,4,2 into Active Low | |
| 488 add %l1, TRGM1, %l3 | |
| 489 sta %l6, [ %l3 ] 4 | |
| 490 | |
| 491 add %l1, REQCLR, %l3 ! clear all pending intrs | |
| 492 sta %l4, [ %l3 ] 4 | |
| 493 | |
| 494 set 0x00100000, %l6 ! clear the latch | |
| 495 add %l1, IRLAT, %l3 | |
| 496 sta %l6, [ %l3 ] 4 | |
| 497 | |
| 498 nop | |
| 499 nop | |
| 500 nop | |
| 501 | |
| 502 led 0x70 | |
| 503 | |
| 504 #endif /* CYGONCE_HAL_HALBOOT_SI */ | |
| 505 /* EOF halboot.si */ |