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annotate packages/hal/powerpc/mbx/current/src/mbx.S @ 62:7a6ac9edc838 ecos-sw-2000-01-24

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Merge from eCos master repository on 2000-01-24-19:43:49-GMT
author jlarmour
date Mon, 24 Jan 2000 21:43:17 +0000
parents e7ba79f6d3a8
children c38311975d4f
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1 ##=============================================================================
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2 ##
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3 ## mbx.S
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4 ##
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5 ## MBX board hardware setup
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6 ##
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7 ##=============================================================================
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8 #####COPYRIGHTBEGIN####
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Cygnus eCos Public License
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12 # Version 1.0 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://sourceware.cygnus.com/ecos
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15 #
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16 # Software distributed under the License is distributed on an "AS IS"
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Cygnus Operating System, released
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22 # September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Cygnus. Portions created
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25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
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26 # -------------------------------------------
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27 #
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28 #####COPYRIGHTEND####
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29 ##=============================================================================
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30 #######DESCRIPTIONBEGIN####
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31 ##
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32 ## Author(s): hmt
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33 ## Contributors:hmt
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34 ## Date: 1999-06-08
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35 ## Purpose: MBX board hardware setup
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36 ## Description: This file contains any code needed to initialize the
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37 ## hardware on a MBX860 or 821 PowerPC board.
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38 ##
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39 ######DESCRIPTIONEND####
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40 ##
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41 ##=============================================================================
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42
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43 #include <pkgconf/system.h>
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/hal_powerpc.h>
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46 #include <pkgconf/hal_powerpc_mbx.h>
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47
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48 #include <cyg/hal/ppc.inc> /* register symbols et al */
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49 #include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
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50 /* registers, IMM layout... */
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51 #include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
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52
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53 #------------------------------------------------------------------------------
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54 # this is kept thus for commonality with CygMon code
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55
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56 #if 40 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED
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57 # define __40MHZ 1
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58 #elif 50 == CYGHWR_HAL_POWERPC_MBX_BOARD_SPEED
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59 # define __50MHZ 1
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60 #else
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61 # error Bad Board speed defined: see CYGBLD_HAL_PLATFORM_H
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62 #endif
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63
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64 #------------------------------------------------------------------------------
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65 # this is controlled with one define for tidiness:
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66 # (and it is undefined by default)
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67
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68 //#define CYGPRI_RAM_START_PROGRAMS_UPMS
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69
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70 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
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71 # define CYGPRI_DO_PROGRAM_UPMS
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72 #endif
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73
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74 #if defined(CYGPRI_RAM_START_PROGRAMS_UPMS) && defined(CYGSEM_HAL_ROM_MONITOR)
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75 /* use old tables in a StubROM build iff RAM start will reprogram them */
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76 # define CYGPRI_USE_OLD_UPM_TABLES
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77 #endif
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78
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79 /* The intention is that we only set up the UPMs in ROM start, be it actual
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80 * ROM application start or Stub ROMs that we built from the same sources.
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81 *
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82 * The alternative approach - in which we have reliability doubts - is to
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83 * program the UPMs with *old* timing data in StubROM start, then
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84 * *reprogram* them with *new* timing data in RAM start - and of course
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85 * program with *new* timing data in plain ROM application start.
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86 * (Re-programming from new to new timing data fails - hence the suspicion
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87 * of reprogramming _at_all_, hence this private configuration)
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88 *
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89 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
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90 * - programming the UPMs exactly once - is obtained. Define it to get the
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91 * latter, untrusted behaviour.
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92 */
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93
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94 #------------------------------------------------------------------------------
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95
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96 // LED macro uses r3, r5: r4 left alone
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97 #define LED( x ) \
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98 lwi r5,0xfa100001; \
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99 lwi r3,((x) & 0xe); \
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100 stb r3,0(r5)
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101
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102
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103 #------------------------------------------------------------------------------
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104
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105 FUNC_START( hal_hardware_init )
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106
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107 # Throughout this routine, r4 is the base address of the control
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108 # registers. r3 and r5 are scratch in general.
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109
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110 lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
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111 mtspr CYGARC_REG_IMMR,r4
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112
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113 LED( 0 ) # turn all LEDs on
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114
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115 #define CACHE_UNLOCKALL 0x0a00
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116 #define CACHE_DISABLE 0x0400
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117 #define CACHE_INVALIDATEALL 0x0c00
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118 #define CACHE_ENABLE 0x0200
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119 #define CACHE_ENABLEBIT 0x8000
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120
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121 #define CACHE_FORCEWRITETHROUGH 0x0100
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122 #define CACHE_NOWRITETHROUGH 0x0300
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123 #define CACHE_CLEAR_LE_SWAP 0x0700
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124
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125 # DATA CACHE
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126 mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
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127 lis r3,CACHE_UNLOCKALL
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128 sync
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129 mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
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130
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131 lis r3,CACHE_INVALIDATEALL
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132 sync
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133 mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
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134
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135 lis r3,CACHE_DISABLE
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136 sync
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137 mtspr CYGARC_REG_DC_CST,r3 /* disable */
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138
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139 lis r3,CACHE_FORCEWRITETHROUGH
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140 sync
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141 mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
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142
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143 lis r3,CACHE_CLEAR_LE_SWAP
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144 sync
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145 mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
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146 /* (dunno what this is, but it sounds like a bad thing) */
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147
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148 # INSTRUCTION CACHE (no writeback modes)
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149 mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
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150 lis r3,CACHE_UNLOCKALL
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151 mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
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152 isync
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153 lis r3,CACHE_INVALIDATEALL
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154 mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
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155 isync
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156 lis r3,CACHE_DISABLE
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157 mtspr CYGARC_REG_IC_CST,r3 /* disable */
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158 isync
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159
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160 sync
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161
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162 /*
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163 * SIU Initialization.
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164 */
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165 /* lwi r3,0x0062A900*/
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166 /* lwi r3,0x006A2900*/
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167 lwi r3,0x00602400
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168 stw r3,SIUMCR(r4)
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169
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170 /*
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171 * Enable bus monitor. Disable Watchdog timer.
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172 */
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173 lwi r3,0xffffff88
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174 stw r3,SYPCR(r4)
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175
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176 /*
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177 * Clear REFA & REFB. Enable but freeze timebase.
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178 */
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179 lwi r3,0x00c2
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180 sth r3,TBSCR(r4)
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181
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182 /*
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183 * Unlock some RTC registers (see section 5.11.2)
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184 */
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185 lwi r3,0x55ccaa33
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186 stw r3,RTCSCK(r4)
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187 stw r3,RTCK(r4)
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188 stw r3,RTSECK(r4)
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189 stw r3,RTCALK(r4)
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190
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191 /*
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192 * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
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193 */
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194 li r3,0x00c3
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195 sth r3,RTCSC(r4)
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196
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197 /*
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198 * Clear periodic timer interrupt status.
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199 * Enable periodic timer and stop it on freeze.
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200 */
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201 li r3,0x0083
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202 sth r3,PISCR(r4)
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203
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204 #ifdef CYGPRI_DO_PROGRAM_UPMS
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205 /*
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206 * Perform UPM programming by writing to its 64 RAM locations.
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207 * Note that UPM initialization must be done before the Bank Register
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208 * initialization. Otherwise, system may hang when writing to Bank
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209 * Registers in certain cases.
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210 */
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211 lis r5,__upmtbl_start@h
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212 ori r5,r5,__upmtbl_start@l
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213 lis r6,__upmtbl_end@h
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214 ori r6,r6,__upmtbl_end@l
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215 sub r7,r6,r5 /* size of table */
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216 srawi r7,r7,2 /* in words */
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217
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218 li r6,0x0000 /* Command - OP=Write, UPMA, MAD=0 */
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219 1:
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220 lwz r3,0(r5) /* get data from table */
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221 stw r3,MDR(r4) /* store the data to MD register */
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222 stw r6,MCR(r4) /* issue command to MCR register */
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223 addi r5,r5,4 /* next entry in the table */
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224 addi r6,r6,1 /* next MAD address */
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225 cmpw r6,r7 /* done yet ? */
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226 blt 1b
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227 #endif // CYGPRI_DO_PROGRAM_UPMS
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228
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229 /*
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230 * Set refresh timer prescaler to divide by 8.
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231 */
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232 li r3,PTP_DIV32
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233 sth r3,MPTPR(r4)
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234
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235 /*
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236 * See Table 15-16 MPC860 User's Manual.
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237 *
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238 * PTA = 0x13 (clock dependent)
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239 * PTAE = enabled
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240 * AMA = 0
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241 * DSA = 2 cycle disable
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242 * G0CLA = A12
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243 * GPL_A4DIS = 0
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244 * RLFA = 0
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245 * WLFA = 0
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246 * TLFA = 0
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247 */
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248 #ifdef __50MHZ
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249 lwi r3,0x18801000
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250 #else
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251 lwi r3,0x13801000
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252 #endif
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253 stw r3,MAMR(r4)
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254
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255 /*
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256 * Base Register initialization.
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257 */
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258 /* BOOT ROM */
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259 lwi r3,0xfe000401 # 8-bit, GPCM
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260 #ifdef __50MHZ
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261 lwi r5,0xff800960 /* for 120nS devices, else 0xff800940 */
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262 #else
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263 lwi r5,0xff800930
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264 #endif
38
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265 #ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
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266 // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
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267 stw r3,BR7(r4)
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268 stw r5,OR7(r4)
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269 #else // Boot from 8-bit ROM - the default, on CS0
32
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270 stw r3,BR0(r4)
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271 stw r5,OR0(r4)
38
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272 #endif
32
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273 /* ONBOARD DRAM */
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274 lwi r3,0x00000081 # 32-bit, UPMA
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275 lwi r5,0xffc00400
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276 stw r3,BR1(r4)
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277 stw r5,OR1(r4)
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278
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279 /* DRAM DIMM BANK0 */
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280 lwi r3,0x00000080 # 32-bit, UPMA, INVALID
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281 lwi r5,0x00000400
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282 stw r3,BR2(r4)
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283 stw r5,OR2(r4)
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284
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285 /* DRAM DIMM BANK1 */
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286 lwi r3,0x00000080 # 32-bit, UPMA, INVALID
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287 lwi r5,0x00000400
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288 stw r3,BR3(r4)
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289 stw r5,OR3(r4)
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290
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291 /* NVRAM */
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292 lwi r3,0xfa000401 # 8-bit, GPCM
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293 #ifdef __50MHZ
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294 lwi r5,0xffe00930
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295 #else
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296 lwi r5,0xffe00920
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297 #endif
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298 stw r3,BR4(r4)
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299 stw r5,OR4(r4)
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300
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301 /* PCI BRIDGE MEM/IO */
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302 lwi r3,0x80000001 # 32-bit, GPCM
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303 lwi r5,0xa0000108
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304 stw r3,BR5(r4)
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305 stw r5,OR5(r4)
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306
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307 /* PCI BRIDGE REGISTERS */
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308 lwi r3,0xfa210001 # 32-bit, GPCM
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309 lwi r5,0xffff0108
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310 stw r3,BR6(r4)
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311 stw r5,OR6(r4)
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312
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313 /* FLASH */
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314 lwi r3,0xfc000001 # 32-bit, GPCM
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315 #ifdef __50MHZ
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316 lwi r5,0xff800940
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317 #else
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318 lwi r5,0xff800930
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319 #endif
38
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320 #ifdef CYGHWR_HAL_POWERPC_MBX_BOOT_32BIT_FLASH
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321 // Then the 32-bit FLASH device is on CS0, the "ROM" is on CS7
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322 stw r3,BR0(r4)
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323 stw r5,OR0(r4)
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324 #else // Boot from 8-bit ROM - so the 32-bit FLASH is on CS7
32
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325 stw r3,BR7(r4)
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326 stw r5,OR7(r4)
38
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327 #endif
32
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328 /*
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329 * SYSTEM CLOCK CONTROL REGISTER
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330 *
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331 * COM (1:2) = 0
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332 * TBS (6) = 1
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333 * RTDIV (7) = 0
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334 * RTSEL (8) = 0
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335 * CRQEN (9) = 0
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336 * PRQEN (10) = 0
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337 * EBDF (13:14) = 0
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338 * DFSYNC(17:18) = 0
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339 * DFBRG (19:20) = 0
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340 * DFNL (21:23) = 0
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341 * DFNH (24:26) = 0
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342 */
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343 lwi r3,0x02000000
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344 stw r3,SCCR(r4)
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345
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346 /*
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347 * The following sets up a 40MHz CPU clock.
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348 * I've seen 2 variations of MBX boards. One
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349 * uses a direct feed (1:1) 40MHz clock on
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350 * EXTCLK inputs. The other uses a 32KHz
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351 * oscillator on the OSCM inputs.
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352 */
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353 lwz r3,PLPRCR(r4)
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354 rlwinm r3,r3,12,20,31
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355 cmpwi r3,0
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356 beq 1f
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357
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358 /*
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359 * PLL, LOW POWER, AND RESET CONTROL REGISTER
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360 *
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361 * MF (0:11) = depends on source clock
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362 * SPLSS (16) = 1
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363 * TEXPS (17) = 1
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364 * TMIST (19) = 1
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365 * CSRC (21) = 0
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366 * LPM (22:23) = 0
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367 * CSR (24) = 0
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368 * LOLRE (25) = 0
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369 * FIOPD (26) = 0
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370 */
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371 /* MF (0:11) = 0x4c4 = 1220 = (40MHz/32.768KHz) */
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372 #ifdef __50MHZ
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373 lwi r3,0x5f50d000
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374 #else
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375 lwi r3,0x4c40d000
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376 #endif
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377 b 2f
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378 1:
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379 /* MF (0:11) = 0x000 = 1 = (1:1) */
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380 lwi r3,0x0000d000
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381 2:
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382 stw r3,PLPRCR(r4)
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383
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384 # mask interrupt sources in the SIU
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385 lis r2,0
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386 lwi r3,CYGARC_REG_IMM_SIMASK
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387 stw r2,0(r3)
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388
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389 # set the decrementer to maxint
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390 lwi r2,0
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391 not r2,r2
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392 mtdec r2
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393
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394 # and enable the timebase and decrementer to make sure
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395 li r2,1 # TBEnable and not TBFreeze
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396 lwi r3,CYGARC_REG_IMM_TBSCR
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397 sth r2,0(r3)
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398
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399 LED( 8 ) # turn red led off
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400
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401 #ifdef CYG_HAL_STARTUP_ROM
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402 # move return address to where the ROM is
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403 mflr r3
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404 andi. r3,r3,0xffff
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405 oris r3,r3,0xfe00
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406 mtlr r3
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407 #endif
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408
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409 blr
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410 FUNC_END( hal_hardware_init )
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411
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412
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413 #ifdef CYGPRI_DO_PROGRAM_UPMS
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414 # -------------------------------------------------------------------------
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415 # this table initializes the User Programmable Machine (UPM) nastiness
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416 # in the QUICC to control DRAM timing.
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417
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418 __upmtbl_start:
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419
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420 #ifdef __25MHZ
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421 /* UPM contents for 25MHz clk. DRAM: EDO,4K,60ns */
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422
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423 /* Single read. (offset 0 in upm RAM) */
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424 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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425 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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426
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427 /* Burst read. (offset 8 in upm RAM) */
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428 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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429 .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
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430 .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
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431 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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432
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433 /* Single write. (offset 18 in upm RAM) */
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434 .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x33ff6c0f
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435 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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436
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437 /* Burst write. (offset 20 in upm RAM) */
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diff changeset
438 .long 0xcfffe004, 0x0fffa404, 0x08ff2c00, 0x03ff2c0c
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439 .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
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440 .long 0x08ff2c00, 0x33ff6c0f, 0xffffec07, 0xffffec07
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441 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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442
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443 /* Refresh (offset 30 in upm RAM) */
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444 .long 0xc0ffec04, 0x07ffec04, 0x3fffec07, 0xffffec07
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445 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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446 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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447
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448 /* Exception. (offset 3c in upm RAM) */
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449 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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450 #endif
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451
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452 #ifdef __33MHZ
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453 /* UPM contents for 33MHz clk. DRAM: EDO,4K,60ns */
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454
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455 /* Single read. (offset 0 in upm RAM) */
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456 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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457 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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458
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459 /* Burst read. (offset 8 in upm RAM) */
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diff changeset
460 .long 0xcfffe004, 0x0fffe404, 0x08af2c04, 0x03af2c08
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461 .long 0x08af2c04, 0x03af2c08, 0x08af2c04, 0x03af2c08
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462 .long 0x08af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
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463 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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464
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465 /* Single write. (offset 18 in upm RAM) */
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466 .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x33ff6c07
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467 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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468
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469 /* Burst write. (offset 20 in upm RAM) */
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470 .long 0xcfffe004, 0x0fff2404, 0x08ff2c00, 0x03ff2c0c
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471 .long 0x08ff2c00, 0x03ff2c0c, 0x08ff2c00, 0x03ff2c0c
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472 .long 0x08ff2c00, 0x33ff6c07, 0xffffec07, 0xffffec07
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473 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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474
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475 /* Refresh (offset 30 in upm RAM) */
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476 .long 0xc0ffec04, 0x03ffec04, 0x1fffec07, 0xffffec07
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477 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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478 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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479
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480 /* Exception. (offset 3c in upm RAM) */
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481 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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482 #endif
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483
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484 #ifdef CYGPRI_USE_OLD_UPM_TABLES
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485
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486 // BUT new tables received from motorola are further down
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487
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488 // And I just discovered a good reason for using the NEW TABLES:
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489 // with the old tables, the cache zero-a-line command does not
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490 // work. It only zeros the first 12 bytes of the line, not all 16.
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491 // This may be related to having the cache set up write-through, as
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492 // seems necessary to have it work on this platform.
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493
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494 #ifdef __40MHZ
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495 /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
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496
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497 /* Single read. (offset 0 in upm RAM) */
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498 .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
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499 .long 0x03af2c08, 0xffffec07, 0xffffec07, 0xffffec07
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500
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501 /* Burst read. (offset 8 in upm RAM) */
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502 .long 0xefffe004, 0x0fffe004, 0x0eefac04, 0x00af2c04
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503 .long 0x03af2c08, 0x0caf2c04, 0x00af2c04, 0x03af2c08
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504 .long 0x0caf2c04, 0x00af2c04, 0x03af2c08, 0x0caf2c04
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505 .long 0x00af2c04, 0x03af2c08, 0xffffec07, 0xffffec07
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506
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507 /* Single write. (offset 18 in upm RAM) */
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508 .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
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509 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
510
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511 /* Burst write. (offset 20 in upm RAM) */
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512 .long 0xefffe004, 0x0fffa004, 0x0eff2c04, 0x00ff2c00
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513 .long 0x0fff2c0c, 0x0cff2c00, 0x03ff2c0c, 0x0cff2c00
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514 .long 0x03ff2c0c, 0x0cff2c00, 0x33ff6c07, 0xffffec07
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515 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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516
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517 /* Refresh (offset 30 in upm RAM) */
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518 .long 0xf0ffec04, 0x00ffec04, 0x0fffec04, 0x0fffec04
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519 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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520 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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521
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522 /* Exception. (offset 3c in upm RAM) */
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523 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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524 #endif
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525
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526 #ifdef __50MHZ
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527 /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
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528
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jlarmour
parents:
diff changeset
529 /* Single read. (offset 0 in upm RAM) */
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530 .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
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531 .long 0x00af2c04, 0x0faf2c08, 0xffffec07, 0xffffec07
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532
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533 /* Burst read. (offset 8 in upm RAM) */
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534 .long 0xffffe004, 0x0fffe004, 0x0fffe404, 0x0cafac04
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535 .long 0x00af2c04, 0x0faf2c08, 0x0caf2c04, 0x00af2c04
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536 .long 0x0faf2c08, 0x0caf2c04, 0x00af2c04, 0x0faf2c08
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537 .long 0x0caf2c04, 0x00af2c04, 0x0faf2c08, 0xffffec07
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538
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diff changeset
539 /* Single write. (offset 18 in upm RAM) */
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diff changeset
540 .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
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541 .long 0x00ff2c00, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
542
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diff changeset
543 /* Burst write. (offset 20 in upm RAM) */
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diff changeset
544 .long 0xffffe004, 0x0fffe004, 0x0fffa404, 0x0cff2c04
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545 .long 0x00ff2c00, 0x0fff2c08, 0x0cff2c04, 0x00ff2c00
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546 .long 0x0fff2c00, 0x0cff2c04, 0x00ff2c00, 0x0fff2c08
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547 .long 0x0cff2c04, 0x00ff2c00, 0xffffec07, 0xffffec07
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diff changeset
548
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549 /* Refresh (offset 30 in upm RAM) */
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diff changeset
550 .long 0xf0ffec04, 0xc0ffec04, 0x00ffec04, 0x0fffec04
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551 .long 0x1fffec07, 0xffffec07, 0xffffec07, 0xffffec07
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552 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
553
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554 /* Exception. (offset 3c in upm RAM) */
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diff changeset
555 .long 0xffffec07, 0xffffec07, 0xffffec07, 0xffffec07
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diff changeset
556 #endif
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557
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558 #else // !CYGPRI_USE_OLD_UPM_TABLES: use the NEW TABLES
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559
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560 // for RAM startup or ROM application when NOT making a stub rom,
62
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561 // ie. CYGSEM_HAL_ROM_MONITOR not defined.
32
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562
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563 #ifdef __40MHZ
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564 /* UPM contents for 40MHz clk. DRAM: EDO,4K,60ns */
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565 .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x30af0c00
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566 .long 0xf1bf4805, 0xffffc005, 0xffffc005, 0xffffc005
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567
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568 .long 0xcfafc004, 0x0fafc404, 0x0caf0c04, 0x03af0c08
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569 .long 0x0caf0c04, 0x03af0c08, 0x0caf0c04, 0x03af0c08
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570 .long 0x0caf0c04, 0x30af0c00, 0xf3bf4805, 0xffffc005
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571 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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572
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573 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x33ff4804
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574 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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575
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576 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
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577 .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
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578 .long 0x0cff0c00, 0x33ff4804, 0xffffc005, 0xffffc005
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579 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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580
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581 .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
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582 .long 0x3fffc004, 0xffffc005, 0xffffc005, 0xffffc005
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583 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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584
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585 .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
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586 #endif
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587
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588 #ifdef __50MHZ
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589 /* UPM contents for 50MHZ clk. DRAM: EDO,4K,60ns */
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590
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591 .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x10af0c04
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592 .long 0xf0af0c00, 0xf3bf4805, 0xffffc005, 0xffffc005
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593
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594 .long 0xcfafc004, 0x0fafc404, 0x0caf8c04, 0x00af0c04
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595 .long 0x07af0c08, 0x0caf0c04, 0x01af0c04, 0x0faf0c08
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596 .long 0x0caf0c04, 0x01af0c04, 0x0faf0c08, 0x0caf0c04
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597 .long 0x10af0c04, 0xf0afc000, 0xf3bf4805, 0xffffc005
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598
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599 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x13ff4804
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600 .long 0xffffc004, 0xffffc005, 0xffffc005, 0xffffc005
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601
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602 .long 0xcfff0004, 0x0fff0404, 0x0cff0c00, 0x03ff0c0c
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603 .long 0x0cff0c00, 0x03ff0c0c, 0x0cff0c00, 0x03ff0c0c
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604 .long 0x0cff0c00, 0x13ff4804, 0xffffc004, 0xffffc005
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605 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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606
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607 .long 0xfcffc004, 0xc0ffc004, 0x01ffc004, 0x0fffc004
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608 .long 0x1fffc004, 0xffffc004, 0xffffc005, 0xffffc005
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609 .long 0xffffc005, 0xffffc005, 0xffffc005, 0xffffc005
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610
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611 .long 0xffffc007, 0xffffc007, 0xffffc007, 0xffffc007
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612 #endif
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613 #endif // OLD/NEW TABLES == CYGPRI_USE_OLD_UPM_TABLES or not.
62
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614 // depending on CYGSEM_HAL_ROM_MONITOR and whether RAM
32
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615 // start re-initializes.
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616
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617 __upmtbl_end:
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618 #endif // CYGPRI_DO_PROGRAM_UPMS
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619
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620 FUNC_START(hal_mbx_set_led)
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621 andi. r3,r3,0x0e
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622 lwi r4,0xfa100001
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623 stb r3,0(r4)
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624 blr
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625 FUNC_END(hal_mbx_set_led)
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626
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627 FUNC_START(hal_mbx_flash_led)
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628 lwi r4,0xfa100001
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629 1:
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630 li r5,10
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631 stb r5,0(r4)
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632
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633 lis r5,10
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634 mtctr r5
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635 2:
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636 bdnz 2b
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637
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638 li r5,12
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639 stb r5,0(r4)
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640
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641 lis r5,10
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642 mtctr r5
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643 3:
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644 bdnz 3b
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645
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646 subi r3,r3,1
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647 cmpwi r3,0
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648 bge 1b
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649
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650 li r5,6
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651 stb r5,0(r4)
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652
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653 lis r5,20
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654 mtctr r5
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655 4:
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656 bdnz 4b
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657
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658 blr
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659 FUNC_END(hal_mbx_flash_led)
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660
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661
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662 #------------------------------------------------------------------------------
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663 # end of mbx.S