annotate packages/hal/cortexm/arch/current/src/hal_misc.c @ 2589:9da21501bc5b

* include/hal_intr.h: Fixed load value of SysTick counter. * src/hal_misc.c: Fixed wrap-around in hal_delay_us().
author nickg
date Wed, 05 Nov 2008 09:59:41 +0000
parents 07fc475e1c28
children d16f29a90821
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1 /*==========================================================================
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2 //
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3 // hal_misc.c
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4 //
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5 // Cortex-M exception vectors
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 2008 eCosCentric Limited.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 // -------------------------------------------
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36 //####ECOSGPLCOPYRIGHTEND####
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37 //==========================================================================
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38 //#####DESCRIPTIONBEGIN####
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39 //
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40 // Author(s): nickg
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41 // Date: 2008-07-30
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42 //
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43 //####DESCRIPTIONEND####
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44 //
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45 //========================================================================*/
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46
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47 #include <pkgconf/hal.h>
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48 #include <pkgconf/hal_cortexm.h>
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49 #ifdef CYGPKG_KERNEL
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50 #include <pkgconf/kernel.h>
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51 #endif
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52
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53 #include <cyg/infra/diag.h>
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54 #include <cyg/infra/cyg_type.h>
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55 #include <cyg/infra/cyg_trac.h> // tracing macros
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56 #include <cyg/infra/cyg_ass.h> // assertion macros
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57
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58 #include <cyg/hal/hal_arch.h> // HAL header
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59 #include <cyg/hal/hal_intr.h> // HAL header
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60
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61 #include <cyg/hal/drv_api.h>
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62
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63 //==========================================================================
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64
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65 typedef cyg_uint32 cyg_isr(cyg_uint32 vector, CYG_ADDRWORD data);
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66
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67 //==========================================================================
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68 // External references
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69
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70 // VSRs in vectors.S
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71 __externC void hal_default_exception_vsr( void );
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72 __externC void hal_default_interrupt_vsr( void );
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73 __externC void hal_default_svc_vsr( void );
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74 __externC void hal_pendable_svc_vsr( void );
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75 __externC void hal_switch_state_vsr( void );
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76
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77 // HAL and eCos functions
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78 __externC void hal_system_init( void );
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79 __externC void hal_variant_init( void );
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80 __externC void hal_platform_init( void );
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81 __externC void hal_ctrlc_isr_init( void );
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82 __externC void initialize_stub( void );
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83 __externC void cyg_hal_invoke_constructors( void );
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84 __externC void cyg_start( void );
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85 __externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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86 __externC void interrupt_end(cyg_uint32 isr_ret, CYG_ADDRWORD intr, HAL_SavedRegisters *regs );
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87
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88 // DATA and BSS locations
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89 __externC cyg_uint32 __ram_data_start;
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90 __externC cyg_uint32 __ram_data_end;
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91 __externC cyg_uint32 __rom_data_start;
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92 __externC cyg_uint32 __bss_start;
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93 __externC cyg_uint32 __bss_end;
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94
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95 // Scheduler lock
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96 __externC volatile cyg_uint32 cyg_scheduler_sched_lock;
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97
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98 //==========================================================================
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99 // Interrupt tables
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100
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101 volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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102 volatile CYG_ADDRWORD hal_interrupt_data [CYGNUM_HAL_ISR_COUNT];
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103 volatile CYG_ADDRESS hal_interrupt_objects [CYGNUM_HAL_ISR_COUNT];
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104
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105 //==========================================================================
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106 // Main entry point
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107 //
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108 // Enter here from reset via slot 1 of VSR table. The stack pointer is
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109 // already set to the value in VSR slot 0, usually the top of internal
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110 // SRAM.
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111
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112 void hal_reset_vsr( void )
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113 {
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114 // Call system init routine. This should do the minimum necessary
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115 // for the rest of the initialization to complete. For example set
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116 // up GPIO, the SRAM, power management etc. This routine is
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117 // usually supplied by the platform HAL. Calls to
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118 // hal_variant_init() and hal_platform_init() later will perform
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119 // the main initialization.
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120
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121 hal_system_init();
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122
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123 // Initialize vector table in base of SRAM.
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124 {
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125 register int i;
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126
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127 #if !defined(CYG_HAL_STARTUP_RAM)
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128
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129 // Only install the exception vectors for non-RAM startup. For
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130 // RAM startup we want these to continue to point to the original
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131 // VSRs, which will belong to RedBoot or GDB stubs.
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132
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133 for( i = 2; i < 15; i++ )
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134 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_exception_vsr;
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135
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136 #endif
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137 // Always point SVC and PENDSVC vectors to our local versions
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138
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139 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
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140 hal_vsr_table[CYGNUM_HAL_VECTOR_PENDSV] = (CYG_ADDRESS)hal_pendable_svc_vsr;
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141
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142 // For all startup type, redirect interrupt vectors to our VSR.
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143 for( i = CYGNUM_HAL_VECTOR_SYS_TICK ;
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144 i < CYGNUM_HAL_VECTOR_SYS_TICK + CYGNUM_HAL_VSR_MAX;
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145 i++ )
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146 hal_vsr_table[i] = (CYG_ADDRESS)hal_default_interrupt_vsr;
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147 }
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148
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149
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150 #if !defined(CYG_HAL_STARTUP_RAM)
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151
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152 // Ensure that the CPU will use the vector table we have just set
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153 // up.
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154
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155 # if defined(CYGHWR_HAL_CORTEXM_M3)
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156
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157 // On M3 parts, the NVIC contains a vector table base register. We
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158 // program this to relocate the vector table base to the base of
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159 // SRAM.
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160
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161 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_VTOR,
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162 CYGARC_REG_NVIC_VTOR_TBLOFF(0)|
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163 CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM );
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164
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165 # else
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166
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167 # error Unknown SRAM/VECTAB remap mechanism
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168
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169 # endif
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170
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171 // Use SVC to switch our state to thread mode running on the PSP.
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172 // We don't need to do this for RAM startup since the ROM code
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173 // will have already done it.
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174
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175 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_switch_state_vsr;
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176
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177 __asm__ volatile( "swi" );
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178
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179 hal_vsr_table[CYGNUM_HAL_VECTOR_SERVICE] = (CYG_ADDRESS)hal_default_svc_vsr;
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180
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181 #endif // !defined(CYG_HAL_STARTUP_RAM)
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182
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183 #if defined(CYG_HAL_STARTUP_ROM)
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184 // Relocate data from ROM to RAM
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185 {
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186 register cyg_uint32 *p, *q;
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187 for( p = &__ram_data_start, q = &__rom_data_start;
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188 p < &__ram_data_end;
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189 p++, q++ )
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190 *p = *q;
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191 }
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192 #endif
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193
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194 // Clear BSS
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195 {
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196 register cyg_uint32 *p;
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197 for( p = &__bss_start; p < &__bss_end; p++ )
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198 *p = 0;
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199 }
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200
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201 // Initialize interrupt vectors. Set the levels for all interrupts
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202 // to default values. Also set the default priorities of the
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203 // system handlers: all exceptions maximum priority except SVC and
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204 // PendSVC which are lowest priority.
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205 {
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206 register int i;
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207
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208 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR0, 0x00000000 );
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209 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR1, 0xFF000000 );
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210 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, 0x00FF0000 );
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211
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212 hal_interrupt_handlers[CYGNUM_HAL_INTERRUPT_SYS_TICK] = (CYG_ADDRESS)hal_default_isr;
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213
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214 for( i = 1; i < CYGNUM_HAL_ISR_COUNT; i++ )
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215 {
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216 hal_interrupt_handlers[i] = (CYG_ADDRESS)hal_default_isr;
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217 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(i-CYGNUM_HAL_INTERRUPT_EXTERNAL), 0x80 );
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218 }
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219 }
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220
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221 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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222 // Enable DebugMonitor exceptions. This is needed to enable single
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223 // step. This only has an effect if no external JTAG device is
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224 // attached.
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225 {
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226 CYG_ADDRESS base = CYGARC_REG_DEBUG_BASE;
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227 cyg_uint32 demcr;
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228
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229 HAL_READ_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
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230 demcr |= CYGARC_REG_DEBUG_DEMCR_MON_EN;
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231 HAL_WRITE_UINT32( base+CYGARC_REG_DEBUG_DEMCR, demcr );
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232 }
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233 #endif
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234
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235 #if !defined(CYG_HAL_STARTUP_RAM)
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236 // Enable Usage, Bus and Mem fault handlers. Do this for ROM and
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237 // JTAG startups. For RAM startups, this will have already been
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238 // done by the ROM monitor.
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239 {
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240 CYG_ADDRESS base = CYGARC_REG_NVIC_BASE;
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241 cyg_uint32 shcsr;
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242
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243 HAL_READ_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
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244 shcsr |= CYGARC_REG_NVIC_SHCSR_USGFAULTENA;
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245 shcsr |= CYGARC_REG_NVIC_SHCSR_BUSFAULTENA;
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246 shcsr |= CYGARC_REG_NVIC_SHCSR_MEMFAULTENA;
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247 HAL_WRITE_UINT32( base+CYGARC_REG_NVIC_SHCSR, shcsr );
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248 }
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249 #endif
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250
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251 // Call variant and platform init routines
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252 hal_variant_init();
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253 hal_platform_init();
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254
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255 // Start up the system clock
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256 HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
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257
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258 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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259
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260 initialize_stub();
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261
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262 #endif
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263
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264 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || \
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265 defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
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266
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267 hal_ctrlc_isr_init();
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268
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269 #endif
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270
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271 // Run through static constructors
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272 cyg_hal_invoke_constructors();
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273
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274 // Finally call into application
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275 cyg_start();
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276 for(;;);
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277 }
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278
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279 //==========================================================================
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280 // Handle Exceptions
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281 //
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282 // Exceptions are passed here from the initial VSR. We pass the
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283 // exception on to GDB stubs or the kernel as appropriate.
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284
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285 __externC void __handle_exception (void);
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286
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287 __externC HAL_SavedRegisters *_hal_registers;
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288 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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289 __externC void* volatile __mem_fault_handler;
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290 #endif
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291
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292 void hal_deliver_exception( HAL_SavedRegisters *regs )
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293 {
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294 // Special case handler for code which has chosen to take care
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295 // of data exceptions (i.e. code which expects them to happen)
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296 // This is common in discovery code, e.g. checking for a particular
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297 // device which may generate an exception when probing if the
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298 // device is not present
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299 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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300 if (__mem_fault_handler )
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301 {
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302 regs->u.exception.pc = (unsigned long)__mem_fault_handler;
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303 return; // Caught an exception inside stubs
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304 }
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305 #endif
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306
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307 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
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308
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309 _hal_registers = regs;
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310 __handle_exception();
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311
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312 #elif defined(CYGPKG_KERNEL_EXCEPTIONS)
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313
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314 cyg_hal_deliver_exception( regs->u.exception.vector, (CYG_ADDRWORD)regs );
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315
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316 #else
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317
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318 CYG_FAIL("Exception!!!");
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319
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320 #endif
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321 }
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322
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323 //==========================================================================
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324 // Handle Interrupts
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325 //
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326 // Interrupts are passed here from the low-level VSR in vectors.S. We
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327 // look up the ISR in the interrupt table, call it and if it requests
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328 // it, post a DSR. If necessary we also then cause the pendable SVC to
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329 // be requested.
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330 //
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331 // This function is also callable from ISR springboards that decode
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332 // additional interrupts via external controllers to deliver an
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333 // interrupt to a secondary vector.
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334
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335 void hal_deliver_interrupt( cyg_uint32 vector )
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336 {
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337 register cyg_uint32 isr_result;
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338 register cyg_isr *isr;
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339 cyg_bool pendsvc = false;
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340
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341 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \
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342 defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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343 cyg_instrument(RAISE_INTR, vector, 0 );
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344 #endif
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345
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346 isr = (cyg_isr *)hal_interrupt_handlers[vector];
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347
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348 // Call the ISR
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349 isr_result = isr( vector, hal_interrupt_data[vector] );
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350
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351
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352 #if !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
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353 // If the ISR has returned the CALL_DSR bit, post the DSR and set
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354 // the pendable SVC exception pending.
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355 if( isr_result & CYG_ISR_CALL_DSR )
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356 {
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357 cyg_interrupt_post_dsr( hal_interrupt_objects[vector] );
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358
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359 // Post the pendable SVC to call interrupt_end(). But only if
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360 // the scheduler lock is currently zero. If it is non zero
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361 // then interrupt_end will do nothing useful, so avoid calling
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362 // it.
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363 if( cyg_scheduler_sched_lock == 0 )
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364 pendsvc = true;
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365 }
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366 #else
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367 // When chaining we don't know here whether the nested interrupt
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368 // has posted a DSR, so we have to run interrupt_end() regardless.
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369 // However, the same considerations as above regarding the
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370 // scheduler lock still apply.
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371 if( cyg_scheduler_sched_lock == 0 )
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372 pendsvc = true;
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373 #endif
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374
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375 // Post the pendable SVC if required.
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376 if( pendsvc )
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377 {
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378 cyg_uint32 icsr;
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379 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
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380 icsr |= CYGARC_REG_NVIC_ICSR_PENDSVSET;
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381 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_ICSR, icsr );
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382 }
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383 }
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384
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385 //==========================================================================
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386 // Call interrupt_end()
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387 //
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388 // This is called on the thread stack as a result of the pendable
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389 // SVC. interrupt_end() decrements the scheduler lock, calls DSRs and
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390 // optionally switches thread context. So before calling, we must
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391 // increment the lock. The actual interrupt end processing has already
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392 // been done above in hal_default_interrupt_vsr1(), so the arguments
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393 // are zero.
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394
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395 __externC void hal_interrupt_end( void )
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396 {
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397 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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398 cyg_scheduler_sched_lock++;
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399 #endif
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400
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401 interrupt_end(0,0,0);
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402 }
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403
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404 //==========================================================================
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405 // Interrupt masking and configuration
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406
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407 #ifndef HAL_VAR_INTERRUPT_MASK
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408 #define HAL_VAR_INTERRUPT_MASK( __vector ) CYG_EMPTY_STATEMENT
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409 #define HAL_VAR_INTERRUPT_UNMASK( __vector ) CYG_EMPTY_STATEMENT
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410 #define HAL_VAR_INTERRUPT_SET_LEVEL( __vector, __level ) CYG_EMPTY_STATEMENT
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411 #define HAL_VAR_INTERRUPT_ACKNOWLEDGE( __vector ) CYG_EMPTY_STATEMENT
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412 #define HAL_VAR_INTERRUPT_CONFIGURE( __vector, __level, __up ) CYG_EMPTY_STATEMENT
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413 #endif
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414
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415 //--------------------------------------------------------------------------
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416
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417 __externC void hal_interrupt_mask( cyg_uint32 vector )
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418 {
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419 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
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420 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
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421 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_CER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
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422 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
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423 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
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424 {
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425 cyg_uint32 csr;
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426 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
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427 csr &= ~CYGARC_REG_SYSTICK_CSR_TICKINT;
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428 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
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429 }
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430 HAL_VAR_INTERRUPT_MASK( vector );
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431 }
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432
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433 //--------------------------------------------------------------------------
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434
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435 __externC void hal_interrupt_unmask( cyg_uint32 vector )
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436 {
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437 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
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438 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
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439 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SER(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
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440 CYGARC_REG_NVIC_IBIT(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL) );
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441 else if( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
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442 {
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443 cyg_uint32 csr;
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444 HAL_READ_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
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445 csr |= CYGARC_REG_SYSTICK_CSR_TICKINT;
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446 HAL_WRITE_UINT32(CYGARC_REG_SYSTICK_BASE+CYGARC_REG_SYSTICK_CSR, csr );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
447 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
448 HAL_VAR_INTERRUPT_UNMASK( vector );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
449 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
450
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
451 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
452
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
453 __externC void hal_interrupt_acknowledge( cyg_uint32 vector )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
454 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
455 HAL_VAR_INTERRUPT_ACKNOWLEDGE( vector );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
456 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
457
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
458 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
459
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
460 __externC void hal_interrupt_configure( cyg_uint32 vector, cyg_uint32 level, cyg_uint32 up )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
461 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
462 HAL_VAR_INTERRUPT_CONFIGURE( vector, level, up );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
463 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
464
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
465 //--------------------------------------------------------------------------
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
466
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
467 __externC void hal_interrupt_set_level( cyg_uint32 vector, cyg_uint32 level )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
468 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
469 cyg_uint32 l = (level)+CYGNUM_HAL_CORTEXM_PRIORITY_MAX;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
470 if( l > 0xFF ) l = 0xFF; /* clamp to 0xFF */
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
471 if( vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL &&
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
472 vector <= CYGNUM_HAL_INTERRUPT_NVIC_MAX )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
473 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
474 HAL_WRITE_UINT8( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_PR(vector-CYGNUM_HAL_INTERRUPT_EXTERNAL),
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
475 l );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
476 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
477 else if ( vector == CYGNUM_HAL_INTERRUPT_SYS_TICK )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
478 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
479 cyg_uint32 shpr2;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
480 HAL_READ_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
481 shpr2 &= ~0xFF000000;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
482 shpr2 |= (l)<<24;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
483 HAL_WRITE_UINT32( CYGARC_REG_NVIC_BASE+CYGARC_REG_NVIC_SHPR2, shpr2 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
484 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
485 HAL_VAR_INTERRUPT_SET_LEVEL( vector, level );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
486 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
487
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
488 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
489 // Microsecond delay
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
490 //
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
491 // The system RTC is set up to tick at 1MHz so all we need to do here
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
492 // is count ticks.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
493
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
494 __externC void hal_delay_us( cyg_int32 us )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
495 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
496 cyg_uint32 t0, t1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
497
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
498 HAL_CLOCK_READ( &t0 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
499 while ( us > 0 )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
500 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
501 HAL_CLOCK_READ( &t1 );
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
502 if( t1 < t0 )
2589
9da21501bc5b * include/hal_intr.h:
nickg
parents: 2580
diff changeset
503 us -= (t1 + CYGNUM_HAL_RTC_PERIOD - t0);
9da21501bc5b * include/hal_intr.h:
nickg
parents: 2580
diff changeset
504 else
9da21501bc5b * include/hal_intr.h:
nickg
parents: 2580
diff changeset
505 us -= t1 - t0;
2580
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
506 t0 = t1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
507 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
508 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
509
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
510 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
511 // C++ support - run initial constructors
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
512
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
513 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
514 cyg_bool cyg_hal_stop_constructors;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
515 #endif
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
516
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
517 typedef void (*pfunc) (void);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
518
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
519 extern pfunc __init_array_start__[];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
520 extern pfunc __init_array_end__[];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
521 #define CONSTRUCTORS_START (__init_array_start__[0])
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
522 #define CONSTRUCTORS_END (__init_array_end__)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
523 #define NEXT_CONSTRUCTOR(c) ((c)++)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
524
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
525 void
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
526 cyg_hal_invoke_constructors (void)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
527 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
528 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
529 static pfunc *p = &CONSTRUCTORS_START;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
530
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
531 cyg_hal_stop_constructors = 0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
532 for (; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p)) {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
533 (*p)();
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
534 if (cyg_hal_stop_constructors) {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
535 NEXT_CONSTRUCTOR(p);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
536 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
537 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
538 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
539 #else
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
540 pfunc *p;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
541
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
542 for (p = &CONSTRUCTORS_START; p != CONSTRUCTORS_END; NEXT_CONSTRUCTOR(p))
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
543 (*p)();
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
544 #endif
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
545 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
546
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
547 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
548 // Architecture default ISR
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
549
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
550 __externC cyg_uint32
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
551 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
552 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
553 CYG_TRACE1(true, "Interrupt: %d", vector);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
554
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
555 CYG_FAIL("Spurious Interrupt!!!");
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
556
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
557 return 0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
558 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
559
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
560 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
561 // GDB support
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
562 //
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
563 // These functions translate between HAL saved contexts and GDB
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
564 // register dumps.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
565
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
566 __externC void hal_get_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
567 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
568 int i;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
569 cyg_uint32 *p = gdbreg->f0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
570
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
571 switch( regs->u.type )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
572 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
573 case HAL_SAVEDREGISTERS_THREAD:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
574 for( i = 0; i < 13; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
575 gdbreg->gpr[i] = regs->u.thread.r[i];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
576 gdbreg->gpr[13] = regs->u.thread.sp;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
577 gdbreg->gpr[14] = regs->u.thread.pc;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
578 gdbreg->gpr[15] = regs->u.thread.pc;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
579 gdbreg->ps = 0x01000000;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
580 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
581
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
582 case HAL_SAVEDREGISTERS_EXCEPTION:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
583 gdbreg->gpr[0] = regs->u.exception.r0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
584 gdbreg->gpr[1] = regs->u.exception.r1;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
585 gdbreg->gpr[2] = regs->u.exception.r2;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
586 gdbreg->gpr[3] = regs->u.exception.r3;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
587 for( i = 0; i < 8; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
588 gdbreg->gpr[i+4] = regs->u.exception.r4_11[i];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
589 gdbreg->gpr[12] = regs->u.exception.r12;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
590 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.exception);
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
591 gdbreg->gpr[14] = regs->u.exception.lr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
592 gdbreg->gpr[15] = regs->u.exception.pc;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
593 gdbreg->ps = regs->u.exception.psr;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
594 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
595
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
596 case HAL_SAVEDREGISTERS_INTERRUPT:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
nickg
parents:
diff changeset
597 gdbreg->gpr[0] = regs->u.interrupt.r0;
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598 gdbreg->gpr[1] = regs->u.interrupt.r1;
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599 gdbreg->gpr[2] = regs->u.interrupt.r2;
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600 gdbreg->gpr[3] = regs->u.interrupt.r3;
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601 gdbreg->gpr[12] = regs->u.interrupt.r12;
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602 gdbreg->gpr[13] = ((cyg_uint32)regs)+sizeof(regs->u.interrupt);
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603 gdbreg->gpr[14] = regs->u.interrupt.lr;
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604 gdbreg->gpr[15] = regs->u.interrupt.pc;
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605 gdbreg->ps = regs->u.interrupt.psr;
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606 break;
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607 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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608
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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609 // Clear FP state, which we don't use
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610 for( i = 0; i < (8*3+1); i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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611 p[i] = 0;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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612
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613 }
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614
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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615 __externC void hal_set_gdb_registers( HAL_CORTEXM_GDB_Registers *gdbreg, HAL_SavedRegisters *regs )
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616 {
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617 int i;
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618
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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619 switch( regs->u.type )
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620 {
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621 case HAL_SAVEDREGISTERS_THREAD:
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622 for( i = 0; i < 13; i++ )
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623 regs->u.thread.r[i] = gdbreg->gpr[i];
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624 regs->u.thread.sp = gdbreg->gpr[13];
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625 regs->u.thread.pc = gdbreg->gpr[14];
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626 regs->u.thread.pc = gdbreg->gpr[15];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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627 break;
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628
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629 case HAL_SAVEDREGISTERS_EXCEPTION:
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630 regs->u.exception.r0 = gdbreg->gpr[0];
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631 regs->u.exception.r1 = gdbreg->gpr[1];
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632 regs->u.exception.r2 = gdbreg->gpr[2];
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633 regs->u.exception.r3 = gdbreg->gpr[3];
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634 for( i = 0; i < 8; i++ )
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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635 regs->u.exception.r4_11[i] = gdbreg->gpr[i+4];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
636 regs->u.exception.r12 = gdbreg->gpr[12];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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637 regs->u.exception.lr = gdbreg->gpr[14];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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638 regs->u.exception.pc = gdbreg->gpr[15];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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639 regs->u.exception.psr = gdbreg->ps;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
640 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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641
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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642 case HAL_SAVEDREGISTERS_INTERRUPT:
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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643 regs->u.interrupt.r0 = gdbreg->gpr[0];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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644 regs->u.interrupt.r1 = gdbreg->gpr[1];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
645 regs->u.interrupt.r2 = gdbreg->gpr[2];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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646 regs->u.interrupt.r3 = gdbreg->gpr[3];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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647 regs->u.interrupt.r12 = gdbreg->gpr[12];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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648 regs->u.interrupt.lr = gdbreg->gpr[14];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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649 regs->u.interrupt.pc = gdbreg->gpr[15];
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
650 regs->u.interrupt.psr = gdbreg->ps;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
651 break;
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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652 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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653 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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654
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655 //==========================================================================
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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656 // When compiling C++ code with static objects the compiler
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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657 // inserts a call to __cxa_atexit() with __dso_handle as one of the
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
658 // arguments. __cxa_atexit() would normally be provided by glibc, and
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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659 // __dso_handle is part of crtstuff.c. eCos applications
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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diff changeset
660 // are linked rather differently, so either a differently-configured
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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661 // compiler is needed or dummy versions of these symbols should be
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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662 // provided. If these symbols are not actually used then providing
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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663 // them is still harmless, linker garbage collection will remove them.
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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664
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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665 void
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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666 __cxa_atexit(void (*arg1)(void*), void* arg2, void* arg3)
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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667 {
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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668 }
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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669
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670 void* __dso_handle = (void*) &__dso_handle;
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671
07fc475e1c28 Add Cortex-M architecture HAL, STM32 variant and STM3210E platform HALs.
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672 //==========================================================================
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673 // EOF hal_misc.c