Mercurial > ecos
annotate packages/io/serial/current/src/arm/pid_serial.h @ 50:a0774359f013 ecos-sw-1999-11-02
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
| author | jlarmour |
|---|---|
| date | Tue, 02 Nov 1999 20:57:07 +0000 |
| parents | 1370c5e55234 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 #ifndef CYGONCE_ARM_PID_SERIAL_H |
| 2 #define CYGONCE_ARM_PID_SERIAL_H | |
| 3 | |
| 4 // ==================================================================== | |
| 5 // | |
| 6 // pid_serial.h | |
| 7 // | |
| 8 // Device I/O - Description of ARM PID7T serial hardware | |
| 9 // | |
| 10 // ==================================================================== | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 29 // ------------------------------------------- | |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 // ==================================================================== | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 35 // Author(s): gthomas | |
| 36 // Contributors: gthomas | |
| 37 // Date: 1999-02-04 | |
| 38 // Purpose: Internal interfaces for serial I/O drivers | |
| 39 // Description: | |
| 40 // | |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 43 // ==================================================================== | |
| 44 | |
| 45 // Description of serial ports on ARM PID7T | |
| 46 | |
| 47 struct serial_port { | |
| 48 unsigned char _byte[32]; | |
| 49 }; | |
| 50 | |
|
50
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
51 // Little-endian version |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
52 #if (CYG_BYTEORDER == CYG_LSBFIRST) |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
53 |
| 2 | 54 #define reg(n) _byte[n*4] |
| 55 | |
|
50
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
56 #else // Big-endian version |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
57 |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
58 #define reg(n) _byte[(n*4)^3] |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
59 |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
60 #endif |
|
a0774359f013
Merge from eCos master repository on 1999-11-02-17:02:15-GMT
jlarmour
parents:
48
diff
changeset
|
61 |
| 2 | 62 // Receive control registers |
| 63 #define rhr reg(0) // Receive holding register | |
| 64 #define isr reg(2) // Interrupt status register | |
| 65 #define lsr reg(5) // Line status register | |
| 66 #define msr reg(6) // Modem status register | |
| 67 #define scr reg(7) // Scratch register | |
| 68 | |
| 69 // Transmit control registers | |
| 70 #define thr reg(0) // Transmit holding register | |
| 71 #define ier reg(1) // Interrupt enable register | |
| 72 #define fcr reg(2) // FIFO control register | |
| 73 #define lcr reg(3) // Line control register | |
| 74 #define mcr reg(4) // Modem control register | |
| 75 #define ldl reg(0) // LSB of baud rate | |
| 76 #define mdl reg(1) // MSB of baud rate | |
| 77 | |
| 78 // Interrupt Enable Register | |
| 79 #define IER_RCV 0x01 | |
| 80 #define IER_XMT 0x02 | |
| 81 #define IER_LS 0x04 | |
| 82 #define IER_MS 0x08 | |
| 83 | |
| 84 // Line Control Register | |
| 85 #define LCR_WL5 0x00 // Word length | |
| 86 #define LCR_WL6 0x01 | |
| 87 #define LCR_WL7 0x02 | |
| 88 #define LCR_WL8 0x03 | |
| 89 #define LCR_SB1 0x00 // Number of stop bits | |
| 90 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words | |
| 91 #define LCR_SB2 0x04 | |
| 92 #define LCR_PN 0x00 // Parity mode - none | |
| 93 #define LCR_PE 0x0C // Parity mode - even | |
| 94 #define LCR_PO 0x08 // Parity mode - odd | |
| 95 #define LCR_PM 0x28 // Forced "mark" parity | |
| 96 #define LCR_PS 0x38 // Forced "space" parity | |
| 97 #define LCR_DL 0x80 // Enable baud rate latch | |
| 98 | |
| 99 // Line Status Register | |
| 100 #define LSR_RSR 0x01 | |
| 101 #define LSR_THE 0x20 | |
| 102 | |
| 103 // Modem Control Register | |
| 104 #define MCR_DTR 0x01 | |
| 105 #define MCR_RTS 0x02 | |
| 106 #define MCR_INT 0x08 // Enable interrupts | |
| 107 | |
| 108 // Interrupt status register | |
| 109 #define ISR_Tx 0x02 | |
|
6
d376b777e2ce
Merge from eCos master repository on 1999-05-14-19:27:43-BST
jlarmour
parents:
2
diff
changeset
|
110 #define ISR_Rx 0x04 |
|
48
1370c5e55234
Merge from eCos master repository on 1999-10-25-21:18:27-BST
jlarmour
parents:
6
diff
changeset
|
111 #define ISR_RxTO 0x0C |
| 2 | 112 |
| 113 static unsigned char select_word_length[] = { | |
| 114 LCR_WL5, // 5 bits / word (char) | |
| 115 LCR_WL6, | |
| 116 LCR_WL7, | |
| 117 LCR_WL8 | |
| 118 }; | |
| 119 | |
| 120 static unsigned char select_stop_bits[] = { | |
| 121 0, | |
| 122 LCR_SB1, // 1 stop bit | |
| 123 LCR_SB1_5, // 1.5 stop bit | |
| 124 LCR_SB2 // 2 stop bits | |
| 125 }; | |
| 126 | |
| 127 static unsigned char select_parity[] = { | |
| 128 LCR_PN, // No parity | |
| 129 LCR_PE, // Even parity | |
| 130 LCR_PO, // Odd parity | |
| 131 LCR_PM, // Mark parity | |
| 132 LCR_PS, // Space parity | |
| 133 }; | |
| 134 | |
| 135 static unsigned short select_baud[] = { | |
| 136 0, // Unused | |
| 137 0, // 50 | |
| 138 0, // 75 | |
| 139 1047, // 110 | |
| 140 0, // 134.5 | |
| 141 768, // 150 | |
| 142 0, // 200 | |
| 143 384, // 300 | |
| 144 192, // 600 | |
| 145 96, // 1200 | |
| 146 24, // 1800 | |
| 147 48, // 2400 | |
| 148 0, // 3600 | |
| 149 24, // 4800 | |
| 150 16, // 7200 | |
| 151 12, // 9600 | |
| 152 8, // 14400 | |
| 153 6, // 19200 | |
| 154 3, // 38400 | |
| 155 2, // 57600 | |
| 156 1, // 115200 | |
| 157 0, // 230400 | |
| 158 }; | |
| 159 | |
| 160 #endif // CYGONCE_ARM_PID_SERIAL_H |