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Merge from eCos master repository on 2001-06-08-21:11:51-BST
author jlarmour
date Sun, 10 Jun 2001 19:35:23 +0000
parents b939e9cada46
children e0c0827131d1
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): nickg, gthomas
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38 // Contributors: nickg, gthomas
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39 // Date: 1998-09-28
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40 // Purpose: Cache control API
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41 // Description: The macros defined here provide the HAL APIs for handling
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42 // cache control operations.
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43 // Usage:
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44 // #include <cyg/hal/hal_cache.h>
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45 // ...
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46 //
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47 //
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48 //####DESCRIPTIONEND####
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49 //
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50 //=============================================================================
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51
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52 #include <cyg/infra/cyg_type.h>
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53
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54 //-----------------------------------------------------------------------------
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55 // Cache dimensions
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56
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57 // Data cache
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58 //#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
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59 //#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
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60 //#define HAL_DCACHE_WAYS 0 // Associativity of the cache
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62 // Instruction cache
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63 //#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
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64 //#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
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65 //#define HAL_ICACHE_WAYS 0 // Associativity of the cache
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67 //#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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68 //#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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69
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70 //-----------------------------------------------------------------------------
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71 // Global control of data cache
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72
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73 // Enable the data cache
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74 #define HAL_DCACHE_ENABLE()
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75
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76 // Disable the data cache
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77 #define HAL_DCACHE_DISABLE()
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78
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79 // Invalidate the entire cache
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80 #define HAL_DCACHE_INVALIDATE_ALL()
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81
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82 // Synchronize the contents of the cache with memory.
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83 #define HAL_DCACHE_SYNC()
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84
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85 // Purge contents of data cache
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86 #define HAL_DCACHE_PURGE_ALL()
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87
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88 // Query the state of the data cache (does not affect the caching)
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89 #define HAL_DCACHE_IS_ENABLED(_state_) \
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90 CYG_MACRO_START \
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91 (_state_) = 0; \
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92 CYG_MACRO_END
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93
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94 // Set the data cache refill burst size
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95 //#define HAL_DCACHE_BURST_SIZE(_size_)
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96
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97 // Set the data cache write mode
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98 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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99
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100 //#define HAL_DCACHE_WRITETHRU_MODE 0
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101 //#define HAL_DCACHE_WRITEBACK_MODE 1
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102
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103 // Load the contents of the given address range into the data cache
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104 // and then lock the cache so that it stays there.
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105 //#define HAL_DCACHE_LOCK(_base_, _size_)
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106
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107 // Undo a previous lock operation
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108 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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109
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110 // Unlock entire cache
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111 //#define HAL_DCACHE_UNLOCK_ALL()
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112
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113 //-----------------------------------------------------------------------------
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114 // Data cache line control
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115
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116 // Allocate cache lines for the given address range without reading its
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117 // contents from memory.
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118 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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119
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120 // Write dirty cache lines to memory and invalidate the cache entries
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121 // for the given address range.
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122 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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123
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124 // Invalidate cache lines in the given range without writing to memory.
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125 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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126
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127 // Write dirty cache lines to memory for the given address range.
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128 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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129
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130 // Preread the given range into the cache with the intention of reading
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131 // from it later.
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132 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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133
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134 // Preread the given range into the cache with the intention of writing
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135 // to it later.
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136 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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137
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138 // Allocate and zero the cache lines associated with the given range.
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139 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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140
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141 //-----------------------------------------------------------------------------
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142 // Global control of Instruction cache
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143
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144 // Enable the instruction cache
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145 #define HAL_ICACHE_ENABLE()
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146
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147 // Disable the instruction cache
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148 #define HAL_ICACHE_DISABLE()
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149
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150 // Invalidate the entire cache
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151 #define HAL_ICACHE_INVALIDATE_ALL()
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152
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153 // Synchronize the contents of the cache with memory.
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154 #define HAL_ICACHE_SYNC()
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155
156
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156 // Query the state of the instruction cache (does not affect the caching)
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157 #define HAL_ICACHE_IS_ENABLED(_state_) \
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158 CYG_MACRO_START \
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159 (_state_) = 0; \
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160 CYG_MACRO_END
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161
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162 // Set the instruction cache refill burst size
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163 //#define HAL_ICACHE_BURST_SIZE(_size_)
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164
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165 // Load the contents of the given address range into the instruction cache
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166 // and then lock the cache so that it stays there.
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167 //#define HAL_ICACHE_LOCK(_base_, _size_)
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168
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169 // Undo a previous lock operation
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170 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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171
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172 // Unlock entire cache
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173 //#define HAL_ICACHE_UNLOCK_ALL()
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174
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175 //-----------------------------------------------------------------------------
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176 // Instruction cache line control
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177
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178 // Invalidate cache lines in the given range without writing to memory.
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179 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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180
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181 //-----------------------------------------------------------------------------
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182 #endif // ifndef CYGONCE_HAL_CACHE_H
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183 // End of hal_cache.h