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annotate packages/hal/i386/pcmb/current/include/pcmb.inc @ 161:ac086aa3217e

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Merge from eCos master repository on 2001-06-08-21:11:51-BST
author jlarmour
date Sun, 10 Jun 2001 19:35:23 +0000
parents
children e0c0827131d1
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1 #ifndef CYGONCE_HAL_PCMB_INC
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2 #define CYGONCE_HAL_PCMB_INC
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3 ##=============================================================================
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4 ##
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5 ## pcmb.inc
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6 ##
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7 ## PC platform support
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.1 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://www.redhat.com/
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17 #
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18 # Software distributed under the License is distributed on an "AS IS"
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): jskov
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37 ## Contributors:jskov, pjo, nickg
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38 ## Date: 1999-01-07
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39 ## Purpose: PC platform support
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40 ## Description: This file contains any PC specific assembler macros needed to
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41 ## run eCos on a standard i386 PC.
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42 ##
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43 ##
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44 ######DESCRIPTIONEND####
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45 ##
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46 ##=============================================================================
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47
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48
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49 ##=============================================================================
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50 ## CPU initialization
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51
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52 #ifndef CYGPKG_HAL_I386_CPU_INIT_DEFINED
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53
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54 #ifdef CYG_HAL_STARTUP_FLOPPY
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55
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56 #define CYGPKG_HAL_I386_CPU_INIT_DEFINED
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57
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58 .macro hal_cpu_init
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59
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60 /* This code is loaded from a floppy disk when the PC powers up. */
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61
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62 .code16
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63
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64 .extern _end
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65
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66 sectorsPerTrack = 18
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67 bytesPerSector = 512
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68 esPerSector = 32 /* = 512/16 */
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69
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70 cld /* always count up. */
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71
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72 /* Configure a stack that we can use. */
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73
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74 movl $_start, %eax
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75 movw %ax, %sp
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76 shr $4, %eax
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77 andl $0xF000, %eax
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78 movw %ax, %ss
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79
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80 /* Ask the BIOS for info about the amount of RAM available. We push
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81 * these onto the stack for later use.
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82 */
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83
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84 xorl %eax, %eax
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85 movb $0x88, %ah /* Get the amount of extended memory. */
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86 int $0x15
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87 shl $10, %eax
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88 pushl %eax
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89
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90 xorl %eax, %eax
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91 int $0x12 /* Get the amount of standard memory. */
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92 shl $10, %eax
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93 pushl %eax
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94
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95 /* reset floppy */
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96 movb $0,%ah
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97 movb $0,%dl
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98 int $0x13
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99 jc _error1
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100
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101 /* Read the rest of the image to _start. This code works by reading
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102 only one sector at a time to avoid "buffer cross 64k boundary" fatal
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103 problem... This is slow but should work in almost all situations.
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104 _start should be aligned on a 512 bytes boundary to be sure.
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105 */
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106
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107 /* destination pointer es:bx */
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108 /* With correct alignement, bx should be 0 and es should be a multiple
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109 * of 32. If not it may cause the "buffer cross 64k boundary" problem
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110 * (cf above)
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111 */
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112 movl $_start,%eax
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113 movw %ax,%bx
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114 andw $0xF,%bx
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115 shrl $4,%eax
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116 movw %ax, %es
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117
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118 /* initials head/track/sector */
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119 movw $0,%dx
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120 movw $1,%cx
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121
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122 movl $_edata,%edi
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123 addl $(bytesPerSector-1),%edi
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124 shrl $4,%edi
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125
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126 jmp _loadsector
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127
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128 _nextsector:
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129 movw %es,%ax
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130 cmpw %di,%ax
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131 jge _endload
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132 addw $esPerSector,%ax
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133 movw %ax,%es
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134 incb %cl
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135 cmpb $sectorsPerTrack, %cl
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136 jbe _loadsector /* next head ?*/
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137 movb $1, %cl
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138 incb %dh
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139 cmpb $1, %dh
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140 je _loadsector /* next track ? */
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141 movb $0, %dh
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142 incb %ch
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143
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144 _loadsector:
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145
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146 pushw %es
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147 pushw %di
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148 movw $0x0201, %ax
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149 clc
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150 int $0x13
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151 popw %di
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diff changeset
152 popw %es
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jlarmour
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diff changeset
153 jc _error2
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diff changeset
154
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155 movw $(0x0E*256+'.'), %ax /* print a dot */
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diff changeset
156 int $0x10
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diff changeset
157
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158 /* So go ahead and resume execution at the real starting address. This
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159 only serves to move us quickly to the real starting location; and has
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160 no effect after reading additional tracks. If we didn't jump after
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diff changeset
161 reading the first track, then we limit ourselves to reading images of
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162 30k bytes max before overwriting ourselves at 0x7C00.
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163 */
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164
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jlarmour
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165 ljmp $0,$_nextsector
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166
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167 _error1:
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168 movw $(0x0E*256+'1'), %ax /* print a ! */
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169 int $0x10
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170 jmp _error
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diff changeset
171
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172 _error2:
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jlarmour
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173 mov %ah,%al
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jlarmour
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174 pushw %ax
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175 shrw $4,%ax
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176 andw $15,%ax
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177 addw $0x0E41,%ax
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178 int $0x10
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179 popw %ax
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180 andw $15,%ax
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181 addw $0x0E41,%ax
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182 int $0x10
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diff changeset
183
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184 movw $(0x0E*256+'2'), %ax /* print a ! */
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185 int $0x10
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186 jmp _error
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187
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188 _error: /* halt on error */
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189 movw $(0x0E*256+'!'), %ax /* print a ! */
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190 int $0x10
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diff changeset
191
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diff changeset
192 cli
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diff changeset
193 hlt
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194 jmp _start
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diff changeset
195
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diff changeset
196
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197 /* Write the 0x55/0xAA signature at the end of the first
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198 block. Without this signature the BIOS won't consider this
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199 block to be bootable.
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200 */
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diff changeset
201
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202 . = _start + 510
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203 .byte 0x55
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204 .byte 0xAA
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205
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206 _endload:
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jlarmour
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207 1:
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diff changeset
208
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209 /* Lets be nice and wait for the diskette drive motor to go off
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210 * before continuing. */
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diff changeset
211
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212 movw $0x40, %ax
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213 movw %ax, %es
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214 movl $0x40, %ebx
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215 2: es
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216 movb (%bx), %al
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217 cmpb $0, %al
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218 jne 2b
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diff changeset
219
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220 /* Now we're all loaded up in memory. */
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diff changeset
221
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222 /* Disable interrupt handling. */
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223 cli
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diff changeset
224
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225 /* Load GDTR and IDTR. */
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226
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jlarmour
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227 lgdt %cs:gdt
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228 lidt %cs:idt
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diff changeset
229
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230 /* Switch to protected mode. */
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231 movl %cr0,%eax
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232 orb $1, %al
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233 movl %eax,%cr0
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234 ljmp $8, $3f
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diff changeset
235
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diff changeset
236 hlt
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diff changeset
237
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238 .align 4, 0xFF
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239 gdt:
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240 .word gdtEnd - gdtStart
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241 .long gdtStart
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diff changeset
242
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243 .align 4, 0xFF
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244 idt:
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245 .extern idtStart
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246 .word 0x07FF # space for 256 entries
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247 .long idtStart
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248
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249 gdtStart:
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250 /* Selector 0x00 == invalid. */
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251 .word 0x0000
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252 .word 0x0000
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253 .byte 0x00
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254 .byte 0x00
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diff changeset
255 .byte 0x00
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diff changeset
256 .byte 0x00
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diff changeset
257
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258 /* Selector 0x08 == code. */
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259 .word 0xFFFF
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260 .word 0x0000
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261 .byte 0x00
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262 .byte 0x9B
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diff changeset
263 .byte 0xCF
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264 .byte 0x00
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diff changeset
265
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266 /* Selector 0x10 == data. */
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267 .word 0xFFFF
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268 .word 0x0000
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269 .byte 0x00
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270 .byte 0x93
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271 .byte 0xCF
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272 .byte 0x00
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diff changeset
273
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274 /* Selector 0x18 == shorter code: faults any code
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275 * access 0xF0000000-0xFFFFFFFF.
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276 */
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277 .word 0xFFFF
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278 .word 0x0000
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279 .byte 0x00
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280 .byte 0x9B
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diff changeset
281 .byte 0xC7
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diff changeset
282 .byte 0x00
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diff changeset
283
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284 /* Selector 0x20 == data; faults any access 0xF0000000-0xFFFFFFFF. */
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285 .word 0xFFFF
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286 .word 0x0000
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diff changeset
287 .byte 0x00
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diff changeset
288 .byte 0x93
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diff changeset
289 .byte 0xC7
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290 .byte 0x00
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diff changeset
291
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292 .align 4, 0xFF
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293 gdtEnd:
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diff changeset
294
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295 .code32
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jlarmour
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296 3:
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jlarmour
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diff changeset
297
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jlarmour
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298 movw $0x10, %ax
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diff changeset
299 movw %ax, %ds
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jlarmour
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diff changeset
300 movw %ax, %es
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jlarmour
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diff changeset
301 movw %ax, %fs
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jlarmour
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diff changeset
302 movw %ax, %gs
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diff changeset
303
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jlarmour
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304 /* Make our new stack point to the same place as the old one. */
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305 xorl %ebx, %ebx
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jlarmour
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306 movw %ss, %bx
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307 shl $4, %ebx
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308 addl %esp, %ebx
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309 movw %ax, %ss
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310 movl %ebx, %esp
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311 movl $0, %ebp
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312
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313 /* Reset the flags register. */
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314 pushl $0
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315 popfl
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316
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317 hal_cpu_init_end:
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318 nop
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319
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320 .endm /* hal_cpu_init */
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321
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322 #endif /* CYG_HAL_STARTUP_FLOPPY */
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323
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324 #endif // CYGPKG_HAL_I386_CPU_INIT_DEFINED
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325
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326 ##=============================================================================
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327 ## Interrupt controller support
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328
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329 #define CYGPKG_HAL_I386_INTC_INIT_DEFINED
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330
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331 #ifndef CYG_HAL_STARTUP_RAM
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332
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333 .macro hal_intc_init
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334
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335 # The interrupt controller is configured so that IRQ levels 0-7 trigger
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336 # interrupt vector 32-39; levels 8-15 trigger 40-47.
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337 movb $0x11, %al
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338 outb %al, $0x20
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339 movb $0x20, %al
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340 outb %al, $0x21
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341 movb $0x04, %al
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342 outb %al, $0x21
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343 movb $0x01, %al
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344 outb %al, $0x21
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345 movb $0xFB, %al /* Mask off all interrupts except 2. */
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346 outb %al, $0x21
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347
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348 movb $0x11, %al
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349 outb %al, $0xA0
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350 movb $0x28, %al
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351 outb %al, $0xA1
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352 movb $0x02, %al
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353 outb %al, $0xA1
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354 movb $0x01, %al
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355 outb %al, $0xA1
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356 movb $0xFF, %al /* Mask off all interrupts. */
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357 outb %al, $0xA1
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358
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359 .endm /* hal_intc_init */
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360
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361 #else
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362
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363 # No need to do any initialization in RAM startup
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364 .macro hal_intc_init
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365 .endm
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366
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367 #endif
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368
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369 .macro hal_intc_ack vector
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370 # Use any registers you like.
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371 movl \vector, %edx
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372 movb $0x20, %al
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373 cmpl $0x20, %edx
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374 jl 8f
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375 cmpl $0x28, %edx
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376 jl 9f
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377 outb %al, $0xA0
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378 9: outb %al, $0x20
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379 8: nop
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380 .endm
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381
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382 ##=============================================================================
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383 #endif // ifndef CYGONCE_HAL_PCMB_INC
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384 ## end of pcmb.inc