Mercurial > ecos
annotate packages/hal/arm/aeb/current/include/hal_cache.h @ 66:bf00f99aec69 ecos-sw-2000-02-02
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| author | jlarmour |
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| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | e0c0827131d1 |
| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.1 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://www.redhat.com/ |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 2 | 33 //####COPYRIGHTEND#### |
| 34 //============================================================================= | |
| 35 //#####DESCRIPTIONBEGIN#### | |
| 36 // | |
| 37 // Author(s): nickg, gthomas | |
| 38 // Contributors: nickg, gthomas | |
| 39 // Date: 1998-09-28 | |
| 40 // Purpose: Cache control API | |
| 41 // Description: The macros defined here provide the HAL APIs for handling | |
| 42 // cache control operations. | |
| 43 // Usage: | |
| 44 // #include <cyg/hal/hal_cache.h> | |
| 45 // ... | |
| 46 // | |
| 47 // | |
| 48 //####DESCRIPTIONEND#### | |
| 49 // | |
| 50 //============================================================================= | |
| 51 | |
| 52 #include <cyg/infra/cyg_type.h> | |
| 53 #include <cyg/hal/hal_io.h> | |
| 54 | |
| 55 //----------------------------------------------------------------------------- | |
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56 // Cache dimensions - one unified cache |
| 2 | 57 |
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58 #define HAL_CACHE_UNIFIED |
| 2 | 59 |
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60 #define HAL_UCACHE_SIZE 0x800 // Size of cache in bytes |
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61 #define HAL_UCACHE_LINE_SIZE 4 // Size of a cache line |
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62 #define HAL_UCACHE_WAYS 4 // Associativity of the cache |
| 2 | 63 |
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64 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS)) |
| 2 | 65 |
| 66 // Cache & SRAM control | |
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67 #define CYG_DEVICE_CCR 0xFFFFA400 |
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68 #define CYG_DEVICE_LSCR 0xFFFFA404 |
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69 #define CYG_DEVICE_CACHE_MEM 0x60000800 |
| 2 | 70 |
| 71 #define CCR_E 0x01 // Cache enabled | |
| 72 #define CCR_S 0x02 // SRAM mode enabled | |
| 73 #define CCR_F 0x04 // Flush mode enabled | |
| 74 #define CCR_I 0x08 // Invalidate mode | |
| 75 | |
| 76 #define LCSR_E 0x01 // Local SRAM enabled | |
| 77 #define LCSR_L 0x02 // Local SRAM mapped to high memory | |
| 78 | |
| 79 //----------------------------------------------------------------------------- | |
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80 // Global control of cache |
| 2 | 81 |
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82 // Enable the cache |
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83 #define HAL_UCACHE_ENABLE() \ |
| 2 | 84 { \ |
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85 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_E); \ |
| 2 | 86 } |
| 87 | |
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88 // Disable the cache |
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89 #define HAL_UCACHE_DISABLE() \ |
| 2 | 90 { \ |
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91 HAL_WRITE_UINT8(CYG_DEVICE_CCR, 0); \ |
| 2 | 92 } |
| 93 | |
| 94 // Invalidate the entire cache | |
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95 #define HAL_UCACHE_INVALIDATE_ALL() \ |
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96 { \ |
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97 register cyg_uint8 old_ccr; \ |
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98 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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99 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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100 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
| 2 | 101 } |
| 102 | |
| 103 // Synchronize the contents of the cache with memory. | |
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104 #define HAL_UCACHE_SYNC() \ |
| 2 | 105 { \ |
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106 register volatile cyg_uint8 *cache_SRAM = \ |
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107 (volatile cyg_uint8*) CYG_DEVICE_CACHE_MEM; \ |
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108 register int i; \ |
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109 register cyg_uint8 old_ccr; \ |
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110 HAL_READ_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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111 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_F); \ |
| 2 | 112 for (i = 0; i < HAL_DCACHE_SETS; i++) { \ |
| 113 *cache_SRAM = 0; \ | |
| 114 cache_SRAM += HAL_DCACHE_LINE_SIZE; \ | |
| 115 } \ | |
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116 HAL_WRITE_UINT8(CYG_DEVICE_CCR, CCR_I); \ |
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117 HAL_WRITE_UINT8(CYG_DEVICE_CCR, old_ccr); \ |
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118 } |
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119 |
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120 // Query the state of the cache |
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121 #define HAL_UCACHE_IS_ENABLED(_state_) \ |
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122 { \ |
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123 cyg_uint8 __ccr; \ |
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124 HAL_READ_UINT8(CYG_DEVICE_CCR, __ccr); \ |
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125 (_state_) = (CCR_E == __ccr) ? 1 : 0; \ |
| 2 | 126 } |
| 127 | |
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128 // Purge contents of cache |
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129 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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130 |
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131 // Set the cache refill burst size |
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132 //#define HAL_UCACHE_BURST_SIZE(_size_) |
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133 |
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134 // Set the cache write mode |
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135 //#define HAL_UCACHE_WRITE_MODE( _mode_ ) |
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136 |
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137 //#define HAL_UCACHE_WRITETHRU_MODE 0 |
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138 //#define HAL_UCACHE_WRITEBACK_MODE 1 |
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139 |
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140 // Load the contents of the given address range into the cache |
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141 // and then lock the cache so that it stays there. |
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142 //#define HAL_UCACHE_LOCK(_base_, _size_) |
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143 |
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144 // Undo a previous lock operation |
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145 //#define HAL_UCACHE_UNLOCK(_base_, _size_) |
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146 |
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147 // Unlock entire cache |
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148 //#define HAL_UCACHE_UNLOCK_ALL() |
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149 |
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150 //----------------------------------------------------------------------------- |
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151 // Cache line control |
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152 |
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153 // Allocate cache lines for the given address range without reading its |
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154 // contents from memory. |
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155 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ ) |
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156 |
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157 // Write dirty cache lines to memory and invalidate the cache entries |
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158 // for the given address range. |
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159 //#define HAL_UCACHE_FLUSH( _base_ , _size_ ) |
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160 |
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161 // Invalidate cache lines in the given range without writing to memory. |
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162 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ ) |
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163 |
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164 // Write dirty cache lines to memory for the given address range. |
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165 //#define HAL_UCACHE_STORE( _base_ , _size_ ) |
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166 |
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167 // Preread the given range into the cache with the intention of reading |
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168 // from it later. |
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169 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ ) |
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170 |
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171 // Preread the given range into the cache with the intention of writing |
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172 // to it later. |
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173 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ ) |
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174 |
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175 // Allocate and zero the cache lines associated with the given range. |
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176 //#define HAL_UCACHE_ZERO( _base_ , _size_ ) |
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177 |
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178 //----------------------------------------------------------------------------- |
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179 |
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180 //----------------------------------------------------------------------------- |
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181 // Data and instruction cache macros map onto the both-cache macros |
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182 |
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183 //----------------------------------------------------------------------------- |
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184 // Global control of data cache |
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185 |
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186 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE |
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187 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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188 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS |
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189 #define HAL_DCACHE_SETS HAL_UCACHE_SETS |
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190 |
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191 // Enable the data cache |
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192 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE() |
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193 |
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194 // Disable the data cache |
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195 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE() |
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196 |
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197 // Invalidate the entire cache |
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198 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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199 |
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200 // Synchronize the contents of the cache with memory. |
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201 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC() |
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202 |
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203 // Query the state of the data cache |
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204 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 205 |
| 206 // Set the data cache refill burst size | |
| 207 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 208 | |
| 209 // Set the data cache write mode | |
| 210 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 211 | |
| 212 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 213 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 214 | |
| 215 // Load the contents of the given address range into the data cache | |
| 216 // and then lock the cache so that it stays there. | |
| 217 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 218 | |
| 219 // Undo a previous lock operation | |
| 220 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 221 | |
| 222 // Unlock entire cache | |
| 223 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 224 | |
| 225 //----------------------------------------------------------------------------- | |
| 226 // Data cache line control | |
| 227 | |
| 228 // Allocate cache lines for the given address range without reading its | |
| 229 // contents from memory. | |
| 230 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 231 | |
| 232 // Write dirty cache lines to memory and invalidate the cache entries | |
| 233 // for the given address range. | |
| 234 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 235 | |
| 236 // Invalidate cache lines in the given range without writing to memory. | |
| 237 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 238 | |
| 239 // Write dirty cache lines to memory for the given address range. | |
| 240 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 241 | |
| 242 // Preread the given range into the cache with the intention of reading | |
| 243 // from it later. | |
| 244 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 245 | |
| 246 // Preread the given range into the cache with the intention of writing | |
| 247 // to it later. | |
| 248 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 249 | |
| 250 // Allocate and zero the cache lines associated with the given range. | |
| 251 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 252 | |
| 253 //----------------------------------------------------------------------------- | |
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254 // Global control of Instruction cache |
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255 |
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256 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE |
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257 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE |
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258 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS |
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259 #define HAL_ICACHE_SETS HAL_UCACHE_SETS |
| 2 | 260 |
| 261 // Enable the instruction cache | |
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262 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE() |
| 2 | 263 |
| 264 // Disable the instruction cache | |
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265 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE() |
| 2 | 266 |
| 267 // Invalidate the entire cache | |
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268 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL() |
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269 |
| 2 | 270 |
| 271 // Synchronize the contents of the cache with memory. | |
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272 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC() |
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273 |
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274 // Query the state of the instruction cache |
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275 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_) |
| 2 | 276 |
| 277 // Set the instruction cache refill burst size | |
| 278 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 279 | |
| 280 // Load the contents of the given address range into the instruction cache | |
| 281 // and then lock the cache so that it stays there. | |
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282 |
| 2 | 283 //#define HAL_ICACHE_LOCK(_base_, _size_) |
| 284 | |
| 285 // Undo a previous lock operation | |
| 286 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 287 | |
| 288 // Unlock entire cache | |
| 289 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 290 | |
| 291 //----------------------------------------------------------------------------- | |
| 292 // Instruction cache line control | |
| 293 | |
| 294 // Invalidate cache lines in the given range without writing to memory. | |
| 295 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 296 | |
| 297 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 298 // End of hal_cache.h |
