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annotate packages/io/pci/current/tests/pci1.c @ 66:bf00f99aec69 ecos-sw-2000-02-02

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Merge from eCos master repository on 2000-02-02-19:16:44-GMT
author jlarmour
date Wed, 02 Feb 2000 19:57:02 +0000
parents c38311975d4f
children b939e9cada46
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1 //==========================================================================
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2 //
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3 // pci1.c
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4 //
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5 // Test PCI library API
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov
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35 // Contributors: jskov
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36 // Date: 1999-03-17
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37 // Description: Simple test that:
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38 // Checks API (compile time)
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39 // Prints out information about found PCI devices.
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40 // Allocates resources to devices (but does not enable
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41 // them).
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42 //####DESCRIPTIONEND####
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43
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44 #include <pkgconf/system.h>
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45
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46 #include <cyg/infra/diag.h> // diag_printf
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47 #include <cyg/infra/testcase.h> // test macros
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48 #include <cyg/infra/cyg_ass.h> // assertion macros
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49
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50 // Package requirements
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51 #if defined(CYGPKG_IO_PCI) && defined(CYGPKG_KERNEL)
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52
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53 #include <pkgconf/kernel.h>
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54 #include <pkgconf/io_pci.h>
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55 #include <cyg/io/pci.h>
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56 #include <cyg/hal/hal_arch.h>
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57
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58 // Package option requirements
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59 #if defined(CYGFUN_KERNEL_API_C) && defined(CYG_PCI_PRESENT)
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60
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61 #include <cyg/kernel/kapi.h>
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62
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63 // If the target has limited memory resources, undef the below to
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64 // avoid inclusion of the big PCI code tables.
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65 //
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66 // The header file is created from http://www.yourvote.com/pci
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67 // maintained by Jim Boemler (jboemler@halcyon.com).
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68 //
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69 // If you have PCI devices not listed in this list, please consider
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70 // registering the codes in the database.
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71 #define USE_PCI_CODE_LIST
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72
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73 #ifdef USE_PCI_CODE_LIST
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74 #include "pcihdr.h"
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75 #endif
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76
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77 // You may want to use this code to do some simple testing of the
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78 // devices on the PCI bus. By enabling the below definition, the
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79 // devices will get PCI IO and MEM access activated after configuration
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80 // so you can play with IO registers and display/set contents of MEM.
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81 #undef ENABLE_PCI_DEVICES
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82
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83 unsigned char stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
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84 cyg_thread thread_data;
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85 cyg_handle_t thread_handle;
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86
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87 cyg_bool
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88 pci_api_test(int dummy)
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89 {
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90 cyg_pci_device dev_info;
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91 cyg_pci_device_id devid = CYG_PCI_NULL_DEVID;
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92 cyg_bool ret;
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93 CYG_PCI_ADDRESS64 mem_base = 0;
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94 CYG_PCI_ADDRESS32 io_base = 0;
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95 CYG_ADDRWORD vec;
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96 cyg_uint8 var_uint8;
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97 cyg_uint16 var_uint16;
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98 cyg_uint32 var_uint32;
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99
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100
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101 // Always return...
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102 if (dummy)
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103 return true;
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104
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105 CYG_TEST_FAIL_FINISH("Not reached");
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106
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107 // PCI library API
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108 cyg_pci_init();
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109
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110 cyg_pci_get_device_info (devid, &dev_info);
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111 cyg_pci_set_device_info (devid, &dev_info);
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112
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113 ret = cyg_pci_find_device(0, 0, &devid);
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114 ret |= cyg_pci_find_class(0, &devid);
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115 ret |= cyg_pci_find_next(devid, &devid);
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116
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117 ret |= cyg_pci_configure_device(&dev_info);
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118
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119 cyg_pci_set_memory_base(mem_base);
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120 cyg_pci_set_io_base(io_base);
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121
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122 ret |= cyg_pci_allocate_memory(&dev_info, 0, &mem_base);
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123 ret |= cyg_pci_allocate_io(&dev_info, 0, &io_base);
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124
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125 ret |= cyg_pci_translate_interrupt(&dev_info, &vec);
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126
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127 cyg_pci_read_config_uint8(devid, 0, &var_uint8);
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128 cyg_pci_read_config_uint16(devid, 0, &var_uint16);
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129 cyg_pci_read_config_uint32(devid, 0, &var_uint32);
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130
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131 cyg_pci_write_config_uint8(devid, 0, var_uint8);
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132 cyg_pci_write_config_uint16(devid, 0, var_uint16);
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133 cyg_pci_write_config_uint32(devid, 0, var_uint32);
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134
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135 return ret;
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136 }
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137
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138 void
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139 pci_test( void )
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140 {
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141 cyg_pci_device dev_info;
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142 cyg_pci_device_id devid;
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143 CYG_ADDRWORD irq;
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144 int i;
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145 #ifdef USE_PCI_CODE_LIST
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146 cyg_bool no_match = false;
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147 cyg_uint16 vendor, device;
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148 cyg_uint8 bc, sc, pi;
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149 PCI_VENTABLE* vtbl;
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150 PCI_DEVTABLE* dtbl;
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151 PCI_CLASSCODETABLE* ctbl;
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152 #endif
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153
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154 pci_api_test(1);
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155
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156 cyg_pci_init();
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157
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158 if (cyg_pci_find_next(CYG_PCI_NULL_DEVID, &devid)) {
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159 do {
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160 // Get device info
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161 cyg_pci_get_device_info(devid, &dev_info);
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162
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163
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164 // Print stuff
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165 diag_printf("Found device on bus %d, devfn 0x%02x:\n",
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166 CYG_PCI_DEV_GET_BUS(devid),
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167 CYG_PCI_DEV_GET_DEVFN(devid));
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168
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169 if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
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170 diag_printf(" Note that board is active. Probed"
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171 " sizes and CPU addresses invalid!\n");
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172 }
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173
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174 // Configure the device
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175 if (cyg_pci_configure_device(&dev_info)) {
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176 diag_printf(" Device configuration succeeded\n");
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177 #ifdef ENABLE_PCI_DEVICES
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178 {
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179 cyg_uint16 cmd;
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180
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181 // Don't use cyg_pci_set_device_info since it clears
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182 // some of the fields we want to print out below.
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183 cyg_pci_read_config_uint16(dev_info.devid,
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184 CYG_PCI_CFG_COMMAND, &cmd);
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185 cmd |= CYG_PCI_CFG_COMMAND_IO|CYG_PCI_CFG_COMMAND_MEMORY;
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186 cyg_pci_write_config_uint16(dev_info.devid,
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187 CYG_PCI_CFG_COMMAND, cmd);
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188 }
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189 diag_printf(" **** Device IO and MEM access enabled\n");
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190 #endif
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191 } else {
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192 diag_printf(" Device configuration failed");
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193 if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE)
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194 diag_printf(" - device already enabled\n");
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195 else
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196 diag_printf(" - resource problem\n");
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197 }
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198
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199 diag_printf(" Vendor 0x%04x", dev_info.vendor);
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200 #ifdef USE_PCI_CODE_LIST
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201 vendor = dev_info.vendor;
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202 vtbl = PciVenTable;
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203 for (i = 0; i < PCI_VENTABLE_LEN; i++, vtbl++)
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204 if (vendor == vtbl->VenId)
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205 break;
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206
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207 if (i < PCI_VENTABLE_LEN) {
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208 diag_printf(" [%s][%s]", vtbl->VenShort, vtbl->VenFull);
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209 } else {
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210 diag_printf(" [UNKNOWN]");
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211 no_match = true;
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212 }
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213 #endif
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214 diag_printf("\n Device 0x%04x", dev_info.device);
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215 #ifdef USE_PCI_CODE_LIST
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216 device = dev_info.device;
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217 dtbl = PciDevTable;
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218 for (i = 0; i < PCI_DEVTABLE_LEN; i++, dtbl++)
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219 if (vendor == dtbl->VenId && device == dtbl->DevId)
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220 break;
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221
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222 if (i < PCI_DEVTABLE_LEN) {
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223 diag_printf(" [%s][%s]", dtbl->Chip, dtbl->ChipDesc);
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224 } else {
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225 diag_printf(" [UNKNOWN]");
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226 no_match = true;
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227 }
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228 #endif
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229
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230 diag_printf("\n Command 0x%04x, Status 0x%04x\n",
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231 dev_info.command, dev_info.status);
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232
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233 diag_printf(" Class/Rev 0x%08x", dev_info.class_rev);
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234 #ifdef USE_PCI_CODE_LIST
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235 bc = (dev_info.class_rev >> 24) & 0xff;
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236 sc = (dev_info.class_rev >> 16) & 0xff;
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237 pi = (dev_info.class_rev >> 8) & 0xff;
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238 ctbl = PciClassCodeTable;
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239 for (i = 0; i < PCI_CLASSCODETABLE_LEN; i++, ctbl++)
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240 if (bc == ctbl->BaseClass
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241 && sc == ctbl->SubClass
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242 && pi == ctbl->ProgIf)
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243 break;
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244
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245 if (i < PCI_CLASSCODETABLE_LEN) {
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246 diag_printf(" [%s][%s][%s]", ctbl->BaseDesc,
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247 ctbl->SubDesc, ctbl->ProgDesc);
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248 } else {
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249 diag_printf(" [UNKNOWN]");
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250 no_match = true;
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251 }
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252 #endif
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253 diag_printf("\n Header 0x%02x\n", dev_info.header_type);
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254
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255 diag_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
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256 dev_info.header.normal.sub_vendor,
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257 dev_info.header.normal.sub_id);
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258
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259
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260 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
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261 diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
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262 diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
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263 dev_info.base_size[i], dev_info.base_map[i]);
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264 }
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265
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266 if (cyg_pci_translate_interrupt(&dev_info, &irq))
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267 diag_printf(" Wired to HAL vector %d\n", irq);
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268 else
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269 diag_printf(" Does not generate interrupts.\n");
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270
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271 } while (cyg_pci_find_next(devid, &devid));
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272
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273
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274 #ifdef USE_PCI_CODE_LIST
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275 diag_printf("\nStrings in [] are from the PCI Code List at http://www.yourvote.com/pci\n");
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276 if (no_match) {
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277 diag_printf("It seems that some of the device information has not been registered in\n");
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278 diag_printf("the PCI Code List. Please consider improving the database by registering\n");
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279 diag_printf("the [UNKNOWN] information for your devices. Thanks.\n");
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280 }
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281 #endif
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282 } else {
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283 diag_printf("No PCI devices found.");
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284 }
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285
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286 CYG_TEST_PASS_FINISH("pci1 test OK");
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287 }
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288
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289 void
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290 cyg_start(void)
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291 {
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292 CYG_TEST_INIT();
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293 cyg_thread_create(10, // Priority - just a number
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294 (cyg_thread_entry_t*)pci_test, // entry
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295 0, //
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296 "pci_thread", // Name
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297 &stack[0], // Stack
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298 CYGNUM_HAL_STACK_SIZE_TYPICAL, // Size
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299 &thread_handle, // Handle
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300 &thread_data // Thread data structure
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301 );
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302 cyg_thread_resume(thread_handle);
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303 cyg_scheduler_start();
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304 }
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305
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306 #else // CYGFUN_KERNEL_API_C && CYG_PCI_PRESENT
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307 #define N_A_MSG "Needs kernel C API & PCI platform support"
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308 #endif
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309
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310 #else // CYGPKG_IO_PCI && CYGPKG_KERNEL
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311 #define N_A_MSG "Needs IO/PCI and Kernel"
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312 #endif
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313
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314 #ifdef N_A_MSG
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315 void
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316 cyg_start( void )
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317 {
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318 CYG_TEST_INIT();
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319 CYG_TEST_NA( N_A_MSG);
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320 }
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321 #endif // N_A_MSG
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322
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323 // EOF pci1.c