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annotate packages/kernel/current/tests/intr0.cxx @ 66:bf00f99aec69 ecos-sw-2000-02-02
Merge from eCos master repository on 2000-02-02-19:16:44-GMT
| author | jlarmour |
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| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | 6512add4f5d6 |
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| 0 | 1 //================================================================= |
| 2 // | |
| 3 // intr0.cxx | |
| 4 // | |
| 5 // Interrupt test 0 | |
| 6 // | |
| 7 //================================================================= | |
| 8 //####COPYRIGHTBEGIN#### | |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.1 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.redhat.com/ |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 0 | 30 //####COPYRIGHTEND#### |
| 31 //================================================================= | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 34 // Author(s): dsm | |
| 2 | 35 // Contributors: dsm, jlarmour |
| 36 // Date: 1999-02-16 | |
| 0 | 37 // Description: Very basic test of interrupt objects |
| 38 // Options: | |
| 39 // CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 40 // CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE | |
| 41 // CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 42 //####DESCRIPTIONEND#### | |
| 43 | |
| 44 #include <pkgconf/kernel.h> | |
| 45 | |
| 46 #include <cyg/kernel/intr.hxx> | |
| 47 #include <cyg/hal/hal_intr.h> | |
| 48 | |
| 49 #include <cyg/infra/testcase.h> | |
| 50 | |
| 51 #include "testaux.hxx" | |
| 52 | |
| 53 static cyg_ISR isr0, isr1; | |
| 54 static cyg_DSR dsr0, dsr1; | |
| 55 | |
| 2 | 56 static char intr0_obj[sizeof(Cyg_Interrupt)]; |
| 57 static char intr1_obj[sizeof(Cyg_Interrupt)]; | |
| 58 | |
| 0 | 59 static cyg_uint32 isr0(cyg_vector vector, CYG_ADDRWORD data) |
| 60 { | |
| 61 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 62 | |
| 63 Cyg_Interrupt::acknowledge_interrupt(vector); | |
| 64 return 0; | |
| 65 } | |
| 66 | |
| 67 static void dsr0(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data) | |
| 68 { | |
| 69 CYG_UNUSED_PARAM(cyg_vector, vector); | |
| 70 CYG_UNUSED_PARAM(cyg_ucount32, count); | |
| 71 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 72 } | |
| 73 | |
| 74 static cyg_uint32 isr1(cyg_vector vector, CYG_ADDRWORD data) | |
| 75 { | |
| 76 CYG_UNUSED_PARAM(cyg_vector, vector); | |
| 77 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 78 return 0; | |
| 79 } | |
| 80 | |
| 81 static void dsr1(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data) | |
| 82 { | |
| 83 CYG_UNUSED_PARAM(cyg_vector, vector); | |
| 84 CYG_UNUSED_PARAM(cyg_ucount32, count); | |
| 85 CYG_UNUSED_PARAM(CYG_ADDRWORD, data); | |
| 86 } | |
| 87 | |
| 88 static bool flash( void ) | |
| 89 { | |
| 90 Cyg_Interrupt intr0 = Cyg_Interrupt( 0, 0, (CYG_ADDRWORD)333, isr0, dsr0 ); | |
| 91 | |
| 92 return true; | |
| 93 } | |
| 94 | |
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95 /* IMPORTANT: The calling convention for VSRs is target dependent. It is |
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96 * unlikely that a plain C or C++ routine would function correctly on any |
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97 * particular platform, even if it could correctly access the system |
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98 * resources necessary to handle the event that caused it to be called. |
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99 * VSRs usually must be written in assembly language. |
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100 * |
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101 * This is just a test program. The routine vsr0() below is defined simply |
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102 * to define an address that will be in executable memory. If an event |
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103 * causes this VSR to be called, all bets are off. If it is accidentally |
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104 * installed in the vector for the realtime clock, the system will likely |
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105 * freeze. |
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106 */ |
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107 |
| 0 | 108 static cyg_VSR vsr0; |
| 109 | |
| 110 static void vsr0() | |
| 111 { | |
| 112 } | |
| 113 | |
| 114 void intr0_main( void ) | |
| 115 { | |
| 116 CYG_TEST_INIT(); | |
| 117 | |
| 118 CHECK(flash()); | |
| 119 CHECK(flash()); | |
| 120 | |
| 2 | 121 // Make sure the chosen levels are not already in use. |
| 122 int in_use; | |
| 123 cyg_vector lvl1 = 1 % (CYGNUM_HAL_ISR_COUNT); | |
| 124 HAL_INTERRUPT_IN_USE( lvl1, in_use ); | |
| 125 Cyg_Interrupt* intr0 = NULL; | |
| 126 if (!in_use) | |
| 127 intr0 = new((void *)&intr0_obj[0]) Cyg_Interrupt( lvl1, 1, (CYG_ADDRWORD)777, isr0, dsr0 ); | |
| 128 | |
| 129 cyg_vector lvl2 = 15 % (CYGNUM_HAL_ISR_COUNT); | |
| 130 HAL_INTERRUPT_IN_USE( lvl2, in_use ); | |
| 131 Cyg_Interrupt* intr1 = NULL; | |
| 132 if (!in_use && lvl1 != lvl2) | |
| 133 intr1 = new((void *)&intr1_obj[0]) Cyg_Interrupt( lvl2, 1, 888, isr1, dsr1 ); | |
| 0 | 134 |
| 135 // Check these functions at least exist | |
| 136 Cyg_Interrupt::enable_interrupts(); | |
| 137 Cyg_Interrupt::disable_interrupts(); | |
| 138 | |
| 2 | 139 if (intr0) |
| 140 intr0->attach(); | |
| 141 if (intr1) | |
| 142 intr1->attach(); | |
| 143 if (intr0) | |
| 144 intr0->detach(); | |
| 145 if (intr1) | |
| 146 intr1->detach(); | |
| 0 | 147 |
| 148 // If this attaching interrupt replaces the previous interrupt | |
| 149 // instead of adding to it we could be in a big mess if the | |
| 150 // vector is being used by something important. | |
| 2 | 151 |
| 152 cyg_vector v = 11 % CYGNUM_HAL_VSR_COUNT; | |
| 0 | 153 cyg_VSR *old_vsr, *new_vsr; |
| 154 Cyg_Interrupt::set_vsr( v, vsr0, &old_vsr ); | |
| 155 Cyg_Interrupt::get_vsr( v, &new_vsr ); | |
| 156 CHECK( vsr0 == new_vsr ); | |
| 157 | |
| 158 new_vsr = NULL; | |
| 159 Cyg_Interrupt::set_vsr( v, old_vsr, &new_vsr ); | |
| 160 CHECK( new_vsr == vsr0 ); | |
| 161 | |
| 162 Cyg_Interrupt::set_vsr( v, new_vsr ); | |
| 163 new_vsr = NULL; | |
| 2 | 164 Cyg_Interrupt::get_vsr( v, &new_vsr ); |
| 0 | 165 CHECK( vsr0 == new_vsr ); |
| 166 | |
| 167 Cyg_Interrupt::set_vsr( v, old_vsr ); | |
| 168 CHECK( vsr0 == new_vsr ); | |
| 169 new_vsr = NULL; | |
| 170 Cyg_Interrupt::get_vsr( v, &new_vsr ); | |
| 171 CHECK( old_vsr == new_vsr ); | |
| 2 | 172 |
| 0 | 173 CHECK( NULL != vsr0 ); |
| 174 | |
| 2 | 175 cyg_vector v1; |
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176 #ifdef CYGPKG_HAL_MIPS_TX39 |
| 2 | 177 // This can be removed when PR 17831 is fixed |
| 178 if ( cyg_test_is_simulator ) | |
| 179 v1 = 12 % CYGNUM_HAL_ISR_COUNT; | |
| 180 else /* NOTE TRAILING ELSE... */ | |
| 181 #endif | |
| 182 v1 = 6 % CYGNUM_HAL_ISR_COUNT; | |
| 183 | |
| 0 | 184 Cyg_Interrupt::mask_interrupt(v1); |
| 185 Cyg_Interrupt::unmask_interrupt(v1); | |
| 186 | |
| 187 Cyg_Interrupt::configure_interrupt(v1, true, true); | |
| 188 | |
| 189 CYG_TEST_PASS_FINISH("Intr 0 OK"); | |
| 190 } | |
| 191 | |
| 192 externC void | |
| 193 cyg_start( void ) | |
| 194 { | |
| 195 intr0_main(); | |
| 196 } | |
| 197 // EOF intr0.cxx |