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annotate packages/hal/sh/arch/current/include/hal_arch.h @ 101:c37d3a9e1b28 ecos-sw-2000-06-16

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Merge from eCos master repository on 2000-06-16-07:47:03-BST
author jlarmour
date Fri, 16 Jun 2000 16:43:59 +0000
parents 435cced73e2f
children eb9fd8c04db3
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1 #ifndef CYGONCE_HAL_ARCH_H
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2 #define CYGONCE_HAL_ARCH_H
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3
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4 //=============================================================================
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5 //
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6 // hal_arch.h
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7 //
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8 // Architecture specific abstractions
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): jskov
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38 // Contributors:jskov
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39 // Date: 1999-04-24
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40 // Purpose: Define architecture abstractions
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41 // Usage: #include <cyg/hal/hal_arch.h>
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42
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43 //
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44 //####DESCRIPTIONEND####
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45 //
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46 //=============================================================================
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47
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48 #include <pkgconf/hal.h>
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49 #include <cyg/infra/cyg_type.h>
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50
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51 //-----------------------------------------------------------------------------
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52 // Processor saved states:
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53 // The layout of this structure is also defined in "sh.inc", for assembly
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54 // code. Do not change this without changing that (or vice versa).
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55
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56 typedef struct
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57 {
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58 // These are common to all saved states
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59 cyg_uint32 r[16]; // Data regs
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60 cyg_uint32 mach; // Multiply and accumulate - high
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61 cyg_uint32 macl; // Multiply and accumulate - low
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62 cyg_uint32 pr; // Procedure Reg
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63 cyg_uint32 sr; // Status Reg
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64 cyg_uint32 pc; // Program Counter
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65
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66 // This marks the limit of state saved during a context switch and
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67 // is used to calculate necessary stack allocation for context switches.
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68 // It would probably be better to have a union instead...
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69 cyg_uint32 context_size[0];
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70
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71 // These are only saved on interrupts
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72 cyg_uint32 vbr; // Vector Base Register
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73 cyg_uint32 gbr; // Global Base Register
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74
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75 // These are only saved on interrupts
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76 cyg_uint32 event; // EXPEVT or INTEVT
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77 } HAL_SavedRegisters;
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78
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79 //-----------------------------------------------------------------------------
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80 // Exception handling function.
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81 // This function is defined by the kernel according to this prototype. It is
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82 // invoked from the HAL to deal with any CPU exceptions that the HAL does
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83 // not want to deal with itself. It usually invokes the kernel's exception
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84 // delivery mechanism.
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85
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86 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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87
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88 //--------------------------------------------------------------------------
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89 // Bit manipulation routines
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90
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91 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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92 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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93
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94 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
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95
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96 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
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97
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98 //-----------------------------------------------------------------------------
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99 // Context Initialization
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100 // Initialize the context of a thread.
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101 // Arguments:
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102 // _sparg_ name of variable containing current sp, will be written with new sp
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103 // _thread_ thread object address, passed as argument to entry point
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104 // _entry_ entry point address.
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105 // _id_ bit pattern used in initializing registers, for debugging.
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106
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107 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
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108 CYG_MACRO_START \
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109 register HAL_SavedRegisters *_regs_; \
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110 int _i_; \
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111 _regs_ = (HAL_SavedRegisters *)((_sparg_) - sizeof(HAL_SavedRegisters)); \
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112 for( _i_ = 0; _i_ < 16; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \
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113 (_regs_)->r[15] = (CYG_WORD)(_regs_); /* SP = top of stack */ \
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114 (_regs_)->r[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \
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115 (_regs_)->mach = 0; /* MACH = 0 */ \
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116 (_regs_)->macl = 0; /* MACL = 0 */ \
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117 (_regs_)->pr = (CYG_WORD)(_entry_); /* PR = entry point */ \
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118 (_regs_)->sr = 0; /* SR = enable interrupts */ \
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119 (_regs_)->pc = (CYG_WORD)(_entry_); /* set PC for thread dbg */ \
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120 _sparg_ = (CYG_ADDRESS)_regs_; \
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121 CYG_MACRO_END
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122
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123 //-----------------------------------------------------------------------------
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124 // Context switch macros.
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125 // The arguments are pointers to locations where the stack pointer
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126 // of the current thread is to be stored, and from where the sp of the
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127 // next thread is to be fetched.
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128
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129 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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130 externC void hal_thread_load_context( CYG_ADDRESS to )
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131 __attribute__ ((noreturn));
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132
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133 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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134 hal_thread_switch_context((CYG_ADDRESS)_tspptr_,(CYG_ADDRESS)_fspptr_);
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135
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136 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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137 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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138
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139 //-----------------------------------------------------------------------------
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140 // Execution reorder barrier.
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141 // When optimizing the compiler can reorder code. In multithreaded systems
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142 // where the order of actions is vital, this can sometimes cause problems.
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143 // This macro may be inserted into places where reordering should not happen.
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144
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145 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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146
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147 //-----------------------------------------------------------------------------
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148 // Breakpoint support
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149 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
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150 // if executed.
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151 // HAL_BREAKINST is the value of the breakpoint instruction and
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152 // HAL_BREAKINST_SIZE is its size in bytes.
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153
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154 // Enable interrupts before doing the trap, or the CPU will reset.
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155 #define HAL_BREAKPOINT(_label_) \
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156 CYG_MACRO_START \
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157 HAL_ENABLE_INTERRUPTS(); \
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158 asm volatile (" .globl _" #_label_ ";_" \
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159 #_label_":" \
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160 " trapa #0xc3;nop;nop;nop"); \
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161 CYG_MACRO_END
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162
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163 #define HAL_BREAKINST 0xc3c3
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164
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165 #define HAL_BREAKINST_SIZE 2
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166
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167 //-----------------------------------------------------------------------------
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168 // Thread register state manipulation for GDB support.
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169
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170 // Translate a stack pointer as saved by the thread context macros above into
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171 // a pointer to a HAL_SavedRegisters structure.
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172 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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173 (_regs_) = (HAL_SavedRegisters *)(_sp_)
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174
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175 // Copy a set of registers from a HAL_SavedRegisters structure into a
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176 // GDB ordered array.
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177 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
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178 CYG_MACRO_START \
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179 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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180 int _i_; \
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181 \
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182 for( _i_ = 0; _i_ < 16; _i_++ ) \
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183 _regval_[_i_] = (_regs_)->r[_i_]; \
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184 \
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185 _regval_[16] = (_regs_)->pc; \
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186 _regval_[17] = (_regs_)->pr; \
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187 _regval_[18] = (_regs_)->gbr; \
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188 _regval_[19] = (_regs_)->vbr; \
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189 _regval_[20] = (_regs_)->mach; \
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190 _regval_[21] = (_regs_)->macl; \
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191 _regval_[22] = (_regs_)->sr; \
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192 \
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193 /* 23-51 not used atm. */ \
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194 CYG_MACRO_END
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195
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196 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
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197 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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198 CYG_MACRO_START \
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199 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
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200 int _i_; \
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201 \
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202 for( _i_ = 0; _i_ < 16; _i_++ ) \
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203 (_regs_)->r[_i_] = _regval_[_i_]; \
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204 \
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205 (_regs_)->pc = _regval_[16]; \
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206 (_regs_)->pr = _regval_[17]; \
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207 (_regs_)->gbr = _regval_[18]; \
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208 (_regs_)->vbr = _regval_[19]; \
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209 (_regs_)->mach = _regval_[20]; \
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210 (_regs_)->macl = _regval_[21]; \
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211 (_regs_)->sr = _regval_[22]; \
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212 CYG_MACRO_END
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213
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214 //-----------------------------------------------------------------------------
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215 // HAL setjmp
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216
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217 typedef struct {
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218 cyg_uint32 sp;
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219 cyg_uint32 pr;
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220 cyg_uint32 r8;
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221 cyg_uint32 r9;
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222 cyg_uint32 r10;
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223 cyg_uint32 r11;
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224 cyg_uint32 r12;
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225 cyg_uint32 r13;
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226 cyg_uint32 r14;
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227 } hal_jmp_buf_t;
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228
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229 typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)];
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230
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231 externC int hal_setjmp(hal_jmp_buf env);
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232 externC void hal_longjmp(hal_jmp_buf env, int val);
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233
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234 //-----------------------------------------------------------------------------
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235 // Idle thread code.
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236 // This macro is called in the idle thread loop, and gives the HAL the
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237 // chance to insert code. Typical idle thread behaviour might be to halt the
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238 // processor.
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239
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240 externC void hal_idle_thread_action(cyg_uint32 loop_count);
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241
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242 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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243
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244 //-----------------------------------------------------------------------------
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245 // Minimal and sensible stack sizes: the intention is that applications
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246 // will use these to provide a stack size in the first instance prior to
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247 // proper analysis. Idle thread stack should be this big.
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248
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249 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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250 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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251 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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252
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253 // This is not a config option because it should not be adjusted except
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254 // under "enough rope" sort of disclaimers.
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255
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256 // Stack frame overhead per call. Space to save FP, PR and 8 registers.
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257 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 10)
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258
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259 // Stack needed for a context switch (shreg_context_size from sh.inc)
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260 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 21)
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261
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262 // Interrupt + call to ISR, interrupt_end() and the DSR
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263 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
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264 ((24*4 /* sizeof(HAL_SavedRegisters) */) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
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265
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266 // We define a minimum stack size as the minimum any thread could ever
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267 // legitimately get away with. We can throw asserts if users ask for less
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268 // than this. Allow enough for three interrupt sources - clock, serial and
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269 // one other
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270
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271 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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272
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273 // An interrupt stack which is large enough for all possible interrupt
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274 // conditions (and only used for that purpose) exists. "User" stacks
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275 // can therefore be much smaller
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276
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277 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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278 (16*CYGNUM_HAL_STACK_FRAME_SIZE + 2*CYGNUM_HAL_STACK_INTERRUPT_SIZE)
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279
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280 #else
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281
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282 // No separate interrupt stack exists. Make sure all threads contain
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283 // a stack sufficiently large
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284 # define CYGNUM_HAL_STACK_SIZE_MINIMUM \
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285 (((2+3)*CYGNUM_HAL_STACK_INTERRUPT_SIZE) + \
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286 (16*CYGNUM_HAL_STACK_FRAME_SIZE))
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287 #endif
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288
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289 // Now make a reasonable choice for a typical thread size. Pluck figures
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290 // from thin air and say 30 call frames with an average of 16 words of
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291 // automatic variables per call frame
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292 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \
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293 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \
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294 30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4)))
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295
101
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296 //--------------------------------------------------------------------------
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297 // Macros for switching context between two eCos instances (jump from
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298 // code in ROM to code in RAM or vice versa).
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299 #define CYGARC_HAL_SAVE_GP()
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300 #define CYGARC_HAL_RESTORE_GP()
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301
76
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302 //-----------------------------------------------------------------------------
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303 #endif // CYGONCE_HAL_ARCH_H
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304 // End of hal_arch.h