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annotate packages/hal/mips/tx39/current/include/variant.inc @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents a0774359f013
children bf00f99aec69
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1 #ifndef CYGONCE_HAL_VARIANT_INC
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2 #define CYGONCE_HAL_VARIANT_INC
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3 ##=============================================================================
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4 ##
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5 ## variant.inc
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6 ##
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7 ## TX39 family assembler header file
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8 ##
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9 ##=============================================================================
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10 #####COPYRIGHTBEGIN####
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11 #
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12 # -------------------------------------------
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13 # The contents of this file are subject to the Red Hat eCos Public License
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14 # Version 1.0 (the "License"); you may not use this file except in
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15 # compliance with the License. You may obtain a copy of the License at
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16 # http://sourceware.cygnus.com/ecos
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17 #
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18 # Software distributed under the License is distributed on an
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19 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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20 # License for the specific language governing rights and limitations under
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21 # the License.
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22 #
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23 # The Original Code is eCos - Embedded Configurable Operating System,
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24 # released September 30, 1998.
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25 #
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26 # The Initial Developer of the Original Code is Red Hat.
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27 # Portions created by Red Hat are
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28 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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29 # All Rights Reserved.
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30 # -------------------------------------------
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31 #
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32 #####COPYRIGHTEND####
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33 ##=============================================================================
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34 #######DESCRIPTIONBEGIN####
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35 ##
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36 ## Author(s): nickg
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37 ## Contributors: nickg
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38 ## Date: 1999-04-06
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39 ## Purpose: TX39 family definitions.
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40 ## Description: This file contains various definitions and macros that are
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41 ## useful for writing assembly code for the TX39 CPU family.
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42 ## Usage:
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43 ## #include <cyg/hal/variant.inc>
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44 ## ...
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45 ##
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46 ##
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47 ######DESCRIPTIONEND####
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48 ##
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49 ##=============================================================================
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50
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51 #include <pkgconf/hal.h>
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52
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53 #include <cyg/hal/mips.inc>
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54
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55 #include <cyg/hal/platform.inc>
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56
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57 ##-----------------------------------------------------------------------------
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58 ## Define CPU variant for architecture HAL.
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59
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60 #define CYG_HAL_MIPS_R3000A
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61 #define CYG_HAL_MIPS_R3900
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62
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63 ##-----------------------------------------------------------------------------
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64 ## Indicate that the ISR tables are defined in variant.S
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65
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66 #define CYG_HAL_MIPS_ISR_TABLES_DEFINED
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67
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68 ##-----------------------------------------------------------------------------
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69 ## TX39 Memory controller.
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70
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71 #ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
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72
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73 ## ROM timing characteristics are dependent on the clock speed.
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74
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75 #if (CYGHWR_HAL_MIPS_CPU_FREQ == 50)
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76 #define ROM_CCR0_INIT 0x00000420
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77 #define DRAM_DREFC_INIT 0x00000180
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78 #define DRAM_DWR0_INIT 0x00111111
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79 #elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66)
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80 #define ROM_CCR0_INIT 0x00000520
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81 #define DRAM_DREFC_INIT 0x00000200
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82 #define DRAM_DWR0_INIT 0x00332222
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83 #else
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84 #error Unsupported clock frequency
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85 #endif
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86
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87 ## DRAM configuration is dependent on the DRAM device used.
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88 ## for 16MByte (4MBit (x4bit) x 8) 0x08024030
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89 ## for 4MByte (1MBit (x4bit) x 8) 0x08013020
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90 ## for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020
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91
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92 #if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
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93 #define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
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94 #else
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95 #define DRAM_CONFIG_INIT 0x08024030
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96 #endif
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97
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98 ## Enabling timeout exceptions can result in bogus exceptions under the
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99 ## following conditions:
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100 ## o half speed bus mode (JMR board uses this mode)
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101 ## o code resides on 0 wait SRAM
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102 ## o I- and D- caches are enabled
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103 ## o a very narrow timing condition of cache refill cycle (not
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104 ## descibed here)
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105 ## The simple solution is to configure 1 cycle wait state SRAM rather
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106 ## than zero.
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107
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108 #ifdef CYGHWR_HAL_MIPS_TX39_JMR3904_ENABLE_TOE
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109 #define SRAM_WAIT_INIT 0x00000100
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110 #else
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111 #define SRAM_WAIT_INIT 0x00000000
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112 #endif
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113
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114 .macro hal_memc_init
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115
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116 # These mappings need to be set up before we
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117 # can use the stack and make calls to other
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118 # functions
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119
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120 # If we have been started from Cygmon, it should have
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121 # already done a lot of this, but it should do no harm
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122 # to reinitialize the following registers.
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123
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124 # SCS0,1 base addr of ISA & PCI
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125 la v0,0xffffe010
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126 la v1,0x20201410
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127 sw v1,0(v0)
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128
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129 la v0,0xffffe014
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130 la v1,0xfffffcfc
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131 sw v1,0(v0)
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132
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133 # ROM configuration
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134 .set at
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135 la v0,0xffff9000
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136 lw v1,0(v0)
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137 and v1,v1,0xffff0004 # keep hardware defaults
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138 or v1,ROM_CCR0_INIT # install our values
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139 sw v1,0(v0)
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140 .set noat
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141
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142 # SRAM config
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143 la v0,0xffff9100
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144 la v1,SRAM_WAIT_INIT
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145 sw v1,0(v0)
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146
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147 # ISA bus setup
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148 la v0,0xb2100000
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149 la v1,4
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150 sb v1,0(v0)
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151
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152 # Clear IMR (to cope with JMON)
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153 la v0,0xffffc004
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154 la v1,0x00000000
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155 sw v1,0(v0)
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156
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157 hal_memc_init_dram
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158
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159 .endm
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160
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161
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162 .macro hal_memc_init_dram
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163 # DRAM Configuration
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164 la v0, 0xffff8000
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165 la v1, DRAM_CONFIG_INIT
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166 sw v1, 0(v0)
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167
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168 # DBMR0
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169 la v0, 0xffff8004
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170 la v1, 0x00000000
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171 sw v1, 0(v0)
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172
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173 # DWR0
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174 la v0, 0xffff8008
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175 la v1, DRAM_DWR0_INIT
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176 sw v1, 0(v0)
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177
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178 # DREFC - Depends on clock requency
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179 la v0, 0xffff8800
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180 la v1, DRAM_DREFC_INIT
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181 sw v1, 0(v0)
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182 .endm
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183
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184 #define CYGPKG_HAL_MIPS_MEMC_DEFINED
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185
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186 #endif
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187
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188 ##-----------------------------------------------------------------------------
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189 ## TX39 interrupt handling.
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190
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191 #ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
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192
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193 #ifdef CYGPKG_HAL_MIPS_TX3904
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194
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195 # Set all ILRX registers to 0, masking all external interrupts.
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196 .macro hal_intc_init
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197
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198 #ifndef CYG_HAL_STARTUP_RAM
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199 la v0,0xFFFFC010
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200 move v1,zero
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201 sw v1,0(v0)
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202 sw v1,4(v0)
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203 sw v1,8(v0)
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204 sw v1,12(v0)
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205 #endif
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206 .endm
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207
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208 .macro hal_intc_decode vnum
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209 mfc0 v1,cause # get cause register
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210 nop
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211 srl v1,v1,10 # shift IP bits to ls bits
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212 andi v1,v1,0x7F # isolate IP bits
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213 la v0,hal_intc_translation_table # address of translation table
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214 add v0,v0,v1 # offset of index byte
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215 lb \vnum,0(v0) # load it
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216 .endm
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217
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218 #ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
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219 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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220 .macro hal_intc_translate inum,vnum
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221 move \vnum,zero # Just vector zero is supported
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222 .endm
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223 #else
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224 .macro hal_intc_translate inum,vnum
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225 move \vnum,\inum # Vector == interrupt number
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226 .endm
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227 #endif
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228 #endif
6
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229
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230 # This table translates from the 6 bit value supplied in the IP bits
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231 # of the cause register into a 0..16 offset into the ISR tables.
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232 .macro hal_intc_decode_data
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233 hal_intc_translation_table:
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234 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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235 .byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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236 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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237 .byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
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238 .endm
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239
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240 #define CYGPKG_HAL_MIPS_INTC_DEFINED
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241
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242 #else
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243
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244 #error Unknown TX39 variant
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245
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246 #endif
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247
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248 #endif
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249
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250 #------------------------------------------------------------------------------
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251 # Diagnostics macros.
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252
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253 #if 0
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254 #ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
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255
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256 # Set up PIO0 for debugging output
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257 .macro hal_diag_init
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258 la v0,0xfffff500
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259 la v1,0xff
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260 sb v1,0(v0)
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261 la v1,0
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262 sb v1,4(v0)
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263 .endm
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264
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265 #define CYGPKG_HAL_MIPS_DIAG_DEFINED
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266
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267 #endif
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268 #endif
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269
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270 #------------------------------------------------------------------------------
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271 #endif // ifndef CYGONCE_HAL_VARIANT_INC
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272 # end of variant.inc