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annotate packages/hal/mn10300/arch/current/src/vectors.S @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 641b639be825
children bf00f99aec69
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1 ##=============================================================================
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2 ##
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3 ## vectors.S
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4 ##
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5 ## MN10300 exception vectors
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6 ##
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7 ##=============================================================================
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8 #####COPYRIGHTBEGIN####
64
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9 #
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10 # -------------------------------------------
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11 # The contents of this file are subject to the Red Hat eCos Public License
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12 # Version 1.0 (the "License"); you may not use this file except in
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13 # compliance with the License. You may obtain a copy of the License at
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14 # http://sourceware.cygnus.com/ecos
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15 #
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16 # Software distributed under the License is distributed on an
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17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 # License for the specific language governing rights and limitations under
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19 # the License.
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20 #
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21 # The Original Code is eCos - Embedded Configurable Operating System,
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22 # released September 30, 1998.
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23 #
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24 # The Initial Developer of the Original Code is Red Hat.
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25 # Portions created by Red Hat are
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26 # Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 # All Rights Reserved.
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28 # -------------------------------------------
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29 #
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30 #####COPYRIGHTEND####
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31 ##=============================================================================
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32 #######DESCRIPTIONBEGIN####
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33 ##
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34 ## Author(s): nickg
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35 ## Contributors: nickg
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36 ## Date: 1997-10-16
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37 ## Purpose: MN10300 exception vectors
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38 ## Description: This file defines the code placed into the exception
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39 ## vectors. It also contains the first level default VSRs
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40 ## that save and restore state for both exceptions and
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41 ## interrupts.
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42 ##
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43 ######DESCRIPTIONEND####
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44 ##
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45 ##=============================================================================
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46
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47 #include <pkgconf/hal.h>
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48
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49 #ifdef CYGPKG_KERNEL
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50
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51 #include <pkgconf/kernel.h>
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52
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53 #endif
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54
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55 #include <cyg/hal/arch.inc>
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56
0
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57
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58 ##-----------------------------------------------------------------------------
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59
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60 .file "vectors.S"
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61
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62 ##-----------------------------------------------------------------------------
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63
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64 .section ".vectors","ax"
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65
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66 .globl reset_vector
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67
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68 reset_vector:
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69 # Reset vector
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70 jmp _start
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71
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72 .p2align 3
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73
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74 # NMI vector
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75 jmp __nmi
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76
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77 .p2align 3
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78
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79 # Trap vector
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80 jmp __trap
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81
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82 ##-----------------------------------------------------------------------------
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83 ## NMI vector
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84
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85 .globl __nmi
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86 __nmi:
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87 add -4,sp # space for SP
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88 hal_cpu_save_all # push all registers
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89 mov (_hal_vsr_table+28),a0
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90 jmp (a0)
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91
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92 ##-----------------------------------------------------------------------------
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93 ## Trap vector
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94
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95 .globl __trap
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96 __trap:
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97 add -8,sp # space for SP and PSW
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98 hal_cpu_save_all # push all registers
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99 mov (_hal_vsr_table+32),a0
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100 jmp (a0)
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101
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102 ##-----------------------------------------------------------------------------
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103 ## Macro to define a hardware VSR
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104
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105 .macro hardware_vector name
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106 .globl __hardware_vector_\name
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107 __hardware_vector_\name:
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108 add -4,sp # space for SP
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109 hal_cpu_save_all
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110 mov \name,d0 # d0 = vector id
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111 mov d0,(0,sp) # save in dummy stack loc
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112 mov _hal_vsr_table,a0 # a0 = vsr table
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113 add \name<<2,a0 # a0 = &required vsr
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114 mov (a0),a0 # a0 = required vsr
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115 jmp (a0) # go there
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116 .endm
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117
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118 ##-----------------------------------------------------------------------------
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119 ## Hardware Vectors. These are pointed to by the registers in
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120 ## mn10300_interrupt_vectors and must be in the range 0x4000XXXX.
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121
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122 hardware_vector 0
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123 hardware_vector 1
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124 hardware_vector 2
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125 hardware_vector 3
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126 hardware_vector 4
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127 hardware_vector 5
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128 hardware_vector 6
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129
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130 ##-----------------------------------------------------------------------------
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131 ## Startup code
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132
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133 .text
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134
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135 .globl _start
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136 _start:
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137
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138 # set up stack
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139
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140 mov __interrupt_stack,a0
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141 sub 8,a0
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142 mov a0,sp
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143
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144 # Initialize hardware
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145 hal_cpu_init
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146 hal_mmu_init
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147 hal_memc_init
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148 hal_diag_init
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149 hal_intc_init
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150 hal_cache_init
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151 hal_timer_init
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152 hal_mon_init
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153
0
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154 #ifdef CYG_HAL_STARTUP_ROM
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155
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156 # Copy data from ROM to RAM
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157
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158 mov __rom_data_start,a0
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159 mov __ram_data_end,a1
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160 mov __ram_data_start,a2
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161
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162 cmp a2,a1
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163 beq 8f
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164 1:
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165 movbu (a0),d0
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166 movbu d0,(a2)
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167 inc a0
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168 inc a2
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169 cmp a2,a1
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170 bne 1b
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171 8:
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172
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173 #endif
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174
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175 # Clear BSS
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176 mov __bss_start,a0
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177 mov __bss_end,a1
0
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178
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179 cmp a0,a1
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180 beq 8f
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181 clr d0
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182 1:
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183 movbu d0,(a0)
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184 inc a0
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185 cmp a0,a1
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186 bne 1b
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187 8:
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188
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189 # Call variant and platform HAL
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190 # initialization routines.
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191
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192 .extern _hal_variant_init
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193 call _hal_variant_init,[],0
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194
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195 .extern _hal_platform_init
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196 call _hal_platform_init,[],0
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197
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198 # Call constructors
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199
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200 .extern _cyg_hal_invoke_constructors
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201 call _cyg_hal_invoke_constructors,[],0
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202
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203 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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204 .extern _initialize_stub
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205 call _initialize_stub,[],0
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206 #endif
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207
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208 # Call cyg_start
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209 clr d0
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210 mov d0,(4,sp)
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211
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212 .extern _cyg_start
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213 call _cyg_start,[],0
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214
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215 9:
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216 bra 9b # Loop if we return
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217
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218 ##-----------------------------------------------------------------------------
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219 ## The following macros are defined depending on whether the HAL is configured
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220 ## to support the kernel or not.
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221
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222 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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223
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224 .extern cyg_scheduler_sched_lock
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225
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226 # Increment the scheduler lock
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227
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228 .macro increment_sched_lock reg=d0
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229 mov (cyg_scheduler_sched_lock),\reg
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230 inc \reg
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231 mov \reg,(cyg_scheduler_sched_lock)
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232 .endm
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233
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234 #else
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235
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236 .macro increment_sched_lock reg=d0
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237 .endm
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238
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239 #endif
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240
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241 ##-----------------------------------------------------------------------------
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242 ## Default interrupt VSR
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243
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244 .text
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245 .globl __default_interrupt_vsr
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246 __default_interrupt_vsr:
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247
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248 # We come here with all the registers pushed
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249 # onto the stack.
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250
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251 hal_diag_intr_start
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252
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253 increment_sched_lock
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254
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255 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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256 # Increment interrupt nesting counter
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257 mov __interrupt_stack,a0 # A0 = interrupt stack top
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258 mov sp,a2 # A2 = SP
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259 cmp __interrupt_stack_base,a2 # compare with base of stack
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260 blt 1f # if lt switch to int stack
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261 cmp a0,a2 # compare sp with stack top
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262 ble 8f # if le already on istack
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263 1:
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264 mov a0,sp # switch to new SP
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265 8:
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266 movm [a2],(sp) # save old SP
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267
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268 #else
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269 mov sp,a2 # A2 = saved thread state
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270 #endif
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271
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272 # Here A2 -> saved thread state on the threads own
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273 # stack. We will be executing either on the same stack
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274 # or on the interrupt stack, depending on config options.
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275
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276 hal_intc_decode d3,a3,d0
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277
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278 # Here D3 contains the table byte offset of the vector to
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279 # call.
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280
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281 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
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282
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283 # Call cyg_instrument to record that this interrupt is being raised.
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284
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285 .extern _cyg_instrument
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286 add -16,sp # make space for return link + args
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287 mov 0x0301,d0 # d0 = type = INTR,RAISE
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288 mov (0,a2),d1 # d1 = arg1 = vector
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289 mov d3,(12,sp) # (12,sp) = arg2 = table offset
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290 calls _cyg_instrument # call instrumentation
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291 add 16,sp # pop space
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292
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293 #endif
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294
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295 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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296 .extern _cyg_hal_gdb_isr
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297 add -16,sp # make space for return link + args
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298 mov (0,a2),d0 # d0 = vector
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299 mov (56,a2),d1 # d1 = pc
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300 calls _cyg_hal_gdb_isr # call GDB isr function
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301 cmp 0x00,d0 # Call ISR proper?
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302 beq 2f # (d0 is 0 when skipping
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303 # to avoid DSR call)
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304 add 16,sp # pop space
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305 #endif
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306
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307 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
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308
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309 # To allow nested interrupts, we set the IE bit. We do
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310 # not touch the IPL bits, so only higher priority interrupts
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311 # will be nested on top of us. Also, new interrupts will not
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312 # be delivered until the ISR calls
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313 # Cyg_Interrupt::acknowledge_interrupt(). At some future point
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314 # we may want to do the ack stuff here to allow immediate nesting.
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315
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316 or 0x0800,psw
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317
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318 #endif
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319 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
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320
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321 # If we have Ctrl-C support enabled, save a pointer to the
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322 # saved CPU state here so we can plant a breakpoint there if
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323 # this is a ^C.
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324
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325 .extern _hal_saved_interrupt_state
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326 mov a2,(_hal_saved_interrupt_state)
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327
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328 #endif
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329
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330 mov _hal_interrupt_handlers,a0 # a0 = isr table
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331 mov (d3,a0),a0 # a0 = isr
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332
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333 mov _hal_interrupt_data,a1 # a1 = data table
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334 mov (d3,a1),d1 # d1 = isr data
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335
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336 mov (0,a2),d0 # d0 = vector. (d3 is...
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337 # ...adjusted for table reads)
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338
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339 add -16,sp # make space for return link
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340
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341 calls (a0) # call isr
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342
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343 # on return d0 bit 1 will indicate whether a DSR is
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344 # to be posted. Pass this together with a pointer to
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345 # the interrupt object we have just used to the
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346 # interrupt tidy up routine.
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347
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348 # D3 is defined to be saved across procedure calls, and
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349 # should still contain the vector byte index. Similarly,
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350 # A2 should still point to the saved machine state.
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351
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352 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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353 # If interrupt was caused by GDB, the ISR call above
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354 # is skipped by jumping here.
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355 2:
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356 #endif
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357
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358 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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359
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360 # If we are returning from the last nested interrupt, move back
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361 # to the thread stack. interrupt_end() must be called on the
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362 # thread stack since it potentially causes a context switch.
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363
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364 add 16,sp # pop call frame from int stack
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365 movm (sp),[a3] # pop old sp
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366 mov a3,sp # put in SP
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367
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368 add -16,sp # make call frame for call
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369
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370 #endif
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371
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372 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
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373
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374 # We only need to call _interrupt_end() when there is a kernel
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375 # present to do any tidying up.
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376
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377 # Using the vector offset in D3, get the interrupt object pointer
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378 # into D1.
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379 mov _hal_interrupt_objects,a0 # a0 = object table
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380 mov (d3,a0),d1 # d1 = object
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381
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382 # Even when this is not the last nested interrupt, we must call
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383 # _interrupt_end() to post the DSR and decrement the scheduler
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384 # lock.
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385
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386 mov a2,(12,sp) # arg3 = saved state.
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387
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388 calls _interrupt_end # call interrupt end fn
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389 #endif
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390
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391 add 16,sp # pop return link
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392
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393 # show_interrupts
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394
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395 hal_diag_restore
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396
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397 hal_cpu_load_all
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398 add 4,sp
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399 rti # and return
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400
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401 ##-----------------------------------------------------------------------------
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402 ## Execute pending DSRs on the interrupt stack with interrupts enabled.
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403 ## Note: this can only be called from code running on a thread stack
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404
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405 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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406 .extern _cyg_interrupt_call_pending_DSRs
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407 .global _hal_interrupt_stack_call_pending_DSRs
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408
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409 _hal_interrupt_stack_call_pending_DSRs:
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410 movm [d2,a2],(sp) # save some work regs
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411 mov __interrupt_stack,a0 # interrupt stack pointer
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412 mov sp,a2 # save current SP
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413 mov a0,sp # set SP to interrupt stack
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414 hal_cpu_get_psw d2 # save PSW
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415 hal_cpu_int_enable # enable interrupts
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416
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417 # Call kernel code to invoke DSRs.
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418 calls _cyg_interrupt_call_pending_DSRs
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419
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420 # On return the old SP in a2 and the old PSW in d2 will
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421 # have been preserved by the calling conventions.
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422
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423 hal_cpu_int_merge d2 # Restore previous PSW
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424 mov a2,sp # restore old SP
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425 movm (sp),[d2,a2] # Retrieve old work regs
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426 ret [],0 # and return
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427
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428 #endif
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429
0
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430 ##-----------------------------------------------------------------------------
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431 ## Default NMI VSR
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432
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433 .globl _cyg_hal_exception_handler
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434
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435 .text
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436 .globl __default_nmi_vsr
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437 __default_nmi_vsr:
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438
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439 # We come here with all the registers saved
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440 # on the stack.
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441
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442 hal_diag_excpt_start
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443
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444 # Decode the cause of the NMI and cancel all the bits in all
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445 # the registers. We need to clear any bits set in the ISR and
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446 # then clear any bits set in the NMICR. Note that we can only
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447 # access the ISR if the DCR:DE bit is set.
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448
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449 movhu (NMICR),d0 # D0 = NMI Control register
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450
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451 movhu (DCR),d1 # D1 = Debug Control Register
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452 mov d1,d2 # D2 = copy of DCR
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453 movhu (ISR),d3 # D3 = Interrupt Status Register
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454
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455 or DCR_DE,d1 # Set DE bit
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456 movhu d1,(DCR)
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457
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458 movhu d3,(ISR) # clear ISR bits
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459
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460 movhu d2,(DCR) # restore DCR to original value
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461
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462 movhu d0,(NMICR) # clear NMI bits
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463 and 0x7,d0 # LS 3 bits only
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464
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465 mov hal_lsbit_table,a0
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466 movbu (d0,a0),d1 # D1 = NMI code
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467 ## 0 = NMI
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468 ## 1 = Watchdog
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469 ## 2 = System Error
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470
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471 add 9,d1 # offset into exception number space
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472
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473 hal_cpu_clear_nmid
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474
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475 mov sp,a1 # a1 = saved state
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476 mov a1,d0 # d0 = arg1 = saved state
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477
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478 add -16,sp # return link + args
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479 mov d1,(16,sp) # save initial vector in spare save slot
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480 mov d3,d1 # d1 = arg2 = ISR value
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481
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482 calls _cyg_hal_exception_handler # call C code
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483
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484 add 16,sp # pop args
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485
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486 hal_cpu_load_all
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487
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488 add 4,sp
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489 rti
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490
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491 .globl hal_lsbit_table
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492 hal_lsbit_table:
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493 .byte 0, 0, 1, 0
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494 .byte 2, 0, 1, 0
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495 .byte 3, 0, 1, 0
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496 .byte 2, 0, 1, 0
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497
0
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498 ##-----------------------------------------------------------------------------
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499 ## Default TRAP VSR
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500
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501 .text
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502 .globl __default_trap_vsr
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503 __default_trap_vsr:
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504
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505 # We come here with all the registers saved
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506 # on the stack.
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507
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508 add -8,sp # return link + arg
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509 mov 3,d1 # 3 == TRAP trap
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510 mov d1,(0,sp) # save in spare save slot
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511 calls _cyg_hal_exception_handler # call C code
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512 add 8,sp # pop args
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513 hal_cpu_load_all
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514 add 4,sp
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515 rets
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516
0
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517 ##-----------------------------------------------------------------------------
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518 ## VSR table. The VSRs pointed to by this table are called from the stubs
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519 ## connected to the hardware.
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520
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521 #ifndef CYG_HAL_MN10300_VSR_TABLE_DEFINED
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522
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523 .data
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524
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525 .globl _hal_vsr_table
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526 _hal_vsr_table:
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527 .long __default_interrupt_vsr
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528 .long __default_interrupt_vsr
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529 .long __default_interrupt_vsr
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530 .long __default_interrupt_vsr
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531 .long __default_interrupt_vsr
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532 .long __default_interrupt_vsr
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533 .long __default_interrupt_vsr
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534 .long __default_nmi_vsr
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535 .long __default_trap_vsr
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536
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537 .long __default_nmi_vsr
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538 .long __default_nmi_vsr
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539 .long __default_nmi_vsr
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540
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541 .long __default_nmi_vsr
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542 .long __default_nmi_vsr
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543 .long __default_nmi_vsr
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544 .long __default_nmi_vsr
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545 .long __default_nmi_vsr
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546 .long __default_nmi_vsr
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547 .long __default_nmi_vsr
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548 .long __default_nmi_vsr
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549 .long __default_nmi_vsr
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550 .long __default_nmi_vsr
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551 .long __default_nmi_vsr
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552 .long __default_nmi_vsr
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553 .long __default_nmi_vsr
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554 .long __default_nmi_vsr
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555 .long __default_nmi_vsr
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556 .long __default_nmi_vsr
0
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557 #endif
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558
0
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559 ##-----------------------------------------------------------------------------
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560 ## Interrupt tables
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561
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562 .data
0
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563
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564 .extern _hal_default_isr
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565
0
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566 .globl _hal_interrupt_handlers
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567 _hal_interrupt_handlers:
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568 .rept CYG_ISR_TABLE_SIZE
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569 .long _hal_default_isr
0
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570 .endr
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571
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572 .globl _hal_interrupt_data
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573 _hal_interrupt_data:
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574 .rept CYG_ISR_TABLE_SIZE
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575 .long 0
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576 .endr
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577
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578 .globl _hal_interrupt_objects
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579 _hal_interrupt_objects:
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580 .rept CYG_ISR_TABLE_SIZE
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581 .long 0
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582 .endr
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583
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584
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585 ##-----------------------------------------------------------------------------
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586 ## Temporary interrupt stack
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587
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588 .section ".bss"
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589
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590 .balign 16
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591 .global _cyg_interrupt_stack_base
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592 _cyg_interrupt_stack_base:
0
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593 __interrupt_stack_base:
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594 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
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595 .byte 0
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596 .endr
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597 .balign 16
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598 .global _cyg_interrupt_stack
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599 _cyg_interrupt_stack:
0
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600 __interrupt_stack:
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601
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602 .long 0,0,0,0,0,0,0,0
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603
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604 ##-----------------------------------------------------------------------------
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605
0
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606 .data
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607 hal_diag_data
0
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608
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609 ##-----------------------------------------------------------------------------
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610 ## end of vectors.S
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611