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annotate packages/hal/powerpc/quicc/current/include/ppc8xx.h @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 29bc183297e1
children bf00f99aec69
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1 #ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H
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2 #define CYGONCE_HAL_PPC_QUICC_PPC8XX_H
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3
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4 //==========================================================================
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5 //
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6 // ppc8xx.h
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7 //
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8 // PowerPC QUICC register definitions
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9 //
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10 //==========================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.0 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://sourceware.cygnus.com/ecos
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18 //
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19 // Software distributed under the License is distributed on an
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //==========================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): Red Hat
32
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38 // Contributors: hmt
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39 // Date: 1999-06-08
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40 // Purpose: Provide PPC QUICC definitions
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41 // Description: Provide PPC QUICC definitions
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42 // Usage: THIS IS NOT AN EXTERNAL API
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43 // This file is in the include dir to share it between
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44 // QUICC serial code and MBX initialization code.
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45 // #include <cyg/hal/quicc/ppc8xx.h>
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46 // ...
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47 //
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48 //
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49 //####DESCRIPTIONEND####
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50 //
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51 //==========================================================================
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52
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53 #ifdef __ASSEMBLER__
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54
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55 #define SIUMCR 0x000 /* SIU Module configuration */
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56 #define SYPCR 0x004 /* SIU System Protection Control */
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57 #define SIPEND 0x010 /* SIU Interrupt Pending Register */
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58 #define SIMASK 0x014 /* SIU Interrupt MASK Register */
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59 #define SIEL 0x018 /* SIU Interrupt Edge/Level Register */
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60 #define SIVEC 0x01C /* SIU Interrupt Vector Register */
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61 #define SDCR 0x030 /* SDMA Config Register */
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62 #define BR0 0x100 /* Base Register 0 */
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63 #define OR0 0x104 /* Option Register 0 */
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64 #define BR1 0x108 /* Base Register 1 */
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65 #define OR1 0x10C /* Option Register 1 */
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66 #define BR2 0x110 /* Base Register 2 */
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67 #define OR2 0x114 /* Option Register 2 */
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68 #define BR3 0x118 /* Base Register 2 */
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69 #define OR3 0x11C /* Option Register 2 */
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70 #define BR4 0x120 /* Base Register 2 */
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71 #define OR4 0x124 /* Option Register 2 */
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72 #define BR5 0x128 /* Base Register 2 */
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73 #define OR5 0x12C /* Option Register 2 */
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74 #define BR6 0x130 /* Base Register 2 */
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75 #define OR6 0x134 /* Option Register 2 */
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76 #define BR7 0x138 /* Base Register 2 */
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77 #define OR7 0x13C /* Option Register 2 */
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78 #define MAR 0x164 /* Memory Address */
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79 #define MCR 0x168 /* Memory Command */
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80 #define MAMR 0x170 /* Machine A Mode Register */
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81 #define MBMR 0x174 /* Machine B Mode Register */
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82 #define MPTPR 0x17A /* Memory Periodic Timer Prescaler */
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83 #define MDR 0x17C /* Memory Data */
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84 #define TBSCR 0x200 /* Time Base Status and Control Register */
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85 #define RTCSC 0x220 /* Real Timer Clock Status and Control */
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86 #define PISCR 0x240 /* PIT Status and Control */
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87 #define SCCR 0x280 /* System Clock Control Register */
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88 #define PLPRCR 0x284 /* PLL, Low power & Reset Control Register */
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89 #define RTCSCK 0x320
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90 #define RTCK 0x324
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91 #define RTSECK 0x328
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92 #define RTCALK 0x32C
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93
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94 #else
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95
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96 /*****************************************************************
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97 Communications Processor Buffer Descriptor
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98 *****************************************************************/
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99 struct cp_bufdesc {
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100 volatile unsigned short ctrl; /* status/control register */
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101 volatile unsigned short length; /* buffer length */
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102 volatile char *buffer; /* buffer pointer */
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103 };
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104
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105 /*****************************************************************
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106 HDLC parameter RAM
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107 *****************************************************************/
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108
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109 struct hdlc_pram {
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110 /*
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111 * SCC parameter RAM
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112 */
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113 unsigned short rbase; /* RX BD base address */
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114 unsigned short tbase; /* TX BD base address */
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115 unsigned char rfcr; /* Rx function code */
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116 unsigned char tfcr; /* Tx function code */
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117 unsigned short mrblr; /* Rx buffer length */
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118 unsigned long rstate; /* Rx internal state */
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119 unsigned long rptr; /* Rx internal data pointer */
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120 unsigned short rbptr; /* rb BD Pointer */
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121 unsigned short rcount; /* Rx internal byte count */
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122 unsigned long rtemp; /* Rx temp */
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123 unsigned long tstate; /* Tx internal state */
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124 unsigned long tptr; /* Tx internal data pointer */
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125 unsigned short tbptr; /* Tx BD pointer */
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126 unsigned short tcount; /* Tx byte count */
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127 unsigned long ttemp; /* Tx temp */
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128 unsigned long rcrc; /* temp receive CRC */
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129 unsigned long tcrc; /* temp transmit CRC */
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130
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131 /*
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132 * HDLC specific parameter RAM
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133 */
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134 unsigned char RSRVD1[4];
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135 unsigned long c_mask; /* CRC constant */
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136 unsigned long c_pres; /* CRC preset */
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137 unsigned short disfc; /* discarded frame counter */
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138 unsigned short crcec; /* CRC error counter */
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139 unsigned short abtsc; /* abort sequence counter */
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140 unsigned short nmarc; /* nonmatching address rx cnt */
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141 unsigned short retrc; /* frame retransmission cnt */
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142 unsigned short mflr; /* maximum frame length reg */
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143 unsigned short max_cnt; /* maximum length counter */
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144 unsigned short rfthr; /* received frames threshold */
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145 unsigned short rfcnt; /* received frames count */
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146 unsigned short hmask; /* user defined frm addr mask */
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147 unsigned short haddr1; /* user defined frm address 1 */
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148 unsigned short haddr2; /* user defined frm address 2 */
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149 unsigned short haddr3; /* user defined frm address 3 */
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150 unsigned short haddr4; /* user defined frm address 4 */
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151 unsigned short tmp; /* temp */
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152 unsigned short tmp_mb; /* temp */
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153 };
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154
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155
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156 /*****************************************************************
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157 ASYNC HDLC parameter RAM
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158 *****************************************************************/
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159
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160 struct async_hdlc_pram {
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161 /*
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162 * SCC parameter RAM
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163 */
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164 unsigned short rbase; /* RX BD base address */
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165 unsigned short tbase; /* TX BD base address */
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166 unsigned char rfcr; /* Rx function code */
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167 unsigned char tfcr; /* Tx function code */
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168 unsigned short mrblr; /* Rx buffer length */
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169 unsigned long rstate; /* Rx internal state */
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170 unsigned long rptr; /* Rx internal data pointer */
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171 unsigned short rbptr; /* rb BD Pointer */
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172 unsigned short rcount; /* Rx internal byte count */
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173 unsigned long rtemp; /* Rx temp */
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174 unsigned long tstate; /* Tx internal state */
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175 unsigned long tptr; /* Tx internal data pointer */
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176 unsigned short tbptr; /* Tx BD pointer */
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177 unsigned short tcount; /* Tx byte count */
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178 unsigned long ttemp; /* Tx temp */
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179 unsigned long rcrc; /* temp receive CRC */
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180 unsigned long tcrc; /* temp transmit CRC */
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181
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182 /*
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183 * ASYNC HDLC specific parameter RAM
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184 */
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185 unsigned char RSRVD1[4];
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186 unsigned long c_mask; /* CRC constant */
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187 unsigned long c_pres; /* CRC preset */
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188 unsigned short bof; /* begining of flag character */
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189 unsigned short eof; /* end of flag character */
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190 unsigned short esc; /* control escape character */
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191 unsigned char RSRVD2[4];
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192 unsigned short zero; /* zero */
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193 unsigned char RSRVD3[2];
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194 unsigned short rfthr; /* received frames threshold */
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195 unsigned char RSRVD4[4];
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196 unsigned long txctl_tbl; /* Tx ctl char mapping table */
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197 unsigned long rxctl_tbl; /* Rx ctl char mapping table */
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198 unsigned short nof; /* Number of opening flags */
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199 };
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200
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201
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202 /*****************************************************************
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203 UART parameter RAM
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204 *****************************************************************/
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205
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206 /*
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207 * bits in uart control characters table
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208 */
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209 #define CC_INVALID 0x8000 /* control character is valid */
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210 #define CC_REJ 0x4000 /* don't store char in buffer */
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211 #define CC_CHAR 0x00ff /* control character */
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212
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213 /* UART */
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214 struct uart_pram {
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215 /*
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216 * SCC parameter RAM
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217 */
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218 unsigned short rbase; /* RX BD base address */
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219 unsigned short tbase; /* TX BD base address */
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220 unsigned char rfcr; /* Rx function code */
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221 unsigned char tfcr; /* Tx function code */
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222 unsigned short mrblr; /* Rx buffer length */
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223 unsigned long rstate; /* Rx internal state */
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224 unsigned long rptr; /* Rx internal data pointer */
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225 unsigned short rbptr; /* rb BD Pointer */
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226 unsigned short rcount; /* Rx internal byte count */
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227 unsigned long rx_temp; /* Rx temp */
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228 unsigned long tstate; /* Tx internal state */
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229 unsigned long tptr; /* Tx internal data pointer */
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230 unsigned short tbptr; /* Tx BD pointer */
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231 unsigned short tcount; /* Tx byte count */
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232 unsigned long ttemp; /* Tx temp */
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233 unsigned long rcrc; /* temp receive CRC */
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234 unsigned long tcrc; /* temp transmit CRC */
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235
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236 /*
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237 * UART specific parameter RAM
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238 */
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239 unsigned char RSRVD1[8];
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240 unsigned short max_idl; /* maximum idle characters */
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241 unsigned short idlc; /* rx idle counter (internal) */
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242 unsigned short brkcr; /* break count register */
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243
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244 unsigned short parec; /* Rx parity error counter */
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245 unsigned short frmer; /* Rx framing error counter */
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246 unsigned short nosec; /* Rx noise counter */
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247 unsigned short brkec; /* Rx break character counter */
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248 unsigned short brkln; /* Reaceive break length */
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249
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250 unsigned short uaddr1; /* address character 1 */
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251 unsigned short uaddr2; /* address character 2 */
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252 unsigned short rtemp; /* temp storage */
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253 unsigned short toseq; /* Tx out of sequence char */
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254 unsigned short cc[8]; /* Rx control characters */
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255 unsigned short rccm; /* Rx control char mask */
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256 unsigned short rccr; /* Rx control char register */
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257 unsigned short rlbc; /* Receive last break char */
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258 };
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259
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260
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261
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262 /*****************************************************************
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263 BISYNC parameter RAM
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264 *****************************************************************/
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265
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266 struct bisync_pram {
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267 /*
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268 * SCC parameter RAM
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269 */
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270 unsigned short rbase; /* RX BD base address */
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271 unsigned short tbase; /* TX BD base address */
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272 unsigned char rfcr; /* Rx function code */
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273 unsigned char tfcr; /* Tx function code */
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274 unsigned short mrblr; /* Rx buffer length */
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275 unsigned long rstate; /* Rx internal state */
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276 unsigned long rptr; /* Rx internal data pointer */
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277 unsigned short rbptr; /* rb BD Pointer */
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278 unsigned short rcount; /* Rx internal byte count */
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279 unsigned long rtemp; /* Rx temp */
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280 unsigned long tstate; /* Tx internal state */
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281 unsigned long tptr; /* Tx internal data pointer */
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282 unsigned short tbptr; /* Tx BD pointer */
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283 unsigned short tcount; /* Tx byte count */
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284 unsigned long ttemp; /* Tx temp */
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285 unsigned long rcrc; /* temp receive CRC */
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286 unsigned long tcrc; /* temp transmit CRC */
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287
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288 /*
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289 * BISYNC specific parameter RAM
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290 */
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291 unsigned char RSRVD1[4];
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292 unsigned long crcc; /* CRC Constant Temp Value */
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293 unsigned short prcrc; /* Preset Receiver CRC-16/LRC */
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294 unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */
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295 unsigned short parec; /* Receive Parity Error Counter */
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296 unsigned short bsync; /* BISYNC SYNC Character */
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297 unsigned short bdle; /* BISYNC DLE Character */
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298 unsigned short cc[8]; /* Rx control characters */
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299 unsigned short rccm; /* Receive Control Character Mask */
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300 };
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301
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302 /*****************************************************************
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303 IOM2 parameter RAM
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304 (overlaid on tx bd[5] of SCC channel[2])
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305 *****************************************************************/
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306 struct iom2_pram {
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307 unsigned short ci_data; /* ci data */
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308 unsigned short monitor_data; /* monitor data */
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309 unsigned short tstate; /* transmitter state */
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310 unsigned short rstate; /* receiver state */
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311 };
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312
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313 /*****************************************************************
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314 SPI/SMC parameter RAM
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315 (overlaid on tx bd[6,7] of SCC channel[2])
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316 *****************************************************************/
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317
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318 #define SPI_R 0x8000 /* Ready bit in BD */
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319
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320 struct spi_pram {
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321 unsigned short rbase; /* Rx BD Base Address */
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322 unsigned short tbase; /* Tx BD Base Address */
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323 unsigned char rfcr; /* Rx function code */
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324 unsigned char tfcr; /* Tx function code */
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325 unsigned short mrblr; /* Rx buffer length */
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326 unsigned long rstate; /* Rx internal state */
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327 unsigned long rptr; /* Rx internal data pointer */
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328 unsigned short rbptr; /* rb BD Pointer */
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329 unsigned short rcount; /* Rx internal byte count */
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330 unsigned long rtemp; /* Rx temp */
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331 unsigned long tstate; /* Tx internal state */
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332 unsigned long tptr; /* Tx internal data pointer */
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333 unsigned short tbptr; /* Tx BD pointer */
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334 unsigned short tcount; /* Tx byte count */
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335 unsigned long ttemp; /* Tx temp */
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336 };
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337
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338 struct smc_uart_pram {
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339 unsigned short rbase; /* Rx BD Base Address */
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340 unsigned short tbase; /* Tx BD Base Address */
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341 unsigned char rfcr; /* Rx function code */
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342 unsigned char tfcr; /* Tx function code */
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343 unsigned short mrblr; /* Rx buffer length */
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344 unsigned long rstate; /* Rx internal state */
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345 unsigned long rptr; /* Rx internal data pointer */
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346 unsigned short rbptr; /* rb BD Pointer */
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347 unsigned short rcount; /* Rx internal byte count */
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348 unsigned long rtemp; /* Rx temp */
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349 unsigned long tstate; /* Tx internal state */
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350 unsigned long tptr; /* Tx internal data pointer */
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351 unsigned short tbptr; /* Tx BD pointer */
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352 unsigned short tcount; /* Tx byte count */
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353 unsigned long ttemp; /* Tx temp */
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354 unsigned short max_idl; /* Maximum IDLE Characters */
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355 unsigned short idlc; /* Temporary IDLE Counter */
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356 unsigned short brkln; /* Last Rx Break Length */
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357 unsigned short brkec; /* Rx Break Condition Counter */
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358 unsigned short brkcr; /* Break Count Register (Tx) */
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359 unsigned short r_mask; /* Temporary bit mask */
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360 };
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361
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362 struct smc_trnsp_pram {
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363 unsigned short rbase; /* Rx BD Base Address */
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364 unsigned short tbase; /* Tx BD Base Address */
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365 unsigned char rfcr; /* Rx function code */
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366 unsigned char tfcr; /* Tx function code */
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367 unsigned short mrblr; /* Rx buffer length */
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368 unsigned long rstate; /* Rx internal state */
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369 unsigned long rptr; /* Rx internal data pointer */
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370 unsigned short rbptr; /* rb BD Pointer */
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371 unsigned short rcount; /* Rx internal byte count */
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372 unsigned long rtemp; /* Rx temp */
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373 unsigned long tstate; /* Tx internal state */
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374 unsigned long tptr; /* Tx internal data pointer */
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375 unsigned short tbptr; /* Tx BD pointer */
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376 unsigned short tcount; /* Tx byte count */
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377 unsigned long ttemp; /* Tx temp */
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378 unsigned short RSRVD[5]; /* RSRVD */
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379 };
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380
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381 struct centronics_pram {
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382 unsigned short rbase; /* Rx BD Base Address */
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383 unsigned short tbase; /* Tx BD Base Address */
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384 unsigned char fcr; /* function code */
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385 unsigned char smask; /* Status Mask */
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386 unsigned short mrblr; /* Rx buffer length */
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387 unsigned long rstate; /* Rx internal state */
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388 unsigned long rptr; /* Rx internal data pointer */
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389 unsigned short rbptr; /* rb BD Pointer */
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390 unsigned short rcount; /* Rx internal byte count */
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391 unsigned long rtemp; /* Rx temp */
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392 unsigned long tstate; /* Tx internal state */
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393 unsigned long tptr; /* Tx internal data pointer */
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394 unsigned short tbptr; /* Tx BD pointer */
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395 unsigned short tcount; /* Tx byte count */
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396 unsigned long ttemp; /* Tx temp */
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397 unsigned short max_sl; /* Maximum Silence period */
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398 unsigned short sl_cnt; /* Silence Counter */
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399 unsigned short char1; /* CONTROL char 1 */
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400 unsigned short char2; /* CONTROL char 2 */
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401 unsigned short char3; /* CONTROL char 3 */
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402 unsigned short char4; /* CONTROL char 4 */
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403 unsigned short char5; /* CONTROL char 5 */
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404 unsigned short char6; /* CONTROL char 6 */
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405 unsigned short char7; /* CONTROL char 7 */
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406 unsigned short char8; /* CONTROL char 8 */
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407 unsigned short rccm; /* Rx Control Char Mask */
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408 unsigned short rccr; /* Rx Char Control Register */
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409 };
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410
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411 struct idma_pram {
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412 unsigned short ibase; /* IDMA BD Base Address */
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413 unsigned short ibptr; /* IDMA buffer descriptor pointer */
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414 unsigned long istate; /* IDMA internal state */
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415 unsigned long itemp; /* IDMA temp */
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416 };
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417
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418 struct ethernet_pram {
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419 /*
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420 * SCC parameter RAM
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421 */
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422 unsigned short rbase; /* RX BD base address */
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423 unsigned short tbase; /* TX BD base address */
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424 unsigned char rfcr; /* Rx function code */
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425 unsigned char tfcr; /* Tx function code */
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426 unsigned short mrblr; /* Rx buffer length */
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427 unsigned long rstate; /* Rx internal state */
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428 unsigned long rptr; /* Rx internal data pointer */
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429 unsigned short rbptr; /* rb BD Pointer */
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430 unsigned short rcount; /* Rx internal byte count */
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431 unsigned long rtemp; /* Rx temp */
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432 unsigned long tstate; /* Tx internal state */
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433 unsigned long tptr; /* Tx internal data pointer */
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434 unsigned short tbptr; /* Tx BD pointer */
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435 unsigned short tcount; /* Tx byte count */
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parents:
diff changeset
436 unsigned long ttemp; /* Tx temp */
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jlarmour
parents:
diff changeset
437 unsigned long rcrc; /* temp receive CRC */
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jlarmour
parents:
diff changeset
438 unsigned long tcrc; /* temp transmit CRC */
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jlarmour
parents:
diff changeset
439
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jlarmour
parents:
diff changeset
440 /*
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jlarmour
parents:
diff changeset
441 * ETHERNET specific parameter RAM
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jlarmour
parents:
diff changeset
442 */
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jlarmour
parents:
diff changeset
443 unsigned long c_pres; /* preset CRC */
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jlarmour
parents:
diff changeset
444 unsigned long c_mask; /* constant mask for CRC */
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jlarmour
parents:
diff changeset
445 unsigned long crcec; /* CRC error counter */
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jlarmour
parents:
diff changeset
446 unsigned long alec; /* alighnment error counter */
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jlarmour
parents:
diff changeset
447 unsigned long disfc; /* discard frame counter */
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jlarmour
parents:
diff changeset
448 unsigned short pads; /* short frame PAD characters */
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jlarmour
parents:
diff changeset
449 unsigned short ret_lim; /* retry limit threshold */
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jlarmour
parents:
diff changeset
450 unsigned short ret_cnt; /* retry limit counter */
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jlarmour
parents:
diff changeset
451 unsigned short mflr; /* maximum frame length reg */
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jlarmour
parents:
diff changeset
452 unsigned short minflr; /* minimum frame length reg */
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jlarmour
parents:
diff changeset
453 unsigned short maxd1; /* maximum DMA1 length reg */
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jlarmour
parents:
diff changeset
454 unsigned short maxd2; /* maximum DMA2 length reg */
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jlarmour
parents:
diff changeset
455 unsigned short maxd; /* rx max DMA */
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jlarmour
parents:
diff changeset
456 unsigned short dma_cnt; /* rx dma counter */
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jlarmour
parents:
diff changeset
457 unsigned short max_b; /* max bd byte count */
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jlarmour
parents:
diff changeset
458 unsigned short gaddr1; /* group address filter 1 */
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jlarmour
parents:
diff changeset
459 unsigned short gaddr2; /* group address filter 2 */
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jlarmour
parents:
diff changeset
460 unsigned short gaddr3; /* group address filter 3 */
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jlarmour
parents:
diff changeset
461 unsigned short gaddr4; /* group address filter 4 */
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jlarmour
parents:
diff changeset
462 unsigned long tbuf0_data0; /* save area 0 - current frm */
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jlarmour
parents:
diff changeset
463 unsigned long tbuf0_data1; /* save area 1 - current frm */
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jlarmour
parents:
diff changeset
464 unsigned long tbuf0_rba0;
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jlarmour
parents:
diff changeset
465 unsigned long tbuf0_crc;
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jlarmour
parents:
diff changeset
466 unsigned short tbuf0_bcnt;
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jlarmour
parents:
diff changeset
467 unsigned short paddr_h; /* physical address (MSB) */
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jlarmour
parents:
diff changeset
468 unsigned short paddr_m; /* physical address */
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jlarmour
parents:
diff changeset
469 unsigned short paddr_l; /* physical address (LSB) */
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jlarmour
parents:
diff changeset
470 unsigned short p_per; /* persistence */
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jlarmour
parents:
diff changeset
471 unsigned short rfbd_ptr; /* rx first bd pointer */
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jlarmour
parents:
diff changeset
472 unsigned short tfbd_ptr; /* tx first bd pointer */
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jlarmour
parents:
diff changeset
473 unsigned short tlbd_ptr; /* tx last bd pointer */
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jlarmour
parents:
diff changeset
474 unsigned long tbuf1_data0; /* save area 0 - next frame */
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jlarmour
parents:
diff changeset
475 unsigned long tbuf1_data1; /* save area 1 - next frame */
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jlarmour
parents:
diff changeset
476 unsigned long tbuf1_rba0;
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jlarmour
parents:
diff changeset
477 unsigned long tbuf1_crc;
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jlarmour
parents:
diff changeset
478 unsigned short tbuf1_bcnt;
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jlarmour
parents:
diff changeset
479 unsigned short tx_len; /* tx frame length counter */
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jlarmour
parents:
diff changeset
480 unsigned short iaddr1; /* individual address filter 1*/
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jlarmour
parents:
diff changeset
481 unsigned short iaddr2; /* individual address filter 2*/
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jlarmour
parents:
diff changeset
482 unsigned short iaddr3; /* individual address filter 3*/
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jlarmour
parents:
diff changeset
483 unsigned short iaddr4; /* individual address filter 4*/
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jlarmour
parents:
diff changeset
484 unsigned short boff_cnt; /* back-off counter */
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jlarmour
parents:
diff changeset
485 unsigned short taddr_h; /* temp address (MSB) */
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jlarmour
parents:
diff changeset
486 unsigned short taddr_m; /* temp address */
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jlarmour
parents:
diff changeset
487 unsigned short taddr_l; /* temp address (LSB) */
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jlarmour
parents:
diff changeset
488 };
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jlarmour
parents:
diff changeset
489
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jlarmour
parents:
diff changeset
490 struct transparent_pram {
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jlarmour
parents:
diff changeset
491 /*
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jlarmour
parents:
diff changeset
492 * SCC parameter RAM
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jlarmour
parents:
diff changeset
493 */
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jlarmour
parents:
diff changeset
494 unsigned short rbase; /* RX BD base address */
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jlarmour
parents:
diff changeset
495 unsigned short tbase; /* TX BD base address */
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jlarmour
parents:
diff changeset
496 unsigned char rfcr; /* Rx function code */
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jlarmour
parents:
diff changeset
497 unsigned char tfcr; /* Tx function code */
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jlarmour
parents:
diff changeset
498 unsigned short mrblr; /* Rx buffer length */
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jlarmour
parents:
diff changeset
499 unsigned long rstate; /* Rx internal state */
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jlarmour
parents:
diff changeset
500 unsigned long rptr; /* Rx internal data pointer */
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jlarmour
parents:
diff changeset
501 unsigned short rbptr; /* rb BD Pointer */
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jlarmour
parents:
diff changeset
502 unsigned short rcount; /* Rx internal byte count */
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jlarmour
parents:
diff changeset
503 unsigned long rtemp; /* Rx temp */
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jlarmour
parents:
diff changeset
504 unsigned long tstate; /* Tx internal state */
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jlarmour
parents:
diff changeset
505 unsigned long tptr; /* Tx internal data pointer */
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jlarmour
parents:
diff changeset
506 unsigned short tbptr; /* Tx BD pointer */
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jlarmour
parents:
diff changeset
507 unsigned short tcount; /* Tx byte count */
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jlarmour
parents:
diff changeset
508 unsigned long ttemp; /* Tx temp */
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jlarmour
parents:
diff changeset
509 unsigned long rcrc; /* temp receive CRC */
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jlarmour
parents:
diff changeset
510 unsigned long tcrc; /* temp transmit CRC */
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jlarmour
parents:
diff changeset
511
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jlarmour
parents:
diff changeset
512 /*
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jlarmour
parents:
diff changeset
513 * TRANSPARENT specific parameter RAM
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jlarmour
parents:
diff changeset
514 */
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jlarmour
parents:
diff changeset
515 unsigned long crc_p; /* CRC Preset */
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jlarmour
parents:
diff changeset
516 unsigned long crc_c; /* CRC constant */
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jlarmour
parents:
diff changeset
517 };
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jlarmour
parents:
diff changeset
518
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jlarmour
parents:
diff changeset
519 struct timer_pram {
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jlarmour
parents:
diff changeset
520 /*
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jlarmour
parents:
diff changeset
521 * RISC timers parameter RAM
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jlarmour
parents:
diff changeset
522 */
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jlarmour
parents:
diff changeset
523 unsigned short tm_base; /* RISC timer table base adr */
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jlarmour
parents:
diff changeset
524 unsigned short tm_ptr; /* RISC timer table pointer */
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jlarmour
parents:
diff changeset
525 unsigned short r_tmr; /* RISC timer mode register */
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jlarmour
parents:
diff changeset
526 unsigned short r_tmv; /* RISC timer valid register */
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jlarmour
parents:
diff changeset
527 unsigned long tm_cmd; /* RISC timer cmd register */
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jlarmour
parents:
diff changeset
528 unsigned long tm_cnt; /* RISC timer internal cnt */
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jlarmour
parents:
diff changeset
529 };
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jlarmour
parents:
diff changeset
530
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jlarmour
parents:
diff changeset
531 struct ucode_pram {
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jlarmour
parents:
diff changeset
532 /*
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jlarmour
parents:
diff changeset
533 * RISC ucode parameter RAM
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jlarmour
parents:
diff changeset
534 */
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jlarmour
parents:
diff changeset
535 unsigned short rev_num; /* Ucode Revision Number */
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jlarmour
parents:
diff changeset
536 unsigned short d_ptr; /* MISC Dump area pointer */
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jlarmour
parents:
diff changeset
537 unsigned long temp1; /* MISC Temp1 */
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jlarmour
parents:
diff changeset
538 unsigned long temp2; /* MISC Temp2 */
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jlarmour
parents:
diff changeset
539 };
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jlarmour
parents:
diff changeset
540
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jlarmour
parents:
diff changeset
541 struct i2c_pram {
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jlarmour
parents:
diff changeset
542 /*
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jlarmour
parents:
diff changeset
543 * I2C parameter RAM
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
544 */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
545 unsigned short rbase; /* RX BD base address */
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jlarmour
parents:
diff changeset
546 unsigned short tbase; /* TX BD base address */
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jlarmour
parents:
diff changeset
547 unsigned char rfcr; /* Rx function code */
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jlarmour
parents:
diff changeset
548 unsigned char tfcr; /* Tx function code */
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jlarmour
parents:
diff changeset
549 unsigned short mrblr; /* Rx buffer length */
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jlarmour
parents:
diff changeset
550 unsigned long rstate; /* Rx internal state */
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jlarmour
parents:
diff changeset
551 unsigned long rptr; /* Rx internal data pointer */
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jlarmour
parents:
diff changeset
552 unsigned short rbptr; /* rb BD Pointer */
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jlarmour
parents:
diff changeset
553 unsigned short rcount; /* Rx internal byte count */
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jlarmour
parents:
diff changeset
554 unsigned long rtemp; /* Rx temp */
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jlarmour
parents:
diff changeset
555 unsigned long tstate; /* Tx internal state */
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jlarmour
parents:
diff changeset
556 unsigned long tptr; /* Tx internal data pointer */
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jlarmour
parents:
diff changeset
557 unsigned short tbptr; /* Tx BD pointer */
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jlarmour
parents:
diff changeset
558 unsigned short tcount; /* Tx byte count */
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jlarmour
parents:
diff changeset
559 unsigned long ttemp; /* Tx temp */
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jlarmour
parents:
diff changeset
560 };
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jlarmour
parents:
diff changeset
561
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
562 /*
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jlarmour
parents:
diff changeset
563 * definitions of EPPC memory structures
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jlarmour
parents:
diff changeset
564 */
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jlarmour
parents:
diff changeset
565 typedef struct eppc {
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jlarmour
parents:
diff changeset
566 /* BASE + 0x0000: INTERNAL REGISTERS */
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jlarmour
parents:
diff changeset
567
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jlarmour
parents:
diff changeset
568 /* SIU */
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jlarmour
parents:
diff changeset
569 volatile unsigned long siu_mcr; /* module configuration reg */
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jlarmour
parents:
diff changeset
570 volatile unsigned long siu_sypcr; /* System protection cnt */
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jlarmour
parents:
diff changeset
571 unsigned char RSRVD58[0x6];
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jlarmour
parents:
diff changeset
572 volatile unsigned short siu_swsr; /* sw service */
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jlarmour
parents:
diff changeset
573 volatile unsigned long siu_sipend; /* Interrupt pend reg */
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jlarmour
parents:
diff changeset
574 volatile unsigned long siu_simask; /* Interrupt mask reg */
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jlarmour
parents:
diff changeset
575 volatile unsigned long siu_siel; /* Interrupt edge level mask reg */
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jlarmour
parents:
diff changeset
576 volatile unsigned long siu_sivec; /* Interrupt vector */
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jlarmour
parents:
diff changeset
577 volatile unsigned long siu_tesr; /* Transfer error status */
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jlarmour
parents:
diff changeset
578 volatile unsigned char RSRVD1[0xc];
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jlarmour
parents:
diff changeset
579 volatile unsigned long dma_sdcr; /* SDMA configuration reg */
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jlarmour
parents:
diff changeset
580 unsigned char RSRVD55[0x4c];
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parents:
diff changeset
581
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jlarmour
parents:
diff changeset
582 /* PCMCIA */
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jlarmour
parents:
diff changeset
583 volatile unsigned long pcmcia_pbr0; /* PCMCIA Base Reg: Window 0 */
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parents:
diff changeset
584 volatile unsigned long pcmcia_por0; /* PCMCIA Option Reg: Window 0 */
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parents:
diff changeset
585 volatile unsigned long pcmcia_pbr1; /* PCMCIA Base Reg: Window 1 */
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parents:
diff changeset
586 volatile unsigned long pcmcia_por1; /* PCMCIA Option Reg: Window 1 */
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parents:
diff changeset
587 volatile unsigned long pcmcia_pbr2; /* PCMCIA Base Reg: Window 2 */
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parents:
diff changeset
588 volatile unsigned long pcmcia_por2; /* PCMCIA Option Reg: Window 2 */
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parents:
diff changeset
589 volatile unsigned long pcmcia_pbr3; /* PCMCIA Base Reg: Window 3 */
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parents:
diff changeset
590 volatile unsigned long pcmcia_por3; /* PCMCIA Option Reg: Window 3 */
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parents:
diff changeset
591 volatile unsigned long pcmcia_pbr4; /* PCMCIA Base Reg: Window 4 */
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parents:
diff changeset
592 volatile unsigned long pcmcia_por4; /* PCMCIA Option Reg: Window 4 */
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diff changeset
593 volatile unsigned long pcmcia_pbr5; /* PCMCIA Base Reg: Window 5 */
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diff changeset
594 volatile unsigned long pcmcia_por5; /* PCMCIA Option Reg: Window 5 */
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parents:
diff changeset
595 volatile unsigned long pcmcia_pbr6; /* PCMCIA Base Reg: Window 6 */
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parents:
diff changeset
596 volatile unsigned long pcmcia_por6; /* PCMCIA Option Reg: Window 6 */
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parents:
diff changeset
597 volatile unsigned long pcmcia_pbr7; /* PCMCIA Base Reg: Window 7 */
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parents:
diff changeset
598 volatile unsigned long pcmcia_por7; /* PCMCIA Option Reg: Window 7 */
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parents:
diff changeset
599 volatile unsigned char RSRVD2[0x20];
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jlarmour
parents:
diff changeset
600 volatile unsigned long pcmcia_pgcra; /* PCMCIA Slot A Control Reg */
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diff changeset
601 volatile unsigned long pcmcia_pgcrb; /* PCMCIA Slot B Control Reg */
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diff changeset
602 volatile unsigned long pcmcia_pscr; /* PCMCIA Status Reg */
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diff changeset
603 volatile unsigned char RSRVD2a[0x4];
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parents:
diff changeset
604 volatile unsigned long pcmcia_pipr; /* PCMCIA Pins Value Reg */
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diff changeset
605 volatile unsigned char RSRVD2b[0x4];
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parents:
diff changeset
606 volatile unsigned long pcmcia_per; /* PCMCIA Enable Reg */
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jlarmour
parents:
diff changeset
607 volatile unsigned char RSRVD2c[0x4];
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parents:
diff changeset
608
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parents:
diff changeset
609 /* MEMC */
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diff changeset
610 volatile unsigned long memc_br0; /* base register 0 */
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diff changeset
611 volatile unsigned long memc_or0; /* option register 0 */
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diff changeset
612 volatile unsigned long memc_br1; /* base register 1 */
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diff changeset
613 volatile unsigned long memc_or1; /* option register 1 */
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diff changeset
614 volatile unsigned long memc_br2; /* base register 2 */
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diff changeset
615 volatile unsigned long memc_or2; /* option register 2 */
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diff changeset
616 volatile unsigned long memc_br3; /* base register 3 */
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diff changeset
617 volatile unsigned long memc_or3; /* option register 3 */
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diff changeset
618 volatile unsigned long memc_br4; /* base register 3 */
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diff changeset
619 volatile unsigned long memc_or4; /* option register 3 */
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diff changeset
620 volatile unsigned long memc_br5; /* base register 3 */
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diff changeset
621 volatile unsigned long memc_or5; /* option register 3 */
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diff changeset
622 volatile unsigned long memc_br6; /* base register 3 */
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jlarmour
parents:
diff changeset
623 volatile unsigned long memc_or6; /* option register 3 */
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diff changeset
624 volatile unsigned long memc_br7; /* base register 3 */
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diff changeset
625 volatile unsigned long memc_or7; /* option register 3 */
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diff changeset
626 volatile unsigned char RSRVD3[0x24];
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parents:
diff changeset
627 volatile unsigned long memc_mar; /* Memory address */
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diff changeset
628 volatile unsigned long memc_mcr; /* Memory command */
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parents:
diff changeset
629 volatile unsigned char RSRVD4[0x4];
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parents:
diff changeset
630 volatile unsigned long memc_mamr; /* Machine A mode */
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parents:
diff changeset
631 volatile unsigned long memc_mbmr; /* Machine B mode */
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diff changeset
632 volatile unsigned short memc_mstat; /* Memory status */
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diff changeset
633 volatile unsigned short memc_mptpr; /* Memory preidic timer prescalar */
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parents:
diff changeset
634 volatile unsigned long memc_mdr; /* Memory data */
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parents:
diff changeset
635 volatile unsigned char RSRVD5[0x80];
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parents:
diff changeset
636
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parents:
diff changeset
637 /* SYSTEM INTEGRATION TIMERS */
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jlarmour
parents:
diff changeset
638 volatile unsigned short simt_tbscr; /* Time base stat&ctr */
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parents:
diff changeset
639 volatile unsigned char RSRVD100[0x2];
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jlarmour
parents:
diff changeset
640 volatile unsigned long simt_tbreff0; /* Time base reference 0 */
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parents:
diff changeset
641 volatile unsigned long simt_tbreff1; /* Time base reference 1 */
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diff changeset
642 volatile unsigned char RSRVD6[0x14];
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jlarmour
parents:
diff changeset
643 volatile unsigned short simt_rtcsc; /* Realtime clk stat&cntr 1 */
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jlarmour
parents:
diff changeset
644 volatile unsigned char RSRVD110[0x2];
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jlarmour
parents:
diff changeset
645 volatile unsigned long simt_rtc; /* Realtime clock */
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jlarmour
parents:
diff changeset
646 volatile unsigned long simt_rtsec; /* Realtime alarm seconds */
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parents:
diff changeset
647 volatile unsigned long simt_rtcal; /* Realtime alarm */
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parents:
diff changeset
648 volatile unsigned char RSRVD56[0x10];
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jlarmour
parents:
diff changeset
649 volatile unsigned long simt_piscr; /* PIT stat&ctrl */
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jlarmour
parents:
diff changeset
650 volatile unsigned long simt_pitc; /* PIT counter */
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diff changeset
651 volatile unsigned long simt_pitr; /* PIT */
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diff changeset
652 volatile unsigned char RSRVD7[0x34];
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diff changeset
653
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jlarmour
parents:
diff changeset
654 /* CLOCKS, RESET */
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diff changeset
655 volatile unsigned long clkr_sccr; /* System clk cntrl */
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diff changeset
656 volatile unsigned long clkr_plprcr; /* PLL reset&ctrl */
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diff changeset
657 volatile unsigned long clkr_rsr; /* reset status */
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diff changeset
658 volatile unsigned char RSRVD66a[0x74];
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diff changeset
659
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diff changeset
660 /* System Integration Timers Keys */
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diff changeset
661 volatile unsigned long simt_tbscrk; /* Timebase Status&Ctrl Key */
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diff changeset
662 volatile unsigned long simt_tbreff0k; /* Timebase Reference 0 Key */
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diff changeset
663 volatile unsigned long simt_tbreff1k; /* Timebase Reference 1 Key */
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diff changeset
664 volatile unsigned long simt_tbk; /* Timebase and Decrementer Key */
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diff changeset
665 volatile unsigned char RSRVD66b[0x10];
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parents:
diff changeset
666 volatile unsigned long simt_rtcsck; /* Real-Time Clock Status&Ctrl Key */
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diff changeset
667 volatile unsigned long simt_rtck; /* Real-Time Clock Key */
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diff changeset
668 volatile unsigned long simt_rtseck; /* Real-Time Alarm Seconds Key */
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diff changeset
669 volatile unsigned long simt_rtcalk; /* Real-Time Alarm Key */
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diff changeset
670 volatile unsigned char RSRVD66c[0x10];
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diff changeset
671 volatile unsigned long simt_piscrk; /* Periodic Interrupt Status&Ctrl Key */
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parents:
diff changeset
672 volatile unsigned long simt_pitck; /* Periodic Interrupt Count Key */
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jlarmour
parents:
diff changeset
673 volatile unsigned char RSRVD66d[0x38];
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jlarmour
parents:
diff changeset
674
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parents:
diff changeset
675
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jlarmour
parents:
diff changeset
676 /* Clock and Reset Keys */
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jlarmour
parents:
diff changeset
677 volatile unsigned long clkr_sccrk; /* System Clock Control Key */
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diff changeset
678 volatile unsigned long clkr_plprcrk; /* PLL, Low Power and Reset Control Key */
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diff changeset
679 volatile unsigned long clkr_rsrk; /* Reset Status Key */
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parents:
diff changeset
680 volatile unsigned char RSRVD66e[0x4b4];
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parents:
diff changeset
681
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diff changeset
682 volatile unsigned long lcd_lccr; /* configuration Reg */
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diff changeset
683 volatile unsigned long lcd_lchcr; /* Horizontal ctl Reg */
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parents:
diff changeset
684 volatile unsigned long lcd_lcvcr; /* Vertical ctl Reg */
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parents:
diff changeset
685 unsigned char RSRVD67[4];
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jlarmour
parents:
diff changeset
686 volatile unsigned long lcd_lcfaa; /* Frame buffer A Address */
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jlarmour
parents:
diff changeset
687 volatile unsigned long lcd_lcfba; /* Frame buffer B Address */
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jlarmour
parents:
diff changeset
688 volatile unsigned char lcd_lcsr; /* Status Reg */
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jlarmour
parents:
diff changeset
689 volatile unsigned char RSRVD9[0x7];
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parents:
diff changeset
690
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jlarmour
parents:
diff changeset
691 /* I2C */
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jlarmour
parents:
diff changeset
692 volatile unsigned char i2c_i2mod; /* i2c mode */
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jlarmour
parents:
diff changeset
693 unsigned char RSRVD59[3];
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jlarmour
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diff changeset
694 volatile unsigned char i2c_i2add; /* i2c address */
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jlarmour
parents:
diff changeset
695 unsigned char RSRVD60[3];
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diff changeset
696 volatile unsigned char i2c_i2brg; /* i2c brg */
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parents:
diff changeset
697 unsigned char RSRVD61[3];
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jlarmour
parents:
diff changeset
698 volatile unsigned char i2c_i2com; /* i2c command */
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jlarmour
parents:
diff changeset
699 unsigned char RSRVD62[3];
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jlarmour
parents:
diff changeset
700 volatile unsigned char i2c_i2cer; /* i2c event */
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jlarmour
parents:
diff changeset
701 unsigned char RSRVD63[3];
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jlarmour
parents:
diff changeset
702 volatile unsigned char i2c_i2cmr; /* i2c mask */
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jlarmour
parents:
diff changeset
703 volatile unsigned char RSRVD10[0x8b];
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jlarmour
parents:
diff changeset
704
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jlarmour
parents:
diff changeset
705 /* DMA */
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jlarmour
parents:
diff changeset
706 volatile unsigned char RSRVD11[0x4];
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jlarmour
parents:
diff changeset
707 volatile unsigned long dma_sdar; /* SDMA address reg */
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jlarmour
parents:
diff changeset
708 volatile unsigned char dma_sdsr; /* SDMA status reg */
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jlarmour
parents:
diff changeset
709 volatile unsigned char RSRVD12[0x3];
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jlarmour
parents:
diff changeset
710 volatile unsigned char dma_sdmr; /* SDMA mask reg */
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jlarmour
parents:
diff changeset
711 volatile unsigned char RSRVD13[0x3];
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jlarmour
parents:
diff changeset
712 volatile unsigned char dma_idsr1; /* IDMA1 status reg */
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jlarmour
parents:
diff changeset
713 volatile unsigned char RSRVD14[0x3];
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jlarmour
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diff changeset
714 volatile unsigned char dma_idmr1; /* IDMA1 mask reg */
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jlarmour
parents:
diff changeset
715 volatile unsigned char RSRVD15[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
716 volatile unsigned char dma_idsr2; /* IDMA2 status reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
717 volatile unsigned char RSRVD16[0x3];
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
718 volatile unsigned char dma_idmr2; /* IDMA2 mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
719 volatile unsigned char RSRVD17[0x13];
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jlarmour
parents:
diff changeset
720
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
721 /* CPM Interrupt Controller */
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jlarmour
parents:
diff changeset
722 volatile unsigned short cpmi_civr; /* CP interrupt vector reg */
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jlarmour
parents:
diff changeset
723 volatile unsigned char RSRVD19[0xe];
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jlarmour
parents:
diff changeset
724 volatile unsigned long cpmi_cicr; /* CP interrupt configuration reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
725 volatile unsigned long cpmi_cipr; /* CP interrupt pending reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
726 volatile unsigned long cpmi_cimr; /* CP interrupt mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
727 volatile unsigned long cpmi_cisr; /* CP interrupt in-service reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
728
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
729 /* I/O port */
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jlarmour
parents:
diff changeset
730 volatile unsigned short pio_padir; /* port A data direction reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
731 volatile unsigned short pio_papar; /* port A pin assignment reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
732 volatile unsigned short pio_paodr; /* port A open drain reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
733 volatile unsigned short pio_padat; /* port A data register */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
734 volatile unsigned char RSRVD20[0x8];
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jlarmour
parents:
diff changeset
735 volatile unsigned short pio_pcdir; /* port C data direction reg */
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jlarmour
parents:
diff changeset
736 volatile unsigned short pio_pcpar; /* port C pin assignment reg */
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jlarmour
parents:
diff changeset
737 volatile unsigned short pio_pcso; /* port C special options */
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jlarmour
parents:
diff changeset
738 volatile unsigned short pio_pcdat; /* port C data register */
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jlarmour
parents:
diff changeset
739 volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */
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jlarmour
parents:
diff changeset
740 unsigned char RSRVD64[6];
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jlarmour
parents:
diff changeset
741 volatile unsigned short pio_pddir; /* port D Data Direction reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
742 volatile unsigned short pio_pdpar; /* port D pin assignment reg */
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jlarmour
parents:
diff changeset
743 unsigned char RSRVD65[2];
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jlarmour
parents:
diff changeset
744 volatile unsigned short pio_pddat; /* port D data reg */
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jlarmour
parents:
diff changeset
745 volatile unsigned char RSRVD21[0x8];
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jlarmour
parents:
diff changeset
746
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jlarmour
parents:
diff changeset
747 /* CPM Timer */
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jlarmour
parents:
diff changeset
748 volatile unsigned short timer_tgcr; /* timer global configuration reg */
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jlarmour
parents:
diff changeset
749 volatile unsigned char RSRVD22[0xe];
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jlarmour
parents:
diff changeset
750 volatile unsigned short timer_tmr1; /* timer 1 mode reg */
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jlarmour
parents:
diff changeset
751 volatile unsigned short timer_tmr2; /* timer 2 mode reg */
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jlarmour
parents:
diff changeset
752 volatile unsigned short timer_trr1; /* timer 1 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
753 volatile unsigned short timer_trr2; /* timer 2 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
754 volatile unsigned short timer_tcr1; /* timer 1 capture reg */
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jlarmour
parents:
diff changeset
755 volatile unsigned short timer_tcr2; /* timer 2 capture reg */
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jlarmour
parents:
diff changeset
756 volatile unsigned short timer_tcn1; /* timer 1 counter reg */
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jlarmour
parents:
diff changeset
757 volatile unsigned short timer_tcn2; /* timer 2 counter reg */
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jlarmour
parents:
diff changeset
758 volatile unsigned short timer_tmr3; /* timer 3 mode reg */
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jlarmour
parents:
diff changeset
759 volatile unsigned short timer_tmr4; /* timer 4 mode reg */
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jlarmour
parents:
diff changeset
760 volatile unsigned short timer_trr3; /* timer 3 referance reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
761 volatile unsigned short timer_trr4; /* timer 4 referance reg */
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jlarmour
parents:
diff changeset
762 volatile unsigned short timer_tcr3; /* timer 3 capture reg */
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jlarmour
parents:
diff changeset
763 volatile unsigned short timer_tcr4; /* timer 4 capture reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
764 volatile unsigned short timer_tcn3; /* timer 3 counter reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
765 volatile unsigned short timer_tcn4; /* timer 4 counter reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
766 volatile unsigned short timer_ter1; /* timer 1 event reg */
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jlarmour
parents:
diff changeset
767 volatile unsigned short timer_ter2; /* timer 2 event reg */
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jlarmour
parents:
diff changeset
768 volatile unsigned short timer_ter3; /* timer 3 event reg */
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jlarmour
parents:
diff changeset
769 volatile unsigned short timer_ter4; /* timer 4 event reg */
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jlarmour
parents:
diff changeset
770 volatile unsigned char RSRVD23[0x8];
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jlarmour
parents:
diff changeset
771
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jlarmour
parents:
diff changeset
772 /* CP */
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jlarmour
parents:
diff changeset
773 volatile unsigned short cp_cr; /* command register */
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jlarmour
parents:
diff changeset
774 volatile unsigned char RSRVD24[0x2];
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jlarmour
parents:
diff changeset
775 volatile unsigned short cp_rccr; /* main configuration reg */
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jlarmour
parents:
diff changeset
776 volatile unsigned char RSRVD25;
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jlarmour
parents:
diff changeset
777 volatile unsigned char cp_resv1; /* RSRVD reg */
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jlarmour
parents:
diff changeset
778 volatile unsigned long cp_resv2; /* RSRVD reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
779 volatile unsigned short cp_rctr1; /* ram break register 1 */
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jlarmour
parents:
diff changeset
780 volatile unsigned short cp_rctr2; /* ram break register 2 */
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jlarmour
parents:
diff changeset
781 volatile unsigned short cp_rctr3; /* ram break register 3 */
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jlarmour
parents:
diff changeset
782 volatile unsigned short cp_rctr4; /* ram break register 4 */
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jlarmour
parents:
diff changeset
783 volatile unsigned char RSRVD26[0x2];
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jlarmour
parents:
diff changeset
784 volatile unsigned short cp_rter; /* RISC timers event reg */
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jlarmour
parents:
diff changeset
785 volatile unsigned char RSRVD27[0x2];
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jlarmour
parents:
diff changeset
786 volatile unsigned short cp_rtmr; /* RISC timers mask reg */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
787 volatile unsigned char RSRVD28[0x14];
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jlarmour
parents:
diff changeset
788
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jlarmour
parents:
diff changeset
789 /* BRG */
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jlarmour
parents:
diff changeset
790 volatile unsigned long brgc1; /* BRG1 configuration reg */
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jlarmour
parents:
diff changeset
791 volatile unsigned long brgc2; /* BRG2 configuration reg */
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jlarmour
parents:
diff changeset
792 volatile unsigned long brgc3; /* BRG3 configuration reg */
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jlarmour
parents:
diff changeset
793 volatile unsigned long brgc4; /* BRG4 configuration reg */
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jlarmour
parents:
diff changeset
794
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jlarmour
parents:
diff changeset
795 /* SCC registers */
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jlarmour
parents:
diff changeset
796 struct scc_regs {
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jlarmour
parents:
diff changeset
797 volatile unsigned long scc_gsmr_l; /* SCC Gen mode (LOW) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
798 volatile unsigned long scc_gsmr_h; /* SCC Gen mode (HIGH) */
5af43b635655 Merge from eCos master repository on 1999-08-18-15:20:01-BST
jlarmour
parents:
diff changeset
799 volatile unsigned short scc_psmr; /* protocol specific mode register */
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jlarmour
parents:
diff changeset
800 volatile unsigned char RSRVD29[0x2];
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jlarmour
parents:
diff changeset
801 volatile unsigned short scc_todr; /* SCC transmit on demand */
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jlarmour
parents:
diff changeset
802 volatile unsigned short scc_dsr; /* SCC data sync reg */
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jlarmour
parents:
diff changeset
803 volatile unsigned short scc_scce; /* SCC event reg */
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jlarmour
parents:
diff changeset
804 volatile unsigned char RSRVD30[0x2];
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jlarmour
parents:
diff changeset
805 volatile unsigned short scc_sccm; /* SCC mask reg */
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jlarmour
parents:
diff changeset
806 volatile unsigned char RSRVD31[0x1];
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jlarmour
parents:
diff changeset
807 volatile unsigned char scc_sccs; /* SCC status reg */
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jlarmour
parents:
diff changeset
808 volatile unsigned char RSRVD32[0x8];
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jlarmour
parents:
diff changeset
809 } scc_regs[2];
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jlarmour
parents:
diff changeset
810
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jlarmour
parents:
diff changeset
811 volatile unsigned char RSRVD120[0x40];
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jlarmour
parents:
diff changeset
812
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jlarmour
parents:
diff changeset
813 /* SMC */
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jlarmour
parents:
diff changeset
814 struct smc_regs {
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jlarmour
parents:
diff changeset
815 volatile unsigned char RSRVD34[0x2];
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jlarmour
parents:
diff changeset
816 volatile unsigned short smc_smcmr; /* SMC mode reg */
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jlarmour
parents:
diff changeset
817 volatile unsigned char RSRVD35[0x2];
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jlarmour
parents:
diff changeset
818 volatile unsigned char smc_smce; /* SMC event reg */
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jlarmour
parents:
diff changeset
819 volatile unsigned char RSRVD36[0x3];
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jlarmour
parents:
diff changeset
820 volatile unsigned char smc_smcm; /* SMC mask reg */
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jlarmour
parents:
diff changeset
821 volatile unsigned char RSRVD37[0x5];
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jlarmour
parents:
diff changeset
822 } smc_regs[2];
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jlarmour
parents:
diff changeset
823
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jlarmour
parents:
diff changeset
824 /* SPI */
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jlarmour
parents:
diff changeset
825 volatile unsigned short spi_spmode; /* SPI mode reg */
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jlarmour
parents:
diff changeset
826 volatile unsigned char RSRVD38[0x4];
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jlarmour
parents:
diff changeset
827 volatile unsigned char spi_spie; /* SPI event reg */
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jlarmour
parents:
diff changeset
828 volatile unsigned char RSRVD39[0x3];
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jlarmour
parents:
diff changeset
829 volatile unsigned char spi_spim; /* SPI mask reg */
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jlarmour
parents:
diff changeset
830 volatile unsigned char RSRVD40[0x2];
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jlarmour
parents:
diff changeset
831 volatile unsigned char spi_spcom; /* SPI command reg */
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jlarmour
parents:
diff changeset
832 volatile unsigned char RSRVD41[0x4];
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jlarmour
parents:
diff changeset
833
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jlarmour
parents:
diff changeset
834 /* PIP */
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jlarmour
parents:
diff changeset
835 volatile unsigned short pip_pipc; /* pip configuration reg */
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jlarmour
parents:
diff changeset
836 volatile unsigned char RSRVD42[0x2];
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jlarmour
parents:
diff changeset
837 volatile unsigned short pip_ptpr; /* pip timing parameters reg */
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jlarmour
parents:
diff changeset
838 volatile unsigned long pip_pbdir; /* port b data direction reg */
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jlarmour
parents:
diff changeset
839 volatile unsigned long pip_pbpar; /* port b pin assignment reg */
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jlarmour
parents:
diff changeset
840 volatile unsigned char RSRVD43[0x2];
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jlarmour
parents:
diff changeset
841 volatile unsigned short pip_pbodr; /* port b open drain reg */
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jlarmour
parents:
diff changeset
842 volatile unsigned long pip_pbdat; /* port b data reg */
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jlarmour
parents:
diff changeset
843 volatile unsigned char RSRVD44[0x18];
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jlarmour
parents:
diff changeset
844
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jlarmour
parents:
diff changeset
845 /* Serial Interface */
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jlarmour
parents:
diff changeset
846 volatile unsigned long si_simode; /* SI mode register */
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jlarmour
parents:
diff changeset
847 volatile unsigned char si_sigmr; /* SI global mode register */
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jlarmour
parents:
diff changeset
848 volatile unsigned char RSRVD45;
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jlarmour
parents:
diff changeset
849 volatile unsigned char si_sistr; /* SI status register */
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jlarmour
parents:
diff changeset
850 volatile unsigned char si_sicmr; /* SI command register */
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jlarmour
parents:
diff changeset
851 volatile unsigned char RSRVD46[0x4];
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852 volatile unsigned long si_sicr; /* SI clock routing */
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853 volatile unsigned long si_sirp; /* SI ram pointers */
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854 volatile unsigned char RSRVD47[0x10c];
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855 volatile unsigned char si_siram[0x200];/* SI routing ram */
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856 volatile unsigned short lcd_lcolr[256]; /* LCD Color RAM -- REV A.x */
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857 volatile unsigned char RSRVD48[0x1000];
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858
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859 /* BASE + 0x2000: user data memory */
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860 volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/
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861 volatile unsigned char udata_bd[0x200]; /*user data Ucode*/
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862 volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram*/
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863 volatile unsigned char RSRVD49[0x1500];
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864
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865 /* BASE + 0x3c00: PARAMETER RAM */
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866 union {
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867 struct scc_pram {
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868 union {
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869 struct hdlc_pram h;
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870 struct uart_pram u;
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871 struct bisync_pram b;
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872 struct transparent_pram t;
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873 struct async_hdlc_pram a;
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874 unsigned char RSRVD50[0x80];
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875 } pscc; /* scc parameter area (protocol dependent) */
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876
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877 union {
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diff changeset
878 struct {
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diff changeset
879 struct i2c_pram i2c;
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diff changeset
880 unsigned char RSRVD56[0x18];
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881 struct idma_pram idma1;
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882 } i2c_idma;
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883 struct {
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884 struct spi_pram spi;
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885 unsigned char RSRVD57[0x8];
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886 struct timer_pram timer;
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887 struct idma_pram idma2;
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888 } spi_timer_idma;
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889 struct {
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890 union {
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891 struct smc_uart_pram u;
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892 struct smc_trnsp_pram t;
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diff changeset
893 struct centronics_pram c;
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894 } psmc;
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895 unsigned char modem_param[0x40];
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896 } smc_modem;
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897 struct {
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898 unsigned char RSRVD54[0x40];
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899 struct ucode_pram ucode;
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900 } pucode;
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901 } pothers;
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902 } scc;
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903 struct ethernet_pram enet_scc;
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904 unsigned char pr[0x100];
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905 } pram[4];
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906 } EPPC;
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907
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908
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909 static inline EPPC *eppc_base(void)
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910 {
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911 EPPC *retval;
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912
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913 asm volatile (
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914 "mfspr %0,638 \n\t"
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915 "andis. %0,%0,65535 \n\t"
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916 : "=r" (retval)
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917 : /* no inputs */ );
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918
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919 return retval;
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920 }
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921
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922
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923
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924 #endif /* __ASSEMBLER__ */
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925
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926 /* Memory Periodic Timer Prescaler Register values */
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927 #define PTP_DIV2 0x2000
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928 #define PTP_DIV4 0x1000
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929 #define PTP_DIV8 0x0800
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930 #define PTP_DIV16 0x0400
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931 #define PTP_DIV32 0x0200
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932 #define PTP_DIV64 0x0100
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933
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934
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935 #endif // ifndef CYGONCE_HAL_PPC_QUICC_PPC8XX_H