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annotate packages/io/pci/current/src/pci_hw.c @ 64:c38311975d4f ecos-sw-2000-01-28

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Merge from eCos master repository on 2000-01-28-04:28:11-GMT
author jlarmour
date Fri, 28 Jan 2000 04:59:39 +0000
parents 7b011d1ab50f
children bf00f99aec69
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1 //=============================================================================
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2 //
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3 // pci_hw.c
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4 //
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5 // PCI hardware library
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6 //
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7 //=============================================================================
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8 //####COPYRIGHTBEGIN####
64
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.0 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://sourceware.cygnus.com/ecos
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15 //
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16 // Software distributed under the License is distributed on an
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
52
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30 //####COPYRIGHTEND####
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31 //=============================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): jskov, from design by nickg
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35 // Contributors: jskov
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36 // Date: 1999-08-09
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37 // Purpose: PCI hardware configuration access
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38 // Description:
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //=============================================================================
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43
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44 #include <cyg/io/pci_hw.h>
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45
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46 // CYG_PCI_PRESENT only gets defined for targets that provide PCI HAL support.
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47 // See pci_hw.h for details.
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48 #ifdef CYG_PCI_PRESENT
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49
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50 // Init
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51 void
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52 cyg_pcihw_init(void)
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53 {
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54 HAL_PCI_INIT();
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55 }
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56
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57 // Read functions
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58 void
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59 cyg_pcihw_read_config_uint8( cyg_uint8 bus, cyg_uint8 devfn,
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60 cyg_uint8 offset, cyg_uint8 *val)
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61 {
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62 HAL_PCI_CFG_READ_UINT8(bus, devfn, offset, *val);
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63 }
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64
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65 void
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66 cyg_pcihw_read_config_uint16( cyg_uint8 bus, cyg_uint8 devfn,
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67 cyg_uint8 offset, cyg_uint16 *val)
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68 {
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69 HAL_PCI_CFG_READ_UINT16(bus, devfn, offset, *val);
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70 }
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71
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72 void
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73 cyg_pcihw_read_config_uint32( cyg_uint8 bus, cyg_uint8 devfn,
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74 cyg_uint8 offset, cyg_uint32 *val)
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75 {
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76 HAL_PCI_CFG_READ_UINT32(bus, devfn, offset, *val);
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77 }
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78
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79 // Write functions
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80 void
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81 cyg_pcihw_write_config_uint8( cyg_uint8 bus, cyg_uint8 devfn,
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82 cyg_uint8 offset, cyg_uint8 val)
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83 {
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84 HAL_PCI_CFG_WRITE_UINT8(bus, devfn, offset, val);
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85 }
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86
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87 void
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88 cyg_pcihw_write_config_uint16( cyg_uint8 bus, cyg_uint8 devfn,
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89 cyg_uint8 offset, cyg_uint16 val)
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90 {
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91 HAL_PCI_CFG_WRITE_UINT16(bus, devfn, offset, val);
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92 }
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93
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94 void
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95 cyg_pcihw_write_config_uint32( cyg_uint8 bus, cyg_uint8 devfn,
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96 cyg_uint8 offset, cyg_uint32 val)
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97 {
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98 HAL_PCI_CFG_WRITE_UINT32(bus, devfn, offset, val);
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99 }
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100
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101 // Interrupt translation
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102 cyg_bool
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103 cyg_pcihw_translate_interrupt( cyg_uint8 bus, cyg_uint8 devfn,
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104 CYG_ADDRWORD *vec)
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105 {
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106 cyg_bool valid;
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107
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108 HAL_PCI_TRANSLATE_INTERRUPT(bus, devfn, *vec, valid);
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109
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110 return valid;
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111 }
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112
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113 #endif // ifdef CYG_PCI_PRESENT
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114
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115 //-----------------------------------------------------------------------------
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116 // end of pci_hw.c