Mercurial > ecos
annotate packages/devs/spi/freescale/dspi/current/include/spi_freescale_dspi.h @ 3166:c7cb4340f6eb
Add: support for 32 channel eDMA, support for cached memory.
| author | vae |
|---|---|
| date | Wed, 09 May 2012 22:07:24 +0000 |
| parents | a18d3fded36e |
| children | 99686efcd5ba |
| rev | line source |
|---|---|
| 3081 | 1 #ifndef CYGONCE_DEVS_SPI_FREESCALE_DSPI_H |
| 2 #define CYGONCE_DEVS_SPI_FREESCALE_DSPI_H | |
| 3 //============================================================================= | |
| 4 // | |
| 5 // spi_freescale_dspi.h | |
| 6 // | |
| 7 // Header definitions for Freescale DSPI driver. | |
| 8 // | |
| 9 //============================================================================= | |
| 10 // ####ECOSGPLCOPYRIGHTBEGIN#### | |
| 11 // ------------------------------------------- | |
| 12 // This file is part of eCos, the Embedded Configurable Operating System. | |
| 13 // Copyright (C) 2011 Free Software Foundation, Inc. | |
| 14 // | |
| 15 // eCos is free software; you can redistribute it and/or modify it under | |
| 16 // the terms of the GNU General Public License as published by the Free | |
| 17 // Software Foundation; either version 2 or (at your option) any later | |
| 18 // version. | |
| 19 // | |
| 20 // eCos is distributed in the hope that it will be useful, but WITHOUT | |
| 21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 23 // for more details. | |
| 24 // | |
| 25 // You should have received a copy of the GNU General Public License | |
| 26 // along with eCos; if not, write to the Free Software Foundation, Inc., | |
| 27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
| 28 // | |
| 29 // As a special exception, if other files instantiate templates or use | |
| 30 // macros or inline functions from this file, or you compile this file | |
| 31 // and link it with other works to produce a work based on this file, | |
| 32 // this file does not by itself cause the resulting work to be covered by | |
| 33 // the GNU General Public License. However the source code for this file | |
| 34 // must still be made available in accordance with section (3) of the GNU | |
| 35 // General Public License v2. | |
| 36 // | |
| 37 // This exception does not invalidate any other reasons why a work based | |
| 38 // on this file might be covered by the GNU General Public License. | |
| 39 // ------------------------------------------- | |
| 40 // ####ECOSGPLCOPYRIGHTEND#### | |
| 41 //============================================================================= | |
| 42 //#####DESCRIPTIONBEGIN#### | |
| 43 // | |
| 44 // Author(s): ilijak | |
| 45 // Date: 2011-11-03 | |
| 46 // Purpose: Freescale DSPI driver definitions. | |
| 47 // Description: | |
| 48 // Usage: #include <cyg/io/spi_freescale_dspi.h> | |
| 49 // | |
| 50 //####DESCRIPTIONEND#### | |
| 51 // | |
| 52 //============================================================================= | |
| 53 | |
| 54 #include <pkgconf/hal.h> | |
| 55 #include <pkgconf/io_spi.h> | |
| 56 #include <pkgconf/devs_spi_freescale_dspi.h> | |
| 57 #include <pkgconf/hal_freescale_edma.h> | |
| 58 | |
| 59 #include <cyg/infra/cyg_type.h> | |
| 60 #include <cyg/hal/drv_api.h> | |
| 61 #include <cyg/io/spi.h> | |
| 62 #include <cyg/hal/freescale_edma.h> | |
| 63 #include <cyg/io/spi_freescale_dspi_io.h> | |
| 64 | |
| 65 //----------------------------------------------------------------------------- | |
| 66 // Macro for defining a SPI device and attaching it to the appropriate bus. | |
| 67 // | |
| 68 // _name_ is the name of the SPI device. This will be used to reference a | |
| 69 // data structure of type cyg_spi_device which can be passed to the | |
| 70 // SPI driver API without needing a cast. | |
| 71 // _bus_ is the bus number to which this device is attached (0, 1 or 2). | |
| 72 // _csnum_ is the chip select line used for this device, numbered from 0. | |
| 73 // _fmsz_ is set device SPI frame size (bits) | |
| 74 // _clpol_ is the SPI bus clock polarity used by the device. This must be | |
| 75 // set to 1 if clock inactive state is high, 0 if clock inactive | |
| 76 // state is low. | |
| 77 // _clpha_ is the SPI bus clock phase used by the device. | |
| 78 // _brate_ is the SPI bus clock baud rate used by the device, measured in Hz. | |
| 79 // _csup_dly_ is the minimum delay between chip select assert and transfer | |
| 80 // start, measured in microseconds. | |
| 81 // _csdw_dly_ is the minimum delay between transfer end and chip select deassert, | |
| 82 // measured in delay units. | |
| 83 // _trbt_dly_ is the minimum delay between consecutive transfers. | |
| 84 // _dlu_ is delay unit in ns | |
| 85 // _dbr_ is enabling double baud rate feature | |
| 86 | |
| 87 | |
| 88 #define CYGNUM_DSPI_DELAY_UNIT(__val) (__val/10) | |
| 89 | |
| 90 #define CYG_SPI_BUS_NAME(_b_) cyg_spi_dspi_bus ## _b_ | |
| 91 | |
| 92 #define CYG_DEVS_SPI_FREESCALE_DSPI_DEVICE( \ | |
| 93 _name_, _bus_, _csnum_, _fmsz_, _clpol_, _clpha_, _brate_, _csup_dly_, _csdw_dly_, _trbt_dly_, _dlu_, _dbr_ \ | |
| 94 ) \ | |
| 95 cyg_spi_freescale_dspi_device_t _name_ ##_fs_dspi CYG_SPI_DEVICE_ON_BUS(_bus_) = { \ | |
| 96 { .spi_bus = (cyg_spi_bus*) &CYG_SPI_BUS_NAME(_bus_) }, \ | |
| 97 .dev_num = _csnum_, \ | |
| 98 .clocking.bus_16bit = _fmsz_ > 8 ? 1 : 0, \ | |
| 99 .clocking.frame_size = _fmsz_, \ | |
| 100 .clocking.cl_pol = _clpol_, \ | |
| 101 .clocking.cl_pha = _clpha_, \ | |
| 102 .clocking.cl_brate = _brate_, \ | |
| 103 .clocking.cs_up_udly = _csup_dly_, \ | |
| 104 .clocking.cs_dw_udly = _csdw_dly_, \ | |
| 105 .clocking.tr_bt_udly = _trbt_dly_, \ | |
| 106 .clocking.dl_unit = CYGNUM_DSPI_DELAY_UNIT(_dlu_), \ | |
| 107 .clocking.cl_dbr = _dbr_, \ | |
| 108 .clocking.dspi_ctar = 0 \ | |
| 109 }; \ | |
| 110 extern cyg_spi_device _name_ __attribute__((alias ( #_name_ "_fs_dspi" ))) | |
| 111 | |
| 112 enum { SPI_DMA_CHAN_TX_I, SPI_DMA_CHAN_RX_I }; | |
| 113 | |
| 114 //----------------------------------------------------------------------------- | |
| 115 // Freescale DSPI bus configuration and state. | |
| 116 | |
| 117 typedef struct cyg_spi_freescale_dspi_bus_setup_s | |
| 118 { | |
| 119 cyghwr_devs_freescale_dspi_t* dspi_p; // Base address of SPI register block. | |
|
3166
c7cb4340f6eb
Add: support for 32 channel eDMA, support for cached memory.
vae
parents:
3081
diff
changeset
|
120 cyghwr_hal_freescale_dma_set_t* dma_set_p; // DMA configuration block. |
| 3081 | 121 cyg_vector_t intr_num; // DSPI interrupt vector |
| 122 cyg_priority_t intr_prio; // Interrupt priority | |
| 123 cyg_uint32 mcr_opt ; // Module Configuratyon Register options | |
| 124 const cyg_uint32* spi_pin_list_p; // List of GPIOs used by the SPI interface. | |
| 125 const cyg_uint32* cs_pin_list_p; // List of GPIOs used as chip selects. | |
| 126 cyg_uint8 cs_pin_num; // Number of chip selects for this bus. | |
| 127 } cyg_spi_freescale_dspi_bus_setup_t; | |
| 128 | |
| 129 #define SPI_DMA_CHAN_I(__dma_set,__rt) (__dma_set->chan_p[SPI_DMA_CHAN_ ## __rt ## _I].dma_chan_i) | |
| 130 | |
| 131 typedef struct cyg_spi_freescale_dspi_bus_s | |
| 132 { | |
| 133 // ---- Upper layer data ---- | |
| 134 cyg_spi_bus spi_bus; // Upper layer SPI bus data. | |
| 135 | |
| 136 // ---- Bus configuration constants ---- | |
| 137 const cyg_spi_freescale_dspi_bus_setup_t* setup_p; | |
| 138 // ---- Driver state (private) ---- | |
| 139 // DMA transfer control descriptors | |
| 140 const cyghwr_hal_freescale_edma_tcd_t* tx_dma_tcd_ini_p; // TCD init. | |
| 141 const cyghwr_hal_freescale_edma_tcd_t* rx_dma_tcd_ini_p; // data | |
| 142 volatile cyghwr_hal_freescale_edma_tcd_t* rx_dma_tcd_p; // DMA TCD (RX) | |
| 143 volatile cyghwr_hal_freescale_edma_tcd_t* tx_dma_tcd_p; // DMA TCD (TX) | |
| 144 volatile cyg_uint32* pushque_p; // Tx command queue | |
| 145 cyg_uint16 pushque_n; // Tx command buffer size | |
| 146 cyg_uint8 txfifo_n; // TxFIFO size | |
| 147 cyg_uint8 rxfifo_n; // RxFIFO size | |
| 148 cyg_interrupt intr_data; // Interrupt state | |
| 149 cyg_handle_t intr_handle; // Interrupt handle | |
| 150 cyg_drv_mutex_t transfer_mutex; // Transfer mutex. | |
| 151 cyg_drv_cond_t transfer_done; // Transfer condition variable. | |
| 152 cyg_uint32 clock_freq; // Clock provided by hal | |
| 153 } cyg_spi_freescale_dspi_bus_t; | |
| 154 | |
| 155 //----------------------------------------------------------------------------- | |
| 156 // Freescale DSPI device. | |
| 157 | |
| 158 typedef struct cyg_freescale_dspi_clocking_s { | |
| 159 cyg_uint32 dspi_ctar; // DSPI Clock and Transfer Attributes Rregister shadow. | |
| 160 cyg_uint32 cl_brate; // Clock baud rate. | |
| 161 cyg_uint8 bus_16bit; // Use 16 bit (1) or 8 bit (0) transfers. | |
| 162 cyg_uint8 cl_pol; // Clock polarity (0 or 1). | |
| 163 cyg_uint8 cl_pha; // Clock phase (0 or 1). | |
| 164 cyg_uint8 cl_dbr; // Use double baud-rate feature if needed | |
| 165 cyg_uint8 cs_up_udly; // Minimum delay in us/ns between CS up and transfer start. | |
| 166 cyg_uint8 cs_dw_udly; // Minimum delay in us/ns between transfer end and CS down. | |
| 167 cyg_uint8 tr_bt_udly; // Minimum delay in us/ns between two transfers. | |
| 168 cyg_uint8 dl_unit; // Delay unit (1/10 * ns) | |
| 169 cyg_uint8 lsb_first; // LSbit shifted first. | |
| 170 cyg_uint8 frame_size; // Device SPI frame size (bits). | |
| 171 } cyg_freescale_dspi_clocking_t;; | |
| 172 | |
| 173 typedef struct cyg_spi_freescale_dspi_device_s | |
| 174 { | |
| 175 // ---- Upper layer data ---- | |
| 176 cyg_spi_device spi_device; // Upper layer SPI device data. | |
| 177 | |
| 178 // ---- Device setup (user configurable) ---- | |
| 179 cyg_freescale_dspi_clocking_t clocking; | |
| 180 cyg_uint8 dev_num; // Device SPI select. | |
| 181 cyg_uint8 chip_sel; | |
| 182 // ---- Device state (private) ---- | |
| 183 } cyg_spi_freescale_dspi_device_t; | |
| 184 | |
| 185 //----------------------------------------------------------------------------- | |
| 186 // Exported bus data structures. | |
| 187 | |
| 188 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI0 | |
| 189 externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus0; | |
| 190 #endif | |
| 191 | |
| 192 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI1 | |
| 193 externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus1; | |
| 194 #endif | |
| 195 | |
| 196 #ifdef CYGHWR_DEVS_SPI_FREESCALE_DSPI2 | |
| 197 externC cyg_spi_freescale_dspi_bus_t cyg_spi_dspi_bus2; | |
| 198 #endif | |
| 199 | |
| 200 __externC void cyghwr_devs_freescale_dspi_diag(cyg_spi_freescale_dspi_bus_t* spi_bus_p); | |
| 201 __externC void cyghwr_devs_freescale_dspi_diag_array(char* name_p, | |
| 202 volatile cyg_uint32* fifo_p, | |
| 203 cyg_uint32 fifo_n); | |
| 204 | |
| 205 //============================================================================= | |
| 206 #endif // CYGONCE_DEVS_SPI_FREESCALE_DSPI_H |