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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children 74dbf4c3f2e1
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1 #ifndef CYGONCE_HAL_CACHE_H
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2 #define CYGONCE_HAL_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // hal_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg, gthomas
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47 // Contributors: nickg, gthomas
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48 // Date: 1998-09-28
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <cyg/infra/cyg_type.h>
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62 #include <cyg/hal/hal_mmu.h>
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63
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64 //-----------------------------------------------------------------------------
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65 // FIXME: This definition forces the IO flash driver to use a
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66 // known-good procedure for fiddling flash before calling flash device
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67 // driver functions. The procedure breaks on other platform/driver
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68 // combinations though so is depricated. Hence this definition.
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69 //
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70 // If you work on this target, please try to remove this definition
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71 // and verify that the flash driver still works (both from RAM and
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72 // flash). If it does, remove the definition and this comment for good
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73 // [and the old macro definition if this happens to be the last client
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74 // of that code].
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75 #define HAL_FLASH_CACHES_OLD_MACROS
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76
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77 //-----------------------------------------------------------------------------
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78 // Cache dimensions
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79
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80 #define HAL_UCACHE_SIZE 0x2000 // Size of data cache in bytes
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81 #define HAL_UCACHE_LINE_SIZE 16 // Size of a data cache line
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82 #define HAL_UCACHE_WAYS 4 // Associativity of the cache
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83 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
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84
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85 #define HAL_CACHE_UNIFIED // Let programs know the caches are combined
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86
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87 //-----------------------------------------------------------------------------
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88 // Global control of caches
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89
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90 // Note: the 'mrc' doesn't seem to work.
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91 #if 0
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92 // Enable the data cache
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93 // mrc MMU_CP,0,r1,MMU_Control,c0
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94 // orr r1,r1,#MMU_Control_C|MMU_Control_B
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95 // mcr MMU_CP,0,r1,MMU_Control,c0
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96
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97 #define HAL_UCACHE_ENABLE() \
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98 { \
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99 asm volatile ("mrc p15,0,r1,c1,c0;" \
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100 "orr r1,r1,#0x000C;" \
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101 "mcr p15,0,r1,c1,c0;" \
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102 : \
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103 : \
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104 : "r1" /* Clobber list */ \
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105 ); \
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106 \
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107 }
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108
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109 // Disable the data cache
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110 #define HAL_UCACHE_DISABLE() \
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111 { \
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112 asm volatile ("mrc p15,0,r1,c1,c0;" \
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113 "bic r1,r1,#0x000C;" \
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114 "mcr p15,0,r1,c1,c0;" \
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115 : \
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116 : \
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117 : "r1" /* Clobber list */ \
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118 ); \
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119 \
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120 }
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121 #else
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122 #define HAL_UCACHE_ENABLE() \
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123 { \
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124 asm volatile ("mov r1,#0x7D;" \
143
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125 "mcr p15,0,r1,c1,c0,0;" \
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126 : \
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127 : \
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128 : "r1" /* Clobber list */ \
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129 ); \
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130 }
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131
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132 // Disable the data cache
143
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133 #define HAL_UCACHE_DISABLE() \
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134 { \
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135 asm volatile ("mov r1,#0x71;" \
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136 "mcr p15,0,r1,c1,c0,0;" \
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137 "mov r1,#0;" \
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138 "mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
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139 "nop; nop; nop; nop; nop;" \
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140 : \
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141 : \
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142 : "r1" /* Clobber list */ \
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143 ); \
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144 }
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145 #endif
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146
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147 // Is the cache turned on?
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148 #define HAL_UCACHE_IS_ENABLED(_state_) _state_ = 1;
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149
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150 // Invalidate the entire cache
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151 // mcr MMU_CP,0,r1,MMU_InvalidateCache,c0
143
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152 #define HAL_UCACHE_INVALIDATE_ALL() \
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153 { \
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154 asm volatile ( \
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155 "mov r1,#0;" \
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156 "mcr p15,0,r1,c7,c7,0;" \
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157 : \
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158 : \
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159 : "r1","memory" /* Clobber list */ \
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160 ); \
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161 \
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162 }
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163
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164 // Synchronize the contents of the cache with memory.
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165 #define HAL_UCACHE_SYNC() \
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166 { \
143
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167 cyg_uint32 *RAM = (cyg_uint32 *)0x00000000; \
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168 int i; \
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169 volatile cyg_uint32 val; \
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170 for (i = 0; i < HAL_UCACHE_SETS; i++) { \
143
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171 val = *RAM; \
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172 RAM += HAL_UCACHE_LINE_SIZE; \
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173 } \
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174 }
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175
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176 // Purge contents of data cache
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177 #define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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178
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179 // Set the data cache refill burst size
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180 //#define HAL_UCACHE_BURST_SIZE(_size_)
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181
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182 // Set the data cache write mode
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183 //#define HAL_UCACHE_WRITE_MODE( _mode_ )
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184
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185 //#define HAL_UCACHE_WRITETHRU_MODE 0
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186 //#define HAL_UCACHE_WRITEBACK_MODE 1
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187
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188 // Load the contents of the given address range into the data cache
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189 // and then lock the cache so that it stays there.
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190 //#define HAL_UCACHE_LOCK(_base_, _size_)
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191
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192 // Undo a previous lock operation
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193 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
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194
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195 // Unlock entire cache
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196 //#define HAL_UCACHE_UNLOCK_ALL()
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197
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198 //-----------------------------------------------------------------------------
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199 // Data cache line control
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200
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201 // Allocate cache lines for the given address range without reading its
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202 // contents from memory.
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203 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
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204
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205 // Write dirty cache lines to memory and invalidate the cache entries
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206 // for the given address range.
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207 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_SYNC()
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208
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209 // Invalidate cache lines in the given range without writing to memory.
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210 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
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211
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212 // Write dirty cache lines to memory for the given address range.
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213 #define HAL_UCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_SYNC()
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214
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215 // Preread the given range into the cache with the intention of reading
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216 // from it later.
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217 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
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218
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219 // Preread the given range into the cache with the intention of writing
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220 // to it later.
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221 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
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222
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223 // Allocate and zero the cache lines associated with the given range.
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224 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
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225
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226 //-----------------------------------------------------------------------------
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227 // Global control of data cache
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228
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229 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
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230 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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231 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
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232 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
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233
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234 // Enable the data cache
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235 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
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236
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237 // Disable the data cache
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238 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
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239
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240 // Invalidate the entire cache
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241 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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242
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243 // Synchronize the contents of the cache with memory.
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244 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
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245
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246 // Query the state of the data cache
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247 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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248
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249 // Set the data cache refill burst size
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250 //#define HAL_DCACHE_BURST_SIZE(_size_)
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251
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252 // Set the data cache write mode
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253 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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254
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255 //#define HAL_DCACHE_WRITETHRU_MODE 0
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256 //#define HAL_DCACHE_WRITEBACK_MODE 1
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257
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258 // Load the contents of the given address range into the data cache
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259 // and then lock the cache so that it stays there.
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260 //#define HAL_DCACHE_LOCK(_base_, _size_)
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261
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262 // Undo a previous lock operation
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263 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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264
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265 // Unlock entire cache
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266 //#define HAL_DCACHE_UNLOCK_ALL()
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267
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268 //-----------------------------------------------------------------------------
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269 // Data cache line control
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270
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271 // Allocate cache lines for the given address range without reading its
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272 // contents from memory.
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273 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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274
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275 // Write dirty cache lines to memory and invalidate the cache entries
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276 // for the given address range.
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277 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_ , _size_ )
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278
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279 // Invalidate cache lines in the given range without writing to memory.
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280 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
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281
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282 // Write dirty cache lines to memory for the given address range.
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283 #define HAL_DCACHE_STORE( _base_ , _size_ ) HAL_UCACHE_STORE( _base_ , _size_ )
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284
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285 // Preread the given range into the cache with the intention of reading
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286 // from it later.
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287 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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288
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289 // Preread the given range into the cache with the intention of writing
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290 // to it later.
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291 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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292
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293 // Allocate and zero the cache lines associated with the given range.
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294 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
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295
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296 //-----------------------------------------------------------------------------
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297 // Global control of Instruction cache - use Data cache controls since they
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298 // are not separatable.
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299
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300 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
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301 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
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302 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
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303 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
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304
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305 // Enable the instruction cache
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306 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
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307
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308 // Disable the instruction cache
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309 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
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310
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311 // Is the cache turned on?
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312 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
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313
54
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314 // Invalidate the entire cache
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315 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
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316
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317 // Synchronize the contents of the cache with memory.
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318 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
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319
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320 // Set the instruction cache refill burst size
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321 //#define HAL_ICACHE_BURST_SIZE(_size_)
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322
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323 // Load the contents of the given address range into the instruction cache
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324 // and then lock the cache so that it stays there.
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325 //#define HAL_ICACHE_LOCK(_base_, _size_)
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326
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327 // Undo a previous lock operation
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328 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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329
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330 // Unlock entire cache
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331 //#define HAL_ICACHE_UNLOCK_ALL()
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332
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333 //-----------------------------------------------------------------------------
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334 // Instruction cache line control
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335
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336 // Invalidate cache lines in the given range without writing to memory.
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337 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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338
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339 //-----------------------------------------------------------------------------
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340 #endif // ifndef CYGONCE_HAL_CACHE_H
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341 // End of hal_cache.h