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annotate packages/hal/powerpc/viper/current/src/viper.S @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children dbca035cc56d
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1 ##=============================================================================
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2 ##
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3 ## viper.S
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4 ##
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5 ## VIPER board hardware setup
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6 ##
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7 ##=============================================================================
208
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8 #####ECOSGPLCOPYRIGHTBEGIN####
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9 ## -------------------------------------------
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10 ## This file is part of eCos, the Embedded Configurable Operating System.
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 ##
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13 ## eCos is free software; you can redistribute it and/or modify it under
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14 ## the terms of the GNU General Public License as published by the Free
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15 ## Software Foundation; either version 2 or (at your option) any later version.
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16 ##
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17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 ## for more details.
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21 ##
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22 ## You should have received a copy of the GNU General Public License along
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23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
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24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 ##
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26 ## As a special exception, if other files instantiate templates or use macros
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27 ## or inline functions from this file, or you compile this file and link it
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28 ## with other works to produce a work based on this file, this file does not
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29 ## by itself cause the resulting work to be covered by the GNU General Public
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30 ## License. However the source code for this file must still be made available
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31 ## in accordance with section (3) of the GNU General Public License.
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32 ##
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33 ## This exception does not invalidate any other reasons why a work based on
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34 ## this file might be covered by the GNU General Public License.
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35 ##
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36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 ## at http://sources.redhat.com/ecos/ecos-license/
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38 ## -------------------------------------------
208
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39 #####ECOSGPLCOPYRIGHTEND####
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40 ##=============================================================================
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41 #######DESCRIPTIONBEGIN####
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42 ##
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43 ## Author(s): hmt
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44 ## Contributors:hmt, gthomas
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45 ## Date: 1999-06-08
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46 ## Purpose: VIPER board hardware setup
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47 ## Description: This file contains any code needed to initialize the
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48 ## hardware on a VIPER PPC860 board.
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49 ##
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50 ######DESCRIPTIONEND####
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51 ##
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52 ##=============================================================================
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53
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54 #include <pkgconf/system.h>
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55 #include <pkgconf/hal.h>
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56 #include <pkgconf/hal_powerpc.h>
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57 #include <pkgconf/hal_powerpc_viper.h>
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58
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59 #include <cyg/hal/arch.inc> /* register symbols et al */
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60 #include <cyg/hal/ppc_regs.h> /* on-chip resource layout, special */
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61 /* registers, IMM layout... */
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62 #include <cyg/hal/quicc/ppc8xx.h> /* more of the same */
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63
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64 #------------------------------------------------------------------------------
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65 # this is controlled with one define for tidiness:
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66 # (and it is undefined by default)
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67
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68 //#define CYGPRI_RAM_START_PROGRAMS_UPMS
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69
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70 #if defined(CYG_HAL_STARTUP_ROM) \
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71 || defined(CYG_HAL_STARTUP_ROMRAM) \
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72 || defined(CYGPRI_RAM_START_PROGRAMS_UPMS)
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73 # define CYGPRI_DO_PROGRAM_UPMS
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74 #endif
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75
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76 /* The intention is that we only set up the UPMs in ROM start, be it actual
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77 * ROM application start or Stub ROMs that we built from the same sources.
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78 *
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79 * The alternative approach - in which we have reliability doubts - is to
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80 * program the UPMs with *old* timing data in StubROM start, then
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81 * *reprogram* them with *new* timing data in RAM start - and of course
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82 * program with *new* timing data in plain ROM application start.
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83 * (Re-programming from new to new timing data fails - hence the suspicion
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84 * of reprogramming _at_all_, hence this private configuration)
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85 *
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86 * With CYGPRI_RAM_START_PROGRAMS_UPMS left undefined, the former behaviour
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87 * - programming the UPMs exactly once - is obtained. Define it to get the
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88 * latter, untrusted behaviour.
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89 */
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90
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91 #------------------------------------------------------------------------------
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92
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93 // LED macro uses r23, r25: r4 left alone
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94 #define LED( x ) \
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95 lwi r25,0xFA100018; \
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96 lwi r23,(x); \
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97 stb r23,0(r25)
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98
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99 #------------------------------------------------------------------------------
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100
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101 FUNC_START( hal_hardware_init )
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102
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103 # Throughout this routine, r4 is the base address of the control
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104 # registers. r3 and r5 are scratch in general.
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105
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106 lwi r4,CYGARC_REG_IMM_BASE # base address of control registers
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107 mtspr CYGARC_REG_IMMR,r4
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108
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109 LED( 0 ) # turn all LEDs off
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110
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111 #define CACHE_UNLOCKALL 0x0a00
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112 #define CACHE_DISABLE 0x0400
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113 #define CACHE_INVALIDATEALL 0x0c00
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114 #define CACHE_ENABLE 0x0200
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115 #define CACHE_ENABLEBIT 0x8000
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116
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117 #define CACHE_FORCEWRITETHROUGH 0x0100
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118 #define CACHE_NOWRITETHROUGH 0x0300
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119 #define CACHE_CLEAR_LE_SWAP 0x0700
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120
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121 # DATA CACHE
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122 mfspr r3,CYGARC_REG_DC_CST /* clear error bits */
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123 lis r3,CACHE_UNLOCKALL
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124 sync
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125 mtspr CYGARC_REG_DC_CST,r3 /* unlock all lines */
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126
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127 lis r3,CACHE_INVALIDATEALL
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128 sync
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129 mtspr CYGARC_REG_DC_CST,r3 /* invalidate all lines */
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130
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131 lis r3,CACHE_DISABLE
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132 sync
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133 mtspr CYGARC_REG_DC_CST,r3 /* disable */
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134
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135 lis r3,CACHE_FORCEWRITETHROUGH
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136 sync
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137 mtspr CYGARC_REG_DC_CST,r3 /* set force-writethrough mode */
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138
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139 lis r3,CACHE_CLEAR_LE_SWAP
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140 sync
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141 mtspr CYGARC_REG_DC_CST,r3 /* clear little-endian swap mode */
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142 /* (dunno what this is, but it sounds like a bad thing) */
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143
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144 # INSTRUCTION CACHE (no writeback modes)
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145 mfspr r3,CYGARC_REG_IC_CST /* clear error bits */
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146 lis r3,CACHE_UNLOCKALL
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147 mtspr CYGARC_REG_IC_CST,r3 /* unlock all lines */
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148 isync
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149 lis r3,CACHE_INVALIDATEALL
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150 mtspr CYGARC_REG_IC_CST,r3 /* invalidate all lines */
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151 isync
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152 lis r3,CACHE_DISABLE
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153 mtspr CYGARC_REG_IC_CST,r3 /* disable */
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154 isync
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155
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156 sync
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157
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158 LED( 0x01 )
208
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159
159
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160 /*
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161 * SIU Initialization.
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162 */
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163 lwi r3,0x00610400
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164 stw r3,SIUMCR(r4)
208
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165
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166 #ifdef CYG_HAL_STARTUP_ROMRAM
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167 // Need to set the PC into the FLASH (ROM) before the address map changes
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168 lwi r3,10f
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169 lwi r5,0xFE000000
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170 or r3,r3,r5
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171 mtctr r3
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172 bctr
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173 10:
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174 #endif
159
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175
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176 /*
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177 * Enable bus monitor. Disable Watchdog timer.
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178 */
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179 lwi r3,0xffffff88
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180 stw r3,SYPCR(r4)
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181
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182 /*
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183 * Clear REFA & REFB. Enable but freeze timebase.
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184 */
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185 lwi r3,0x0000 // FIXME: should this be 0x0000 or 0x00C2
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186 sth r3,TBSCR(r4)
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187
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188 /*
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189 * Unlock some RTC registers (see section 5.11.2)
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190 */
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191 lwi r3,0x55ccaa33
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192 stw r3,RTCSCK(r4)
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193 stw r3,RTCK(r4)
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194 stw r3,RTSECK(r4)
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195 stw r3,RTCALK(r4)
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196
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197 /*
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198 * Clear SERC & ALR. RTC runs on freeze. Enable RTC.
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199 */
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200 li r3,0x0000 // FIXME: should this be 0x0000 or 0x00C3
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201 sth r3,RTCSC(r4)
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202
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203 /*
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204 * Clear periodic timer interrupt status.
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205 * Enable periodic timer and stop it on freeze.
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206 */
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207 li r3,0x0001 // FIXME: should this be 0x0001 or 0x0083
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208 sth r3,PISCR(r4)
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209
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210 LED( 0x02 )
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211 #ifdef CYGPRI_DO_PROGRAM_UPMS
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212 /*
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213 * Perform UPM programming by writing to its 64 RAM locations.
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214 * Note that UPM initialization must be done before the Bank Register
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215 * initialization. Otherwise, system may hang when writing to Bank
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216 * Registers in certain cases.
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217 */
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218 lis r5,__upmtbl_start@h
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219 ori r5,r5,__upmtbl_start@l
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220 lis r6,__upmtbl_end@h
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221 ori r6,r6,__upmtbl_end@l
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222 sub r7,r6,r5 /* size of table */
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223 srawi r7,r7,2 /* in words */
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224
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225 li r6,0x00000000 /* Command - OP=Write, UPMA, MAD=0 */
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226 1:
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227 lwz r3,0(r5) /* get data from table */
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228 stw r3,MDR(r4) /* store the data to MD register */
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229 stw r6,MCR(r4) /* issue command to MCR register */
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230 addi r5,r5,4 /* next entry in the table */
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231 addi r6,r6,1 /* next MAD address */
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232 cmpw r6,r7 /* done yet ? */
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233 blt 1b
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234 #endif // CYGPRI_DO_PROGRAM_UPMS
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235 LED( 0x12 )
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236
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237 /*
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238 * Set refresh timer prescaler to divide by 8.
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239 */
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240 li r3,PTP_DIV32
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241 sth r3,MPTPR(r4)
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242
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243 /*
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244 * See Table 15-16 MPC860 User's Manual.
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245 *
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246 // Set the value of Machine A Mode Register (MAMR) to $5E802114.
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247 // Field PTA (bits 0-7) = 94
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248 // Field PTAE (bit 8) = 1
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249 // Field AMA (bits 9-11) = 0
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250 // Field Reserved (bit 12) = 0
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251 // Field DSA (bits 13-14) = 0
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252 // Field Reserved (bit 15) = 0
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253 // Field G0CLA (bits 16-18) = 1
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254 // Field GPL_A4DIS (bit 19) = 0
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255 // Field RLFA (bits 20-23) = 1
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256 // Field WLFA (bits 24-27) = 1
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257 // Field TLFA (bits 28-31) = 4
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258 */
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259 lwi r3,0x5E802114
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260 stw r3,MAMR(r4)
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261 stw r3,MBMR(r4)
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262
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263 /*
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264 * Base Register initialization.
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265 */
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266
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267 /* BOOT ROM */
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268 lwi r3,0xFE000401 # 8-bit, GPCM
208
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269 lwi r5,0xFFF00774 # 7 wait states
159
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270 stw r3,BR0(r4)
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271 stw r5,OR0(r4)
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272
208
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273 /* Misc I/O, 16 bit port */
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274 lwi r3,0xFA100801
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275 lwi r5,0xFFFF8730
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276 stw r3,BR2(r4)
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277 stw r5,OR2(r4)
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278
159
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279 /* ONBOARD DRAM */
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280 lwi r3,0x00000081 # 32-bit, UPMA
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281 lwi r5,0xFF800E00
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282 stw r3,BR1(r4)
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283 stw r5,OR1(r4)
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284
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285 /* DRAM DIMM BANK1 */
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286 lwi r3,0x00000080 # 32-bit, UPMA, INVALID
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287 lwi r5,0xFFFF87FC
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288 stw r3,BR3(r4)
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289 stw r5,OR3(r4)
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290
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291 #if 0
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292 /* NVRAM */
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293 lwi r3,0xfa000401 # 8-bit, GPCM
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294 lwi r5,0xffe00930
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295 stw r3,BR4(r4)
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296 stw r5,OR4(r4)
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297
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298 /* PCI BRIDGE MEM/IO */
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299 lwi r3,0x80000001 # 32-bit, GPCM
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300 lwi r5,0xa0000108
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301 stw r3,BR5(r4)
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302 stw r5,OR5(r4)
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303
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304 /* PCI BRIDGE REGISTERS */
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305 lwi r3,0xfa210001 # 32-bit, GPCM
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306 lwi r5,0xffff0108
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307 stw r3,BR6(r4)
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308 stw r5,OR6(r4)
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309
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310 /* FLASH */
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311 lwi r3,0xfc000001 # 32-bit, GPCM
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312 lwi r5,0xff800940
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313 stw r3,BR7(r4)
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314 stw r5,OR7(r4)
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315 #endif
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316
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317 /*
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318 * SYSTEM CLOCK CONTROL REGISTER
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319 // Set the value of System Clock and Reset Control Register (SCCR) to $00400000.
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320 // Field Reserved (bit 0) = 0
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321 // Field COM (bits 1-2) = 0
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322 // Field Reserved (bits 3-5) = 0
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323 // Field TBS (bit 6) = 0
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324 // Field RTDIV (bit 7) = 0
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325 // Field RTSEL (bit 8) = 0
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326 // Field CRQEN (bit 9) = 1
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327 // Field PRQEN (bit 10) = 0
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328 // Field Reserved (bits 11-12) = 0
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329 // Field EBDF (bits 13-14) = 0
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330 // Field Reserved (bits 15-16) = 0
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331 // Field DFSYNC (bits 17-18) = 0
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332 // Field DFBRG (bits 19-20) = 0
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333 // Field DFNL (bits 21-23) = 0
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334 // Field DFNH (bits 24-26) = 0
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335 // Field Reserved (bits 27-31) = 0
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336 */
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337 lwi r3,0x00400000
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338 stw r3,SCCR(r4)
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339
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340 LED( 0x03 )
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341
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342 /*
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343 * PLL, LOW POWER, AND RESET CONTROL REGISTER
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344 // Set the value of PLL, Low Power and Reset Control Register (PLPRCR) to $00C04000.
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345 // Field MF (bits 0-11) = 12
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346 // Field Reserved (bits 12-15) = 0
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347 // Field SPLSS (bit 16) = 0
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348 // Field TEXPS (bit 17) = 1
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349 // Field Reserved (bit 18) = 0
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350 // Field TMIST (bit 19) = 0
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351 // Field Reserved (bit 20) = 0
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352 // Field CSRC (bit 21) = 0
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353 // Field LPM (bits 22-23) = 0
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354 // Field CSR (bit 24) = 0
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355 // Field LOLRE (bit 25) = 0
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356 // Field FIOPD (bit 26) = 0
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357 // Field Reserved (bits 27-31) = 0
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358 */
208
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359 /* MF (0:11) = 0x00C = 12 = (47MHz/3.6864MHz)-1 */
159
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360 lwi r3,0x00C04000
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361 stw r3,PLPRCR(r4)
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362
208
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363 LED(0xE0)
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364 lwi r3,0x10000
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365 mtctr r3
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366 10: nop
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367 bdnz 10b
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368 LED(0xE1)
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369
159
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370 /* SDRAM Initialization Sequence, UPMA, CS1 */
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371 li r3,0
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372 stw r3,MAR(r4)
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373
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374 lwi r3,0x80002115; /* run precharge from loc 21 (0x15) */
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375 stw r3,MCR(r4)
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376
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377 lwi r3,0x80002830; /* run refresh 8 times */
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378 stw r3,MCR(r4)
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379
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380 lwi r3,0x88; /* MR 88 for high range */
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381 stw r3,MAR(r4)
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382
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383 lwi r3,0x80002116; /* run MRS pattern from loc 22 (0x16) */
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384 stw r3,MCR(r4)
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385
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386 # mask interrupt sources in the SIU
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387 lis r2,0
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388 lwi r3,CYGARC_REG_IMM_SIMASK
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389 stw r2,0(r3)
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390
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391 # set the decrementer to maxint
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392 lwi r2,0
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393 not r2,r2
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394 mtdec r2
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395
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396 # and enable the timebase and decrementer to make sure
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397 li r2,1 # TBEnable and not TBFreeze
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398 lwi r3,CYGARC_REG_IMM_TBSCR
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399 sth r2,0(r3)
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400
208
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401 LED( 8 )
159
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402
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403 #ifdef CYG_HAL_STARTUP_ROM
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404 # move return address to where the ROM is
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405 mflr r3
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406 lwi r4,0x00FFFFFF // CAUTION!! Assumes only low 16M for ROM
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407 and r3,r3,r4
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408 oris r3,r3,CYGMEM_REGION_rom>>16
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409 mtlr r3
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410 #endif
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411
208
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412 #ifdef CYG_HAL_STARTUP_ROMRAM
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413 // Copy image from ROM to RAM
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414 LED(0x10)
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415 mflr r3
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416 lwi r4,0xFE000000
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417 lwi r5,0x01FFFFFF // ROM/FLASH base
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418 and r3,r3,r5 // segment relative
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419 lwi r6,_hal_hardware_init_done
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420 mtlr r6
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421 sub r6,r3,r6 // Absolute address
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422 add r6,r6,r4 // FLASH address
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423 lwi r7,0 // where to copy to
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424 lwi r8,__ram_data_end
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425 10: lwz r5,0(r6)
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426 stw r5,0(r7)
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427 addi r6,r6,4
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428 addi r7,r7,4
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429 cmplw r7,r8
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430 bne 10b
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431 LED(0x20)
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432 #endif
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433
159
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434 blr
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435 FUNC_END( hal_hardware_init )
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436
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437
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438 #ifdef CYGPRI_DO_PROGRAM_UPMS
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439 # -------------------------------------------------------------------------
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440 # this table initializes the User Programmable Machine (UPM) nastiness
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441 # in the QUICC to control DRAM timing.
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442
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443 __upmtbl_start:
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444 // single read (offset 0x00 in upm ram)
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445 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00
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446 .long 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04
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447 // burst read (offset 0x08 in upm ram)
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448 .long 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00
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449 .long 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44
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450 .long 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35
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451 .long 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35
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452 // single write (offset 0x18 in upm ram)
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453 .long 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47
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454 .long 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
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455 // burst write (offset 0x20 in upm ram)
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456 .long 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00
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457 .long 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04
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458 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
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459 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
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460 // refresh (offset 0x30 in upm ram)
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461 .long 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04
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462 .long 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04
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463 .long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
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464 // exception (offset 0x3C in upm ram)
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465 .long 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
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466 __upmtbl_end:
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467 #endif // CYGPRI_DO_PROGRAM_UPMS
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468
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469 FUNC_START(hal_viper_set_led)
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470 lwi r4,0xFA100018
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471 stb r3,0(r4)
208
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472 lwi r5,_hold_led
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473 stw r3,0(r5)
159
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474 blr
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475 FUNC_END(hal_viper_set_led)
208
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476 .data
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477 _hold_led:
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478 .long 0
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479 .text
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480
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481 FUNC_START(hal_viper_get_led)
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482 lwi r5,_hold_led
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483 lwz r3,0(r5)
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484 blr
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485 FUNC_END(hal_viper_get_led)
159
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486
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487 FUNC_START(hal_viper_flash_led)
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488 lwi r4,0xFA100018
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489 1:
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490 li r5,10
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491 stb r5,0(r4)
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492
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493 lis r5,10
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494 mtctr r5
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495 2:
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496 bdnz 2b
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497
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498 li r5,12
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499 stb r5,0(r4)
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500
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501 lis r5,10
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502 mtctr r5
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503 3:
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504 bdnz 3b
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505
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506 subi r3,r3,1
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507 cmpwi r3,0
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508 bge 1b
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509
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510 li r5,6
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511 stb r5,0(r4)
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512
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513 lis r5,20
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514 mtctr r5
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515 4:
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516 bdnz 4b
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517
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518 blr
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519 FUNC_END(hal_viper_flash_led)
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520
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521
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522 #------------------------------------------------------------------------------
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523 # end of viper.S