Mercurial > ecos
annotate packages/hal/arm/arch/current/src/vectors.S @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | ece80412419a |
| children | 01ce82f3e11a |
| rev | line source |
|---|---|
| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 // ####COPYRIGHTEND#### | |
| 29 // #======================================================================== | |
| 30 // ######DESCRIPTIONBEGIN#### | |
| 31 // # | |
| 32 // # Author(s): nickg, gthomas | |
| 33 // # Contributors: nickg, gthomas | |
| 34 // # Date: 1999-02-20 | |
| 35 // # Purpose: ARM exception vectors | |
| 36 // # Description: This file defines the code placed into the exception | |
| 37 // # vectors. It also contains the first level default VSRs | |
| 38 // # that save and restore state for both exceptions and | |
| 39 // # interrupts. | |
| 40 // # | |
| 41 // #####DESCRIPTIONEND#### | |
| 42 // # | |
| 43 // #======================================================================== | |
| 44 | |
| 45 #include <pkgconf/hal.h> | |
| 46 #include <pkgconf/hal_arm.h> | |
| 47 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 48 #include <pkgconf/kernel.h> | |
| 49 #else | |
| 50 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
|
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51 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 52 #endif |
| 53 #include <cyg/hal/hal_platform_setup.h> | |
| 54 | |
| 55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 56 // The CDL should enforce this | |
| 57 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 58 #endif | |
| 59 | |
| 60 #include "arm.inc" | |
| 61 | |
| 62 #define FUNC_START(name) \ | |
| 63 .globl _name; \ | |
| 64 _name: | |
| 65 | |
| 66 #define PTR(name) \ | |
| 67 .##name: .word name | |
| 68 | |
| 69 | |
| 70 .file "vectors.S" | |
| 71 | |
| 72 | |
| 73 //========================================================================== | |
| 74 // Hardware exception vectors. | |
| 75 // This entire section will be copied to location 0x0000 at startup time. | |
| 76 // | |
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77 .code 32 |
| 2 | 78 .section ".vectors","ax" |
| 79 .global __exception_handlers | |
| 80 __exception_handlers: | |
| 81 ldr pc,.reset_vector // 0x00 | |
| 82 ldr pc,.undefined_instruction // 0x04 | |
| 83 ldr pc,.software_interrupt // 0x08 start && software int | |
| 84 ldr pc,.abort_prefetch // 0x0C | |
| 85 ldr pc,.abort_data // 0x10 | |
| 86 .word 0 // unused | |
| 87 ldr pc,.IRQ // 0x18 | |
| 88 ldr pc,.FIQ // 0x1C | |
| 89 | |
| 90 // The layout of these pointers should match the vector table above since | |
| 91 // they are copied in pairs. | |
| 92 .global vectors | |
| 93 vectors: | |
| 94 PTR(reset_vector) | |
| 95 PTR(undefined_instruction) | |
| 96 PTR(software_interrupt) | |
| 97 PTR(abort_prefetch) | |
| 98 PTR(abort_data) | |
| 99 .word 0 | |
| 100 PTR(IRQ) | |
| 101 PTR(FIQ) | |
| 102 PTR(start) | |
| 103 | |
| 104 .text | |
| 105 // Startup code which will get the machine into supervisor mode | |
| 106 .global reset_vector | |
| 107 .type reset_vector,function | |
| 108 reset_vector: | |
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109 |
| 2 | 110 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 111 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 112 mrs r7,cpsr // move back to IRQ mode | |
| 113 and r7,r7,#CPSR_MODE_BITS | |
| 114 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 115 beq start | |
| 116 #endif | |
| 117 | |
| 118 PLATFORM_SETUP1 // Early stage platform initialization | |
| 119 // see <cyg/hal/hal_platform_setup.h> | |
| 120 | |
| 121 mov r0,#0 // move vectors | |
| 122 ldr r1,.__exception_handlers | |
| 123 ldr r2,[r1,#0x04] // undefined instruction | |
| 124 str r2,[r0,#0x04] | |
| 125 ldr r2,[r1,#0x24] | |
| 126 str r2,[r0,#0x24] | |
| 127 ldr r2,[r1,#0x08] // software interrupt | |
| 128 str r2,[r0,#0x08] | |
| 129 ldr r2,[r1,#0x40] | |
| 130 str r2,[r0,#0x28] | |
| 131 swi // switch to supervisor mode | |
| 132 | |
| 133 // ========================================================================= | |
| 134 // Real startup code. We jump here from the reset vector to set up the world. | |
| 135 .globl start | |
| 136 start: | |
| 137 | |
| 138 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 139 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 140 // If we get restarted, hang here to avoid corrupting memory | |
| 141 ldr r0,.init_flag | |
| 142 ldr r1,[r0] | |
| 143 1: cmp r1,#0 | |
| 144 bne 1b | |
| 145 ldr r1,init_done | |
| 146 str r1,[r0] | |
| 147 #endif | |
| 148 | |
| 149 // Reset software interrupt pointer | |
| 150 mov r0,#0 // move vectors | |
| 151 ldr r1,.__exception_handlers | |
| 152 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 153 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 154 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 155 beq 10f | |
| 156 #endif | |
| 157 ldr r2,[r1,#0x28] // software interrupt | |
| 158 str r2,[r0,#0x28] | |
| 159 10: | |
| 160 ldr r2,[r1,#0x18] // IRQ | |
| 161 str r2,[r0,#0x18] | |
| 162 ldr r2,[r1,#0x38] | |
| 163 str r2,[r0,#0x38] | |
| 164 ldr r2,[r1,#0x1C] // FIQ | |
| 165 str r2,[r0,#0x1C] | |
| 166 ldr r2,[r1,#0x3C] | |
| 167 str r2,[r0,#0x3C] | |
| 168 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 169 str r2,[r0,#0x0C] | |
| 170 ldr r2,[r1,#0x2C] | |
| 171 str r2,[r0,#0x2C] | |
| 172 ldr r2,[r1,#0x10] // abort (data) | |
| 173 str r2,[r0,#0x10] | |
| 174 ldr r2,[r1,#0x30] | |
| 175 str r2,[r0,#0x30] | |
| 176 | |
| 177 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) | |
| 178 // Relocate [copy] data from ROM to RAM | |
| 179 ldr r3,.__rom_data_start | |
| 180 ldr r4,.__ram_data_start | |
| 181 ldr r5,.__ram_data_end | |
| 182 cmp r4,r5 // jump if no data to move | |
| 183 beq 2f | |
| 184 sub r3,r3,#4 // loop adjustments | |
| 185 sub r4,r4,#4 | |
| 186 1: ldr r0,[r3,#4]! // copy info | |
| 187 str r0,[r4,#4]! | |
| 188 cmp r4,r5 | |
| 189 bne 1b | |
| 190 2: | |
| 191 #endif | |
| 192 | |
| 193 // initialize interrupt/exception environments | |
| 194 ldr sp,.__startup_stack | |
| 195 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 196 msr cpsr,r0 | |
| 197 ldr sp,.__exception_stack | |
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198 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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199 msr cpsr,r0 |
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200 ldr sp,.__exception_stack |
| 2 | 201 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 202 msr cpsr,r0 | |
| 203 ldr sp,.__exception_stack | |
| 204 | |
| 205 // initialize CPSR (machine state register) | |
| 206 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 207 msr cpsr,r0 | |
| 208 | |
| 209 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 210 msr spsr,r0 | |
| 211 | |
| 212 // initialize stack | |
| 213 ldr sp,.__startup_stack | |
| 214 | |
| 215 // clear BSS | |
| 216 ldr r1,.__bss_start | |
| 217 ldr r2,.__bss_end | |
| 218 mov r0,#0 | |
| 219 cmp r1,r2 | |
| 220 beq 2f | |
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221 1: str r0,[r1],#4 |
| 2 | 222 cmp r1,r2 |
| 223 bne 1b | |
| 224 2: | |
| 225 | |
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226 |
| 2 | 227 // Call platform specific hardware initialization |
| 228 bl hal_hardware_init | |
| 229 | |
| 230 // Run through static constructors | |
| 231 bl cyg_hal_invoke_constructors | |
| 232 | |
| 233 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 234 bl initialize_stub | |
| 235 #endif | |
| 236 | |
| 237 // This starts up the eCos kernel | |
| 238 bl cyg_start | |
| 239 _start_hang: | |
| 240 b _start_hang | |
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241 .code 32 |
| 2 | 242 |
| 243 init_done: | |
| 244 .long 0xDEADB00B | |
| 245 | |
| 246 // | |
| 247 // Exception handlers | |
| 248 // Assmumption: get here from a Supervisor context [mode] | |
| 249 // | |
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250 .code 32 |
| 2 | 251 undefined_instruction: |
| 252 ldr sp,.__undef_exception_stack // get good stack | |
| 253 sub lr,lr,#4 // PC at time of interrupt | |
| 254 stmfd sp!,{r0,fp,ip,lr} | |
| 255 mrs r0,spsr | |
| 256 stmfd sp!,{r0} | |
| 257 mov ip,sp // save SP which will vanish with | |
| 258 // mode switch | |
| 259 mrs r0,cpsr // switch to Supervisor Mode | |
| 260 bic r0,r0,#CPSR_MODE_BITS | |
| 261 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 262 msr cpsr,r0 // sp,lr are now old values | |
| 263 mov fp,sp | |
| 264 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 265 ldr sp,.__GDB_stack | |
| 266 cmp fp,sp // already on GDB stack? | |
| 267 bhi 10f | |
| 268 ldr r0,.__GDB_stack_base | |
| 269 cmp fp,r0 | |
| 270 bls 10f // no - switch to GDB stack | |
| 271 // (already in sp) | |
| 272 mov sp,fp // yes - no switch | |
| 273 10: | |
| 274 #endif | |
| 275 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 276 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 277 ldmfd ip,{r0-r4} // saved registers | |
| 278 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 279 str r1,[sp,#armreg_r0] // saved R0 | |
| 280 str r2,[sp,#armreg_fp] // saved FP | |
| 281 str r3,[sp,#armreg_ip] // saved IP | |
| 282 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 283 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 284 add r0,ip,#ARMREG_SIZE | |
| 285 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 286 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 287 mov r0,sp | |
| 288 bl undefined_instruction | |
| 289 #endif | |
| 290 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 291 b call_exception_handler | |
| 292 | |
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293 .code 32 |
| 2 | 294 software_interrupt: |
| 295 ldr sp,.__startup_stack // get good stack | |
| 296 sub lr,lr,#4 // PC at time of interrupt | |
| 297 stmfd sp!,{r0,ip,lr} | |
| 298 mrs r0,spsr | |
| 299 stmfd sp!,{r0} | |
| 300 mov ip,sp // save SP which will vanish with | |
| 301 // mode switch | |
| 302 mrs r0,cpsr // switch to Supervisor Mode | |
| 303 bic r0,r0,#CPSR_MODE_BITS | |
| 304 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 305 msr cpsr,r0 // sp,lr are now old values | |
| 306 mov ip,sp | |
| 307 ldr sp,.__startup_stack // get good stack | |
| 308 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 309 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 310 ldmfd ip,{r0-r3} // saved registers | |
| 311 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 312 str r1,[sp,#armreg_r0] // saved R0 | |
| 313 str r2,[sp,#armreg_ip] // saved IP | |
| 314 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 315 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 316 add r0,ip,#ARMREG_SIZE | |
| 317 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 318 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 319 mov r0,sp | |
| 320 bl software_interrupt | |
| 321 #endif | |
| 322 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 323 b call_exception_handler | |
| 324 | |
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325 .code 32 |
| 2 | 326 abort_prefetch: |
| 327 ldr sp,.__undef_exception_stack // get good stack | |
| 328 sub lr,lr,#4 // PC at time of interrupt | |
| 329 stmfd sp!,{r0,fp,ip,lr} | |
| 330 mrs r0,spsr | |
| 331 stmfd sp!,{r0} | |
| 332 mov ip,sp // save SP which will vanish with | |
| 333 // mode switch | |
| 334 mrs r0,cpsr // switch to Supervisor Mode | |
| 335 bic r0,r0,#CPSR_MODE_BITS | |
| 336 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 337 msr cpsr,r0 // sp,lr are now old values | |
| 338 mov fp,sp | |
| 339 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 340 ldr sp,.__GDB_stack | |
| 341 cmp fp,sp // already on GDB stack? | |
| 342 bhi 10f | |
| 343 ldr r0,.__GDB_stack_base | |
| 344 cmp fp,r0 | |
| 345 bls 10f // no - switch to GDB stack | |
| 346 // (already in sp) | |
| 347 mov sp,fp // yes - no switch | |
| 348 10: | |
| 349 #endif | |
| 350 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 351 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 352 ldmfd ip,{r0-r4} // saved registers | |
| 353 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 354 str r1,[sp,#armreg_r0] // saved R0 | |
| 355 str r2,[sp,#armreg_fp] // saved FP | |
| 356 str r3,[sp,#armreg_ip] // saved IP | |
| 357 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 358 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 359 add r0,ip,#ARMREG_SIZE | |
| 360 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 361 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 362 mov r0,sp | |
| 363 bl abort_prefetch | |
| 364 #endif | |
| 365 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 366 b call_exception_handler | |
| 367 | |
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368 .code 32 |
| 2 | 369 abort_data: |
| 370 ldr sp,.__undef_exception_stack // get good stack | |
| 371 sub lr,lr,#4 // PC at time of interrupt | |
| 372 stmfd sp!,{r0,fp,ip,lr} | |
| 373 mrs r0,spsr | |
| 374 stmfd sp!,{r0} | |
| 375 mov ip,sp // save SP which will vanish with | |
| 376 // mode switch | |
| 377 mrs r0,cpsr // switch to Supervisor Mode | |
| 378 bic r0,r0,#CPSR_MODE_BITS | |
| 379 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 380 msr cpsr,r0 // sp,lr are now old values | |
| 381 mov fp,sp | |
| 382 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 383 ldr sp,.__GDB_stack | |
| 384 cmp fp,sp // already on GDB stack? | |
| 385 bhi 10f | |
| 386 ldr r0,.__GDB_stack_base | |
| 387 cmp fp,r0 | |
| 388 bls 10f // no - switch to GDB stack | |
| 389 // (already in sp) | |
| 390 mov sp,fp // yes - no switch | |
| 391 10: | |
| 392 #endif | |
| 393 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 394 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 395 ldmfd ip,{r0-r4} // saved registers | |
| 396 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 397 str r1,[sp,#armreg_r0] // saved R0 | |
| 398 str r2,[sp,#armreg_fp] // saved FP | |
| 399 str r3,[sp,#armreg_ip] // saved IP | |
| 400 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 401 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 402 add r0,ip,#ARMREG_SIZE | |
| 403 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 404 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 405 mov r0,sp | |
| 406 bl abort_data | |
| 407 #endif | |
| 408 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 409 b call_exception_handler | |
| 410 | |
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411 .code 32 |
| 2 | 412 FIQ: |
| 413 ldr sp,.__startup_stack // get good stack | |
| 414 sub lr,lr,#4 // PC at time of interrupt | |
| 415 stmfd sp!,{r0,ip,lr} | |
| 416 mrs r0,spsr | |
| 417 stmfd sp!,{r0} | |
| 418 mov ip,sp // save SP which will vanish with | |
| 419 // mode switch | |
| 420 mrs r0,cpsr // switch to Supervisor Mode | |
| 421 bic r0,r0,#CPSR_MODE_BITS | |
| 422 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 423 msr cpsr,r0 // sp,lr are now old values | |
| 424 mov ip,sp | |
| 425 ldr sp,.__startup_stack // get good stack | |
| 426 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 427 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 428 ldmfd ip,{r0-r3} // saved registers | |
| 429 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 430 str r1,[sp,#armreg_r0] // saved R0 | |
| 431 str r2,[sp,#armreg_ip] // saved IP | |
| 432 str r3,[sp,#armreg_pc] // PC at time of interrupt | |
| 433 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 434 add r0,ip,#ARMREG_SIZE | |
| 435 str r0,[sp,#armreg_sp] // SP at time of interrupt | |
| 436 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 437 mov r0,sp | |
| 438 bl FIQ | |
| 439 #endif | |
| 440 mov v1,#CYGNUM_HAL_EXCEPTION_FIQ | |
| 441 b call_exception_handler | |
| 442 | |
| 443 // | |
| 444 // Dispatch an exception handler. | |
| 445 | |
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446 .code 32 |
| 2 | 447 call_exception_handler: |
| 448 str v1,[sp,#armreg_vector] | |
| 449 mov r0,sp | |
| 450 bl exception_handler | |
| 451 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 452 mov r0,sp | |
| 453 bl exception_handler_returned | |
| 454 #endif | |
| 455 | |
| 456 // Restore [interrupted] context | |
| 457 mov ip,sp // get stack pointer | |
| 458 | |
| 459 ldr lr,[ip,#armreg_lr] | |
| 460 ldr sp,[sp,#armreg_sp] | |
| 461 | |
| 462 mrs r0,cpsr // move back to IRQ mode | |
| 463 bic r0,r0,#CPSR_MODE_BITS | |
| 464 orr r0,r0,#CPSR_IRQ_MODE | |
| 465 msr cpsr,r0 | |
| 466 | |
| 467 mov sp,ip | |
| 468 ldr lr,[sp,#armreg_pc] | |
| 469 ldr r0,[sp,#armreg_cpsr] | |
| 470 ldr ip,[sp,#armreg_ip] | |
| 471 msr spsr,r0 | |
| 472 ldmfd sp,{r0-r10,fp} | |
| 473 | |
| 474 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 475 | |
| 476 // Handle device interrupts | |
| 477 // This is slightly more complicated than the other exception handlers because | |
| 478 // it needs to interface with the kernel (if present). | |
| 479 | |
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480 .code 32 |
| 2 | 481 IRQ: |
| 482 // Note: I use this exception stack while saving the context because | |
| 483 // the current SP does not seem to be always valid in this CPU mode. | |
| 484 ldr sp,.__exception_stack // get good stack | |
| 485 sub lr,lr,#4 // PC at time of interrupt | |
| 486 stmfd sp!,{r0,fp,ip,lr} | |
| 487 mrs r0,spsr | |
| 488 stmfd sp!,{r0} | |
| 489 mov ip,sp // save SP which will vanish with | |
| 490 // mode switch | |
| 491 mrs r0,cpsr // switch to Supervisor Mode | |
| 492 bic r0,r0,#CPSR_MODE_BITS | |
| 493 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 494 msr cpsr,r0 // sp,lr are now old values | |
| 495 mov fp,sp // save old SP | |
| 496 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 497 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 498 ldmfd ip,{r0-r4} // saved registers | |
| 499 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 500 str r1,[sp,#armreg_r0] // saved R0 | |
| 501 str r2,[sp,#armreg_fp] // saved FP | |
| 502 str r3,[sp,#armreg_ip] // saved IP | |
| 503 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 504 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 505 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 506 mov v6,sp // Save pointer to register frame | |
| 507 | |
| 508 // mov r0,sp | |
| 509 // bl _show_frame_in | |
| 510 | |
| 511 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 512 // Switch to interrupt stack | |
| 513 ldr r2,.irq_level // current number of nested interrupts | |
| 514 ldr r0,[r2] | |
| 515 add r1,r0,#1 | |
| 516 str r1,[r2] // if was zero, switch stacks | |
| 517 cmp r0,#0 | |
| 518 moveq r1,sp // save old stack pointer | |
| 519 ldreq sp,.__interrupt_stack | |
| 520 stmeqfd sp!,{r1} | |
| 521 10: | |
| 522 #endif | |
| 523 | |
| 524 // The entire CPU state is now stashed on the stack, | |
| 525 // increment the scheduler lock and handle the interrupt | |
| 526 | |
| 527 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 528 .extern cyg_scheduler_sched_lock | |
| 529 ldr r3,.cyg_scheduler_sched_lock | |
| 530 ldr r4,[r3] | |
| 531 add r4,r4,#1 | |
| 532 str r4,[r3] | |
| 533 #endif | |
| 534 | |
| 535 bl hal_IRQ_handler // determine interrupt source | |
| 536 mov v1,r0 // returned vector # | |
| 537 | |
| 538 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 539 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 540 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 541 mov r1,v1 // arg1 = vector | |
| 542 mov r2,#0 // arg2 = 0 | |
| 543 bl cyg_instrument // call instrument function | |
| 544 #endif | |
| 545 | |
| 546 mov r0,v1 // vector # | |
| 547 ldr r1,.hal_interrupt_data | |
| 548 ldr r1,[r1,v1,lsl #2] // handler data | |
| 549 ldr r2,.hal_interrupt_handlers | |
| 550 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
| 551 mov r2,v6 // register frame | |
| 552 | |
| 553 mov lr,pc // invoke handler (call indirect | |
| 554 mov pc,v3 // thru v3) | |
| 555 | |
| 556 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 557 // If we are returning from the last nested interrupt, move back | |
| 558 // to the thread stack. interrupt_end() must be called on the | |
| 559 // thread stack since it potentially causes a context switch. | |
| 560 ldr r2,.irq_level | |
| 561 ldr r3,[r2] | |
| 562 subs r1,r3,#1 | |
| 563 str r1,[r2] | |
| 564 ldreq sp,[sp] // This should be the saved stack pointer | |
| 565 #endif | |
| 566 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 567 // The return value from the handler (in r0) will indicate whether a | |
| 568 // DSR is to be posted. Pass this together with a pointer to the | |
| 569 // interrupt object we have just used to the interrupt tidy up routine. | |
| 570 | |
| 571 ldr r1,.hal_interrupt_objects | |
| 572 ldr r1,[r1,v1,lsl #2] | |
| 573 bl interrupt_end // post any bottom layer handler | |
| 574 // threads and call scheduler | |
| 575 #endif | |
| 576 | |
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577 |
| 2 | 578 // mov r0,sp |
| 579 // bl show_frame_out | |
| 580 | |
| 581 mov ip,sp // get stack pointer | |
| 582 | |
| 583 ldr lr,[ip,#armreg_lr] | |
| 584 ldr sp,[sp,#armreg_sp] | |
| 585 | |
| 586 mrs r0,cpsr // move back to IRQ mode | |
| 587 bic r0,r0,#CPSR_MODE_BITS | |
| 588 orr r0,r0,#CPSR_IRQ_MODE | |
| 589 msr cpsr,r0 | |
| 590 | |
| 591 mov sp,ip | |
| 592 ldr lr,[sp,#armreg_pc] | |
| 593 ldr r0,[sp,#armreg_cpsr] | |
| 594 ldr ip,[sp,#armreg_ip] | |
| 595 msr spsr,r0 | |
| 596 ldmfd sp,{r0-r10,fp} | |
| 597 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 598 | |
| 599 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 600 // Execute pending DSRs the interrupt stack | |
| 601 // Note: this can only be called from code running on a thread stack | |
| 602 .global hal_interrupt_stack_call_pending_DSRs | |
| 603 hal_interrupt_stack_call_pending_DSRs: | |
| 604 stmfd sp!,{r4,r5,lr} | |
| 605 // Disable interrupts | |
| 606 mrs r4,cpsr // disable IRQ's | |
| 607 orr r2,r4,#CPSR_IRQ_DISABLE | |
| 608 bic r5,r4,#CPSR_IRQ_DISABLE | |
| 609 msr cpsr,r2 | |
| 610 // Switch to interrupt stack | |
| 611 mov r3,sp // save old stack pointer | |
| 612 ldr sp,.__interrupt_stack | |
| 613 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 614 ldr r2,.irq_level // current number of nested interrupts | |
| 615 ldr r3,[r2] | |
| 616 add r3,r3,#1 // bump nesting level | |
| 617 str r3,[r2] | |
| 618 msr cpsr,r5 // enable interrupts | |
| 619 | |
| 620 bl cyg_interrupt_call_pending_DSRs | |
| 621 | |
| 622 // Disable interrupts | |
| 623 mrs r1,cpsr // disable IRQ's | |
| 624 orr r2,r1,#CPSR_IRQ_DISABLE | |
| 625 msr cpsr,r2 | |
| 626 | |
| 627 // Move back to the thread stack. | |
| 628 ldr r2,.irq_level | |
| 629 ldr r3,[r2] | |
| 630 sub r3,r3,#1 // decrement nesting level | |
| 631 str r3,[r2] | |
| 632 ldr sp,[sp] // This should be the saved stack pointer | |
| 633 msr cpsr,r4 // restore interrupts to original state | |
| 634 | |
| 635 ldmfd sp!,{r4,r5,pc} // return | |
| 636 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 637 | |
| 638 // Dummy functions | |
| 639 | |
| 640 .global __gccmain | |
| 641 __gccmain: | |
| 642 mov pc,lr | |
| 643 | |
| 644 .global _psr | |
| 645 _psr: | |
| 646 mrs r0,cpsr | |
| 647 mov pc,lr | |
| 648 | |
| 649 .global _sp | |
| 650 _sp: | |
| 651 mov r0,sp | |
| 652 mov pc,lr | |
| 653 | |
| 654 | |
| 655 // | |
| 656 // Pointers to various objects. | |
| 657 // | |
| 658 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 659 PTR(__GDB_stack_base) | |
| 660 PTR(__GDB_stack) | |
| 661 #endif | |
| 662 PTR(__startup_stack) | |
| 663 PTR(__exception_stack) | |
| 664 PTR(__undef_exception_stack) | |
| 665 PTR(__bss_start) | |
| 666 PTR(__bss_end) | |
| 667 PTR(_end) | |
| 668 PTR(__rom_data_start) | |
| 669 PTR(__ram_data_start) | |
| 670 PTR(__ram_data_end) | |
| 671 PTR(hal_interrupt_handlers) | |
| 672 PTR(hal_interrupt_data) | |
| 673 PTR(hal_interrupt_objects) | |
| 674 PTR(__exception_handlers) | |
| 675 PTR(init_flag) | |
| 676 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 677 PTR(cyg_scheduler_sched_lock) | |
| 678 #endif | |
| 679 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 680 PTR(irq_level) | |
| 681 PTR(__interrupt_stack) | |
| 682 #endif | |
| 683 | |
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684 // |
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685 // Identification - useful to find out when a system was configured |
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686 _eCos_id: |
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687 .asciz "eCos v1.2.1: " __DATE__ |
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688 |
| 2 | 689 |
| 690 // ------------------------------------------------------------------------- | |
| 691 // Interrupt vector tables. | |
| 692 // These tables contain the isr, data and object pointers used to deliver | |
| 693 // interrupts to user code. | |
| 694 | |
| 695 .data | |
| 696 | |
| 697 init_flag: | |
| 698 .long 0 | |
| 699 | |
| 700 .extern hal_default_isr | |
| 701 | |
| 702 .globl hal_vsr_table | |
| 703 hal_vsr_table: | |
| 704 .rept CYGNUM_HAL_VSR_COUNT | |
| 705 .long 0 // hal_default_isr | |
| 706 .endr | |
| 707 | |
| 708 .globl hal_interrupt_handlers | |
| 709 hal_interrupt_handlers: | |
| 710 .rept CYGNUM_HAL_ISR_COUNT | |
| 711 .long hal_default_isr | |
| 712 .endr | |
| 713 | |
| 714 .globl hal_interrupt_data | |
| 715 hal_interrupt_data: | |
| 716 .rept CYGNUM_HAL_ISR_COUNT | |
| 717 .long 0 | |
| 718 .endr | |
| 719 | |
| 720 .globl hal_interrupt_objects | |
| 721 hal_interrupt_objects: | |
| 722 .rept CYGNUM_HAL_ISR_COUNT | |
| 723 .long 0 | |
| 724 .endr | |
| 725 | |
| 726 // ------------------------------------------------------------------------- | |
| 727 // Temporary interrupt stack | |
| 728 | |
| 729 .section ".bss" | |
| 730 | |
| 731 // Small stacks, only used for saving information between CPU modes | |
| 732 __exception_stack_base: | |
| 733 .rept 32 | |
| 734 .long 0 | |
| 735 .endr | |
| 736 __exception_stack: | |
| 737 .rept 32 | |
| 738 .long 0 | |
| 739 .endr | |
| 740 __undef_exception_stack: | |
| 741 | |
| 742 // Runtime stack used during all interrupt processing | |
| 743 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 744 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 745 #endif | |
| 746 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 747 .balign 16 | |
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748 .global cyg_interrupt_stack_base |
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749 cyg_interrupt_stack_base: |
| 2 | 750 __interrupt_stack_base: |
| 751 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 752 .byte 0 | |
| 753 .endr | |
| 754 .balign 16 | |
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755 .global cyg_interrupt_stack |
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756 cyg_interrupt_stack: |
| 2 | 757 __interrupt_stack: |
| 758 irq_level: | |
| 759 .long 0 | |
| 760 #endif | |
| 761 | |
| 762 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 763 .balign 16 | |
| 764 __GDB_stack_base: | |
| 765 .rept 0x400 | |
| 766 .byte 0 | |
| 767 .endr | |
| 768 __GDB_stack: | |
| 769 #endif | |
| 770 .balign 16 | |
| 771 __startup_stack_base: | |
| 772 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 773 .rept 512 | |
| 774 #else | |
| 775 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 776 #endif | |
| 777 .byte 0 | |
| 778 .endr | |
| 779 .balign 16 | |
| 780 __startup_stack: | |
| 781 | |
| 782 // -------------------------------------------------------------------------- | |
| 783 // end of vectors.S |