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annotate packages/hal/arm/iq80310/current/include/hal_platform_setup.h @ 201:dd81b18e45fb

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Merge from eCos master repository on 2002-01-04-06:43:04-GMT
author jlarmour
date Fri, 04 Jan 2002 14:13:51 +0000
parents f62680ef1804
children 353a011b23b8
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1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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2 #define CYGONCE_HAL_PLATFORM_SETUP_H
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3
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4 /*=============================================================================
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5 //
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6 // hal_platform_setup.h
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7 //
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8 // Platform specific support for HAL (assembly code)
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9 //
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10 //=============================================================================
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11 //####COPYRIGHTBEGIN####
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12 //
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13 // -------------------------------------------
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14 // The contents of this file are subject to the Red Hat eCos Public License
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15 // Version 1.1 (the "License"); you may not use this file except in
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16 // compliance with the License. You may obtain a copy of the License at
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17 // http://www.redhat.com/
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18 //
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19 // Software distributed under the License is distributed on an "AS IS"
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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21 // License for the specific language governing rights and limitations under
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22 // the License.
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23 //
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24 // The Original Code is eCos - Embedded Configurable Operating System,
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25 // released September 30, 1998.
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26 //
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27 // The Initial Developer of the Original Code is Red Hat.
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28 // Portions created by Red Hat are
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29 // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.
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30 // All Rights Reserved.
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31 // -------------------------------------------
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32 //
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33 //####COPYRIGHTEND####
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34 //=============================================================================
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35 //#####DESCRIPTIONBEGIN####
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36 //
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37 // Author(s): msalter
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38 // Contributors:
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39 // Date: 2000-10-10
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40 // Purpose: Intel IQ80310 platform specific support routines
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41 // Description:
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42 // Usage: #include <cyg/hal/hal_platform_setup.h>
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43 //
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44 //####DESCRIPTIONEND####
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45 //
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46 //===========================================================================*/
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47
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48 #include <pkgconf/system.h> // System-wide configuration info
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49 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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50 #include <cyg/hal/hal_iq80310.h> // Platform specific hardware definitions
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51 #include <cyg/hal/hal_mmu.h> // MMU definitions
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52
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53 // Define macro used to diddle the LEDs during early initialization.
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54 // Can use r0+r1. Argument in \x.
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55 #define CYGHWR_LED_MACRO \
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56 b 667f ;\
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57 666: ;\
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58 .byte 0xc0, 0xf9, 0xa4, 0xb0 ;\
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59 .byte 0x99, 0x92, 0x82, 0xf8 ;\
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60 .byte 0x80, 0x90, 0x88, 0x83 ;\
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61 .byte 0xa7, 0xa1, 0x86, 0x8e ;\
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62 667: ;\
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63 ldr r0, =666b ;\
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64 add r0, r0, #\x ;\
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65 ldrb r1, [r0] ;\
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66 ldr r0, =DISPLAY_RIGHT ;\
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67 str r1, [r0]
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68
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69
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70 // The main useful output of this file is PLATFORM_SETUP1: it invokes lots
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71 // of other stuff (may depend on RAM or ROM start). The other stuff is
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72 // divided into further macros to make it easier to manage what's enabled
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73 // when.
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74
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75 #if defined(CYG_HAL_STARTUP_ROM)
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76 #define PLATFORM_SETUP1 _platform_setup1
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77 //#define CYGHWR_HAL_ARM_HAS_MMU
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78 #else
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79 #define PLATFORM_SETUP1
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80 #endif
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81
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82
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83 #define RAM_BASE 0xa0000000
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84 #define DRAM_SIZE (512*1024*1024) // max size of available SDRAM
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85 #define DCACHE_SIZE (32*1024) // size of the Dcache
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86 #define DCACHE_FLUSH_AREA (RAM_BASE+DRAM_SIZE) // NB: needs page table support
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87
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88 #define MMU_Control_BTB 0x800
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89
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90 // Reserved area for battery backup SDRAM memory test
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91 // This area is not zeroed out by initialization code
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92 #define SDRAM_BATTERY_TEST_BASE 0xA1FFFFF0 // base address of last 16 memory locations in a 32MB SDRAM
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93
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94
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95
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96 // Display 'lvalue:rvalue' on the hex display
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97 // lvalue and rvalue must be of the form 'DISPLAY_x'
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98 // where 'x' is a hex digit from 0-F.
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99 .macro HEX_DISPLAY reg0, reg1, lvalue, rvalue
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100 ldr \reg0, =DISPLAY_LEFT // display left digit
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101 ldr \reg1, =\lvalue
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102 str \reg1, [\reg0]
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103 ldr \reg0, =DISPLAY_RIGHT
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104 ldr \reg1, =\rvalue // display right digit
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105 str \reg1, [\reg0]
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106 .endm
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107
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108 // Trigger the logic analyzer by writing a particular
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109 // address, and triggering on that address.
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110 .macro TRIGGER_LA_ON_ADDRESS address, reg0, reg1
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111 mrc p15, 0, \reg0, c1, c0, 0 // read ARM control register
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112 // CPWAIT \reg0
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113 ldr \reg1, =\address
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114 str \reg0, [\reg1]
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115 .endm
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116
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117 // Delay a bit
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118 .macro DELAY_FOR cycles, reg0
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119 ldr \reg0, =\cycles
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120 subs \reg0, \reg0, #1
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121 subne pc, pc, #0xc
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122 .endm
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123
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124 // wait for coprocessor write complete
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125 .macro CPWAIT reg
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126 mrc p15,0,\reg,c2,c0,0
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127 mov \reg,\reg
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128 sub pc,pc,#4
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129 .endm
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130
182
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131 // Enable the BTB
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132 .macro BTB_INIT reg
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133 #ifdef CYGSEM_HAL_ARM_IQ80310_BTB
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134 mrc p15, 0, \reg, c1, c0, 0
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135 orr \reg, \reg, #MMU_Control_BTB
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136 mcr p15, 0, \reg, c1, c0, 0
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137 CPWAIT \reg
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138 #endif
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139 .endm
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140
152
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141 // form a first-level section entry
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142 .macro FL_SECTION_ENTRY base,x,ap,p,d,c,b
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143 .word (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) |\
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144 (\d << 5) | (\c << 3) | (\b << 2) | 2
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145 .endm
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146
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147 // form a first-level page table entry
177
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148 .macro FL_PT_ENTRY base,p,d
152
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149 // I wanted to use logical operations here, but since I am using symbols later
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150 // to fill in the parameters, I had to use addition to force the assembler to
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151 // do it right
177
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152 .word \base + (\p << 9) + (\d << 5) + 1
152
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153 .endm
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154
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155 // form a second level small page entry
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156 .macro SL_SMPAGE_ENTRY base,ap3,ap2,ap1,ap0,c,b
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157 .word (\base << 12) | (\ap3 << 10) | (\ap2 << 8) | (\ap1 << 6) |\
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158 (\ap0 << 4) | (\c << 3) | (\b << 2) | 2
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159 .endm
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160
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161 // form a second level extended small page entry
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162 .macro SL_XSMPAGE_ENTRY base,x,ap,c,b
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163 .word (\base << 12) | (\x << 6) | (\ap << 4) | (\c << 3) | (\b << 2) | 3
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164 .endm
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165
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166
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167 // start of platform setup
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168 .macro _platform_setup1
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169
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170 // This is where we wind up immediately after reset. On the IQ80310, we have
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171 // to jump around a hole in flash which runs from 0x00001000 - 0x0001fff.
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172 // The start of _platform_setup1 will be below 0x1000 and since we need to
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173 // align the mmu table on a 16k boundary, we just branch around the page
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174 // table which we will locate at FLASH_BASE+0x4000.
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175 b _real_platform_setup
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176
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177 .p2align 13
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178 // the following alignment creates the mmu table at address 0x4000.
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179 mmu_table:
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180
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181 // 1MB of FLASH with i80312 MMRs mapped in using 4K small pages so we can
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182 // set the access permission on flash and memory-mapped registers properly.
177
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183 FL_PT_ENTRY mmu_table_flashbase,0,0
152
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184
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185 // Remaining 7MB of FLASH
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186 // rw, cacheable, non-bufferable
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187 .set __base,1
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188 .rept 7
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189 FL_SECTION_ENTRY __base,0,3,0,0,1,0
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190 .set __base,__base+1
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191 .endr
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192
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193 // nothing interesting here (Address Translation)
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194 .rept 0xA00 - 0x8
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195 FL_SECTION_ENTRY __base,0,3,0,0,0,0
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196 .set __base,__base+1
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197 .endr
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198
177
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199 // up to 512MB ECC SDRAM mapped 1-to-1
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200 // first 1MB mapped in 4K chunks
152
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201 // x=c=b=1
177
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202 FL_PT_ENTRY mmu_table_rambase,1,0
152
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203 .set __base,__base+1
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204 .rept 0xC00 - 0xA01
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205 FL_SECTION_ENTRY __base,1,3,1,0,1,1
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206 .set __base,__base+1
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207 .endr
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208
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209 // Cache flush region.
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210 // Don't need physical memory, just a cached area.
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211 .rept 0xD00 - 0xC00
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212 FL_SECTION_ENTRY __base,0,3,0,0,1,1
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213 .set __base,__base+1
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214 .endr
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215
177
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216 // Alias for first 1MB of FLASH
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217 // rw, cacheable, non-bufferable
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218 FL_SECTION_ENTRY 0x000,0,3,0,0,1,0
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219 .set __base,__base+1
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220
152
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221 // Invalid
201
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222 .rept 0xE00 - 0xD01
152
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223 .word 0
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224 .set __base,__base+1
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225 .endr
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226
201
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227 // Uncached and unbuffered alias for first 256MB of SDRAM. This
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228 // area can be used by device drivers for DMA operations. Buffers
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229 // should be cache aligned.
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230 .set __base,0xA00
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231 .rept 0xF00 - 0xE00
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232 FL_SECTION_ENTRY __base,0,3,0,0,0,0
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233 .set __base,__base+1
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234 .endr
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235
152
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236 // only I/O at 0xFE8xxxxx
201
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237 .set __base,0xF00
152
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238 .rept 0x1000 - 0xF00
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239 FL_SECTION_ENTRY __base,0,3,0,0,0,0
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240 .set __base,__base+1
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241 .endr
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242
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243 // Immediately after the above table (at 0x8000) is the
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244 // second level page table which breaks up the lowest 1MB
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245 // of physical memory into 4KB sized virtual pages. These
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246 // pages work around a hole in flash (0x1000-0x1fff) used
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247 // by the Yavapai companion chip internal registers.
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248 mmu_table_flashbase:
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249 // Virtual address 0 (Flash boot code).
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250 // Map 4k page at 0x00000000 virt --> 0xA0000000 physical
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251 // This allows us to have a writable vector table.
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252 // Read-Write, cacheable, bufferable
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253 SL_XSMPAGE_ENTRY 0xa0000,1,3,1,1
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254
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255 // Virtual address 0x1000 (Memory mapped registers)
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256 // Map 1-to-1, but don't cache or buffer
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257 // Read-Write, non-cacheable, non-bufferable
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258 .set __base,1
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259 SL_SMPAGE_ENTRY __base,3,3,3,3,0,0
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260 .set __base,__base+1
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261
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262 // Virtual address 0x2000-0x100000 (remainder of flash1)
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263 // Read-Write, cacheable, non-bufferable
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264 .rept 0x100 - 0x2
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265 SL_SMPAGE_ENTRY __base,3,3,3,3,1,0
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266 .set __base,__base+1
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267 .endr
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268
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269 // Now is the second level table for the first megabyte
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270 // of DRAM.
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271 mmu_table_rambase:
177
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272 // Map first meg of SDRAM
157
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273 // Read-Write, cacheable, bufferable
177
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274 .set __base,0xA0000
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275 .rept 0x100
152
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276 SL_XSMPAGE_ENTRY __base,1,3,1,1
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277 .set __base,__base+1
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278 .endr
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279
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280 _real_platform_setup:
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281 // Drain write and fill buffer
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282 mcr p15,0,r0,c7,c10,4
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283 CPWAIT r0
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284
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285 // Disable write buffer coalescing
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286 mrc p15,0,r0,c1,c0,1
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287 orr r0,r0,#1 // set the disable bit
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288 mcr p15,0,r0,c1,c0,1
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289 CPWAIT r0
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290
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291 // Delay appx 60 ms to let battery-backup reset complete
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292 DELAY_FOR 0x400000, r0
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293 // Eventually we will be able to check a register bit
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294 // to determine when this is complete
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295
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296 HEX_DISPLAY r0, r1, DISPLAY_0, DISPLAY_1
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297
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298 //
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299 // *** I2C interface initialization ***
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300 //
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301
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302 // Setup I2C Slave Address Register
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303 ldr r1, =I2C_DEVID // Load slave address r1.
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304 ldr r2, =ISAR_ADDR // Load address of the I2C Slave Address Register in r2.
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305 ldr r3, =0x0000007f // Load mask in r3.
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306 and r1, r3, r3 // The mask zeroes the 25 MSBs of r1 just to make sure.
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307 str r3, [r2] // Save the value 0x02 (I2C_DEVID) in the register.
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308
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309 // Setup I2C Clock Count Register
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310 ldr r2, =ICCR_ADDR // Load the address of the I2C Clock Control Register in r2.
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311 ldr r3, =0x0000014d // Set for 5.05 us transition time at 66MHz (0x14D = 333).
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312 str r3, [r2] // Save the value in the register.
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313
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314 // Enable I2C Interface Unit - status will be polled
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315 ldr r2, =ICR_ADDR // Load the address of the Control Register in r2.
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316 ldr r1, =ICR_GCALL // Disable General Call (will be master)
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317 ldr r3, =ICR_ENB // Enable I2C unit ).
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318 orr r1, r3, r1 // OR the two and store in R1
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319 ldr r3, =ICR_SCLENB // Enable I2C Clock Generator disabled
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320 orr r1, r3, r1 // OR the two and store in R1
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321 str r1, [r2] // Save the value to the Control Register.
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322
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323 //
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324 // *** Now read the SPD Data ***
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325 //
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326
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327 // Pointers to I2C Registers
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328 ldr r11, =ICR_ADDR // Load the address of the I2C Control Register in r11.
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329 ldr r12, =ISR_ADDR // Load the address of the I2C Status Register in r12.
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330 ldr r13, =IDBR_ADDR // Load the address of the I2C Data Buffer Register in r13.
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331
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332 // Initialize byte counters
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333 ldr r6, =0x00000000 // Counter incremented before byte is read
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334 ldr r7, =0x00000040 // Number of bytes to read in the Presence Detect EEPROM of SDRAM: 64 bytes
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335 ldr r5, =0x00000000 // R5 has running checksum calculation
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336 ldr r9, =I2C_TIMOUT // Timeout limit in case EEPROM does not respond
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337
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338 // At the end of all this, R4 has DRAM size, R8 has bank count, and R10 has Bank size
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339 ldr r10,=0x00000000 // Bank size
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340 ldr r8, =0x00000000 // Bank count
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341 ldr r4, =0x00000000 // SDRAM size
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342
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343 /* FREE REGISTERS ARE R0 - R3 */
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344
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345 // *** Put out address, with WRITE mode ***
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346
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347 // Set SDRAM module address and write mode
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348 ldr r1, =SDRAM_DEVID // Load slave address for SDRAM module: 0xA2 (Presence Detect Data)
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349 bic r1, r1, #IDBR_MODE // Clear read bit (bit #0)
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350 str r1, [r13] // Store to data register
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351
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352 // Initiate dummy write to set EEPROM pointer to 0
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353 ldr r1, [r11] // read the current Control Register value
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354 orr r1, r1, #ICR_START // Set start bit
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355 orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
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356 str r1, [r11] // Store to control register
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357
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358 // Wait for transmit empty status
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359 ldr r1, =0x00000000 // Initialize I2C timeout counter
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360 0:
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361 add r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
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362 cmp r1, r9
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363 beq i2c_error // Kick out of SDRAM initialization if timeout occurs
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364 ldr r0, [r12] // Load I2C Status Reg into R0
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365 str r2, =ISR_EMPTY // Poll status register
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366 and r3, r2, r0 // Bit #6 is checked: IDBR Transmit Empty
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367 cmp r3, r2 // If bit = 0 then branch to 0 and check again
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368 bne 0b
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369 str r0, [r12] // Write back status to clear
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370
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371 // *** Write pointer register on EEPROM to 0x00000000 ***
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372
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373 // Set SDRAM module EEPROM address to 0
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374 ldr r1, =0x00000000 // Load base address of SDRAM module EEPROM
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375 str r1, [r13] // Store to data register
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376
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377 // Send address to EEPROM
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378 ldr r1, [r11] // read the current Control Register value
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379 bic r1, r1, #ICR_START // No start bit (already started)
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380 orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
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381 str r1, [r11] // Store to control register
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382
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383 // Wait for transmit empty status
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384 ldr r1, =0x00000000 // Initialize I2C timeout counter
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385 0:
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386 add r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
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387 cmp r1, r9
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388 beq i2c_error // Kick out of SDRAM initialization if timeout occurs
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389 ldr r0, [r12] // Load I2C Status Reg into R0 - ld (r12), r10
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390 str r2, =ISR_EMPTY // Poll status register
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391 and r3, r2, r0 // Bit #6 is checked: IDBR Transmit Empty
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392 cmp r3, r2 // If bit = 0 then branch to 0 and check again (r3 = 0x00)
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393 bne 0b
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394 str r0, [r12] // Write back status to clear
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395
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396 // *** Read SDRAM PD data ***
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397
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398 // *** Put out address, with READ mode ***
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399
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400 // Set SDRAM module address and read mode
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401 ldr r0, =SDRAM_DEVID // Load slave address for SDRAM module (0xA2)
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402 orr r1, r0, #IDBR_MODE // Set read bit (bit #0)
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403 str r1, [r13] // Store to data register
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404
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405 // Send next read request
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406 ldr r1, [r11] // read the current Control Register value
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407 orr r1, r1, #ICR_START // Set start bit
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408 orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
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409 str r1, [r11] // Store to control register
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diff changeset
410
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jlarmour
parents:
diff changeset
411 // Wait for transmit empty status
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jlarmour
parents:
diff changeset
412 ldr r1, =0x00000000 // Initialize I2C timeout counter
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jlarmour
parents:
diff changeset
413 0:
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jlarmour
parents:
diff changeset
414 add r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
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jlarmour
parents:
diff changeset
415 cmp r1, r9
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jlarmour
parents:
diff changeset
416 beq i2c_error // Kick out of SDRAM initialization if timeout occurs
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jlarmour
parents:
diff changeset
417 ldr r0, [r12] // Load I2C Status Reg into R0 - ld (r12), r10
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jlarmour
parents:
diff changeset
418 str r2, =ISR_EMPTY // Poll status register
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jlarmour
parents:
diff changeset
419 and r3, r2, r0 // Bit #6 is checked: IDBR Transmit Empty
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
420 cmp r3, r2 // If bit = 0 then branch to 0 and check again (r3 = 0x00)
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jlarmour
parents:
diff changeset
421 bne 0b
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jlarmour
parents:
diff changeset
422 str r0, [r12] // Write back status to clear
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jlarmour
parents:
diff changeset
423
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jlarmour
parents:
diff changeset
424 sdram_loop:
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jlarmour
parents:
diff changeset
425 add r6, r6, #1 // Increment byte counter
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jlarmour
parents:
diff changeset
426
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jlarmour
parents:
diff changeset
427 // *** READ the next Byte!!! ***
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jlarmour
parents:
diff changeset
428
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jlarmour
parents:
diff changeset
429 ldr r1, [r11] // read the current Control Register value
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jlarmour
parents:
diff changeset
430 bic r1, r1, #ICR_START // No start bit (already started)
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jlarmour
parents:
diff changeset
431 orr r1, r1, #ICR_TRANSFER // Set transfer bit - bit is self_clearing
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jlarmour
parents:
diff changeset
432
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jlarmour
parents:
diff changeset
433 // we have to set NACK before reading the last bit
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jlarmour
parents:
diff changeset
434 cmp r6, r7 // r7 = 64 (decimal) so if r6 = 64, this is the last byte to be read
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jlarmour
parents:
diff changeset
435 bne 1f // If bytes left, skip ahead
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jlarmour
parents:
diff changeset
436 orr r1, r1, #ICR_ACK // Set NACK if this is the last byte
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jlarmour
parents:
diff changeset
437 orr r1, r1, #ICR_STOP // Set STOP if this is the last byte
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jlarmour
parents:
diff changeset
438 1:
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jlarmour
parents:
diff changeset
439 str r1, [r11] // Store to control register
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jlarmour
parents:
diff changeset
440
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jlarmour
parents:
diff changeset
441 // Wait for read full status
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jlarmour
parents:
diff changeset
442 ldr r1, =0x00000000 // Initialize I2C timeout counter
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jlarmour
parents:
diff changeset
443 0:
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jlarmour
parents:
diff changeset
444 add r1, r1, #1 // Increment I2C timeout counter (r1 = r1 + 1)
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jlarmour
parents:
diff changeset
445 cmp r1, r9
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jlarmour
parents:
diff changeset
446 beq i2c_error // Kick out of SDRAM initialization if timeout occurs
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jlarmour
parents:
diff changeset
447 ldr r0, [r12] // Load I2C Status Reg into R0
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jlarmour
parents:
diff changeset
448 str r2, =ISR_FULL // Poll status register
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jlarmour
parents:
diff changeset
449 and r3, r2, r0 // Bit #6 is checked: IDBR Transmit Empty
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jlarmour
parents:
diff changeset
450 cmp r3, r2 // If bit = 0 then branch to 0 and check again
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jlarmour
parents:
diff changeset
451 bne 0b
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jlarmour
parents:
diff changeset
452 str r0, [r12] // Write back status to clear
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jlarmour
parents:
diff changeset
453
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jlarmour
parents:
diff changeset
454 // Read the data byte
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jlarmour
parents:
diff changeset
455 ldr r1, [r13] // Read the byte
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jlarmour
parents:
diff changeset
456
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jlarmour
parents:
diff changeset
457 ldr r2, =CHECKSUM_BYTE
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jlarmour
parents:
diff changeset
458 cmp r6, r2 // is it the CHECKSUM byte???
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jlarmour
parents:
diff changeset
459 beq 1f
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parents:
diff changeset
460 add r5, r5, r1 // Add it to the checksum if not the checksum byte
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jlarmour
parents:
diff changeset
461 bal 2f // skip checksum comparison
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jlarmour
parents:
diff changeset
462 1:
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jlarmour
parents:
diff changeset
463 ldr r0, =0xff // If this is the checksum byte, compare it
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jlarmour
parents:
diff changeset
464 and r5, r5, r0 // against the calculated checksum
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jlarmour
parents:
diff changeset
465 cmp r1, r5
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jlarmour
parents:
diff changeset
466 bne bad_checksum // If no match, skip SDRAM controller initialization
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jlarmour
parents:
diff changeset
467 2:
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jlarmour
parents:
diff changeset
468 ldr r2, =BANKCNT_BYTE // Check for bank count byte
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jlarmour
parents:
diff changeset
469 cmp r6, r2
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jlarmour
parents:
diff changeset
470 bne 1f
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jlarmour
parents:
diff changeset
471 mov r8, r1 // Store bank count
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parents:
diff changeset
472 1:
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jlarmour
parents:
diff changeset
473 ldr r2, =BANKSZ_BYTE // Check for bank size byte
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jlarmour
parents:
diff changeset
474 cmp r6, r2
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jlarmour
parents:
diff changeset
475 bne 1f
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parents:
diff changeset
476
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jlarmour
parents:
diff changeset
477 ldr r2, =0x04 // Store bank size in Mbytes (shift left 2 bits)
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jlarmour
parents:
diff changeset
478 mul r10, r1, r2
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jlarmour
parents:
diff changeset
479 mul r2, r8, r10 // Multiply by bank count to get DRAM size in MB
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jlarmour
parents:
diff changeset
480 ldr r0, =0x100000
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jlarmour
parents:
diff changeset
481 mul r4, r2, r0 // Convert size to bytes - r4 contains DRAM size in bytes
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jlarmour
parents:
diff changeset
482
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jlarmour
parents:
diff changeset
483 1:
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jlarmour
parents:
diff changeset
484 // Handle the SDRAM drive strength setup here since we are out of
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jlarmour
parents:
diff changeset
485 // temporary registers to hold the SDRAM width value until after
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jlarmour
parents:
diff changeset
486 // all of the SPD data has been read. Using the value of r8 for
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jlarmour
parents:
diff changeset
487 // the Bank Count is allright here since the SPD specification states that
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jlarmour
parents:
diff changeset
488 // the Bank Count SPD byte is #5 and the SDRAM Width SPD byte is #13.
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jlarmour
parents:
diff changeset
489
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jlarmour
parents:
diff changeset
490 ldr r2, =SDRAM_WIDTH_BYTE // Check for SDRAM width byte
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jlarmour
parents:
diff changeset
491 cmp r6, r2
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jlarmour
parents:
diff changeset
492 bne 1f
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jlarmour
parents:
diff changeset
493 mov r2, #0x10 // Check for data width of 16
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jlarmour
parents:
diff changeset
494 cmp r1, r2
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jlarmour
parents:
diff changeset
495 bne SDRAM_DRIVE_X8
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jlarmour
parents:
diff changeset
496
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jlarmour
parents:
diff changeset
497 // Module is composed of x16 devices
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jlarmour
parents:
diff changeset
498 mov r2, #0x02
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jlarmour
parents:
diff changeset
499 cmp r2, r8 // do we have 2 banks???
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jlarmour
parents:
diff changeset
500 beq SDRAM_DRIVE_2_BANK_X16
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jlarmour
parents:
diff changeset
501
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
502 // Module is composed of 1 Bank of x16 devices
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jlarmour
parents:
diff changeset
503 ldr r1, =SDCR_ADDR // point at SDRAM Control Register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
504 ldr r2, =SDCR_1BANK_X16 // drive strength value
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jlarmour
parents:
diff changeset
505 str r2, [r1] // set value in SDCR
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jlarmour
parents:
diff changeset
506 b 1f
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jlarmour
parents:
diff changeset
507
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
508 SDRAM_DRIVE_2_BANK_X16:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
509 // Module is composed of 2 Banks of x16 devices
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jlarmour
parents:
diff changeset
510 ldr r1, =SDCR_ADDR // point at SDRAM Control Register
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jlarmour
parents:
diff changeset
511 ldr r2, =SDCR_2BANK_X16 // drive strength value
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jlarmour
parents:
diff changeset
512 str r2, [r1] // set value in SDCR
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jlarmour
parents:
diff changeset
513 b 1f
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jlarmour
parents:
diff changeset
514
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jlarmour
parents:
diff changeset
515 SDRAM_DRIVE_X8:
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jlarmour
parents:
diff changeset
516 // Module is composed of x8 devices
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jlarmour
parents:
diff changeset
517 mov r2, #0x02
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jlarmour
parents:
diff changeset
518 cmp r2, r8 // do we have 2 banks???
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jlarmour
parents:
diff changeset
519 beq SDRAM_DRIVE_2_BANK_X8
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jlarmour
parents:
diff changeset
520
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
521 // Module is composed of 1 Bank of x8 devices
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jlarmour
parents:
diff changeset
522 ldr r1, =SDCR_ADDR // point at SDRAM Control Register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
523 ldr r2, =SDCR_1BANK_X8 // drive strength value
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jlarmour
parents:
diff changeset
524 str r2, [r1] // set value in SDCR
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jlarmour
parents:
diff changeset
525 b 1f
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jlarmour
parents:
diff changeset
526
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
527 SDRAM_DRIVE_2_BANK_X8:
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jlarmour
parents:
diff changeset
528 // Module is composed of 2 Banks of x16 devices
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jlarmour
parents:
diff changeset
529 ldr r1, =SDCR_ADDR // point at SDRAM Control Register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
530 ldr r2, =SDCR_2BANK_X8 // drive strength value
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jlarmour
parents:
diff changeset
531 str r2, [r1] // set value in SDCR
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jlarmour
parents:
diff changeset
532 1:
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jlarmour
parents:
diff changeset
533
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
534
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
535 // Continue reading bytes if not done
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
536 cmp r6, r7
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jlarmour
parents:
diff changeset
537 bne sdram_loop
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jlarmour
parents:
diff changeset
538
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jlarmour
parents:
diff changeset
539 b i2c_disable
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jlarmour
parents:
diff changeset
540
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jlarmour
parents:
diff changeset
541 bad_checksum:
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jlarmour
parents:
diff changeset
542 HEX_DISPLAY r2, r3, DISPLAY_7, DISPLAY_7
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
543
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jlarmour
parents:
diff changeset
544 i2c_error:
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jlarmour
parents:
diff changeset
545 // hit the leds if an error occurred
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jlarmour
parents:
diff changeset
546 HEX_DISPLAY r2, r3, DISPLAY_5, DISPLAY_5
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jlarmour
parents:
diff changeset
547
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
548
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
549 i2c_disable:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
550 // Disable I2C Interface Unit
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
551 ldr r1, [r11]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
552 bic r1, r1, #ICR_ENB // Disable I2C unit
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
553 bic r1, r1, #ICR_SCLENB // Disable I2C clock generator
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
554 str r1, [r11] // Store to control register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
555
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
556 // ADD THIS???:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
557 // cmpobne 1, g9, test_init
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
558 // Skip SDRAM controller initialization if checksum test failed
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
559
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
560 // *** SDRAM setup ***
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
561
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
562 ldr r9, =MMR_BASE // get base of MMRs
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
563 ldr r0, =RAM_BASE // Program SDRAM Base Address register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
564 str r0, [r9, #SDBR_OFF]
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jlarmour
parents:
diff changeset
565
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
566 // Set up bank 0 register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
567 CHECK_32MB:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
568 ldr r1, =RAM_32MEG // do we have 32 MB banks?
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
569 cmp r10, r1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
570 bne CHECK_64MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
571
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
572 ldr r0, =SBR_32MEG // Program SDRAM Bank0 Boundary register to 32 MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
573 b SET_BANK1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
574
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jlarmour
parents:
diff changeset
575 CHECK_64MB:
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jlarmour
parents:
diff changeset
576 ldr r1, =RAM_64MEG // do we have 64 MB banks?
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
577 cmp r10, r1
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jlarmour
parents:
diff changeset
578 bne CHECK_128MB
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jlarmour
parents:
diff changeset
579
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jlarmour
parents:
diff changeset
580 ldr r0, =SBR_64MEG // Program SDRAM Bank0 Boundary register to 64 MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
581 b SET_BANK1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
582
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
583 CHECK_128MB:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
584 ldr r1, =RAM_128MEG // do we have 128 MB banks?
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
585 cmp r10, r1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
586 bne CHECK_256MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
587
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jlarmour
parents:
diff changeset
588 ldr r0, =SBR_128MEG // Program SDRAM Bank0 Boundary register to 128 MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
589 b SET_BANK1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
590
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
591 CHECK_256MB:
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jlarmour
parents:
diff changeset
592 ldr r1, =RAM_256MEG // do we have 256 MB banks?
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
593 cmp r10, r1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
594 bne dram_error
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jlarmour
parents:
diff changeset
595
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
596 ldr r0, =SBR_256MEG // Program SDRAM Bank0 Boundary register to 64 MB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
597 b SET_BANK1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
598
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
599 SET_BANK1:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
600 str r0, [r9, #SBR0_OFF] // store SBR0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
601
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
602 ldr r2, =0x02
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
603 cmp r2, r8 // do we have 2 banks???
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jlarmour
parents:
diff changeset
604 bne SDRAM_1_BANK
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jlarmour
parents:
diff changeset
605
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jlarmour
parents:
diff changeset
606 add r0, r0, r0 // SDRAM Bank1 Boundary register is double SBR0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
607 str r0, [r9, #SBR1_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
608 b END_DRAM_SIZE
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jlarmour
parents:
diff changeset
609
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jlarmour
parents:
diff changeset
610 SDRAM_1_BANK:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
611 // SDRAM Bank1 Boundary register is same as SBR0 for 1 bank configuration
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
612 str r0, [r9, #SBR1_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
613 b END_DRAM_SIZE
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
614
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
615 END_DRAM_SIZE:
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jlarmour
parents:
diff changeset
616 b init_dram
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jlarmour
parents:
diff changeset
617
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jlarmour
parents:
diff changeset
618 dram_error:
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jlarmour
parents:
diff changeset
619
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jlarmour
parents:
diff changeset
620 HEX_DISPLAY r2, r3, DISPLAY_F, DISPLAY_F
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
621
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jlarmour
parents:
diff changeset
622 init_dram:
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jlarmour
parents:
diff changeset
623 ldr r0, =0 // turn off refresh
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
624 str r0, [r9, #RFR_OFF]
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jlarmour
parents:
diff changeset
625
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
626 ldr r0, =MRS_NO_OP // Issue NOP cmd to SDRAM
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
627 str r0, [r9, #SDIR_OFF]
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jlarmour
parents:
diff changeset
628 DELAY_FOR 0x4000, r0
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jlarmour
parents:
diff changeset
629
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jlarmour
parents:
diff changeset
630 ldr r0, =MRS_PRECHRG // Issue 1 Precharge all
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
631 str r0, [r9, #SDIR_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
632 DELAY_FOR 0x4000, r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
633
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
634
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
635 ldr r0, =MRS_AUTO_RFRSH // Issue 1 Auto Refresh command
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
636 str r0, [r9, #SDIR_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
637 DELAY_FOR 0x4000, r0
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jlarmour
parents:
diff changeset
638
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
639
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
640 ldr r0, =MRS_AUTO_RFRSH
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
641 str r0, [r9, #SDIR_OFF] // Auto Refresh #1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
642 str r0, [r9, #SDIR_OFF] // Auto Refresh #2
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
643 str r0, [r9, #SDIR_OFF] // Auto Refresh #3
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
644 str r0, [r9, #SDIR_OFF] // Auto Refresh #4
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
645 str r0, [r9, #SDIR_OFF] // Auto Refresh #5
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
646 str r0, [r9, #SDIR_OFF] // Auto Refresh #6
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
647 str r0, [r9, #SDIR_OFF] // Auto Refresh #7
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
648 str r0, [r9, #SDIR_OFF] // Auto Refresh #8
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
649
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
650 ldr r0, =MRS_CAS_LAT_2 // set the CAS latency
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
651 str r0, [r9, #SDIR_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
652 DELAY_FOR 0x4000, r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
653
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
654 ldr r0, =MRS_NORM_OP // Issue a Normal Operation command
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
655 str r0, [r9, #SDIR_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
656
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
657 ldr r0, =RFR_INIT_VAL // Program Refresh Rate register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
658 str r0, [r9, #RFR_OFF]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
659
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
660 // ldr r0, =(FLASH_BASE :AND: &FFFF0000)
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
661 // str r0, [r10, #FEBR1_OFF] ; Program Flash Bank1 Base Address register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
662
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
663 // ldr r0, =(FLASH_SIZE :AND: &FFFF0000)
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
664 // str r0, [r10, #FBSR1_OFF] ; Program Flash Bank1 Size register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
665
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
666 // ldr r0, =FWSR0_INIT_VAL
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
667 // str r0, [r10, #FWSR0_OFF] ; Program Flash Bank0 Wait State register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
668
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
669 // ldr r0, =FWSR1_INIT_VAL
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
670 // str r0, [r10, #FWSR1_OFF] ; Program Flash Bank1 Wait State register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
671
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
672 HEX_DISPLAY r0, r1, DISPLAY_0, DISPLAY_2
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
673
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
674 // begin initializing the i80310
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
675
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
676 // Enable access to all coprocessor registers
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
677 ldr r0, =0x2001 // enable access to all coprocessors
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
678 mcr p15, 0, r0, c15, c1, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
679
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
680 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
681 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
682
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
683 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
684 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
685
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
686 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
687 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
688
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
689 // Enable the Icache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
690 mrc p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
691 orr r0, r0, #MMU_Control_I
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
692 mcr p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
693 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
694
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
695 // Set the TTB register
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
696 ldr r0, =mmu_table
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
697 mcr p15, 0, r0, c2, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
698
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
699 // Enable permission checks in all domains
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
700 ldr r0, =0x55555555
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
701 mcr p15, 0, r0, c3, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
702
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
703 // Enable the MMU
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
704 mrc p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
705 orr r0, r0, #MMU_Control_M
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
706 orr r0, r0, #MMU_Control_R
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
707 mcr p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
708 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
709
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
710 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
711 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
712
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
713 // Enable the Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
714 mrc p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
715 orr r0, r0, #MMU_Control_C
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
716 mcr p15, 0, r0, c1, c0, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
717 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
718
182
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST
jlarmour
parents: 177
diff changeset
719 // Initialize branch target buffer
f62680ef1804 Merge from eCos master repository on 2001-09-07-06:43:02-BST
jlarmour
parents: 177
diff changeset
720 BTB_INIT r0
152
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
721
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
722 // Battery Backup SDRAM Memory Test
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
723 // Move 4 byte Test Pattern into register prior to zeroing out
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
724 // contents of SDRAM locations
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
725 ldr r9, =SDRAM_BATTERY_TEST_BASE
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
726 ldr r10, [r9]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
727
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
728 // scrub/init SDRAM if enabled/present
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
729 ldr r11, =RAM_BASE // base address of SDRAM
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
730 mov r12, r4 // size of memory to scrub
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
731 mov r8,r4 // save DRAM size
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
732 mov r0, #0 // scrub with 0x0000:0000
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
733 mov r1, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
734 mov r2, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
735 mov r3, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
736 mov r4, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
737 mov r5, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
738 mov r6, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
739 mov r7, #0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
740 10: // fastScrubLoop
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
741 subs r12, r12, #32 // 32 bytes/line
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
742 stmia r11!, {r0-r7}
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
743 beq 15f
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
744 b 10b
177
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
745 15:
152
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
746
177
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
747 // now copy 1st 4K page of flash into first 4K of RAM.
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
748 ldr r1, =RAM_BASE // base address of SDRAM
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
749 mov r2, #0xd0000000 // alias for first 1M of flash
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
750 mov r3, #0x1000
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
751 16:
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
752 ldr r4, [r2]
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
753 add r2, r2, #4
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
754 str r4, [r1]
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
755 add r1, r1, #4
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
756 subs r3, r3, #4
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
757 bne 16b
4c750ce71ae3 Merge from eCos master repository on 2001-08-10-19:22:57-BST
jlarmour
parents: 159
diff changeset
758
152
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
759 // Battery Backup SDRAM Memory Test
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
760 // Store 4 byte Test Pattern back into memory
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
761 str r10, [r9, #0x0]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
762
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
763 HEX_DISPLAY r0, r1, DISPLAY_1, DISPLAY_0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
764
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
765 // clean/drain/flush the main Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
766 mov r1, #DCACHE_FLUSH_AREA // use a CACHEABLE area of
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
767 // the memory map above SDRAM
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
768 mov r0, #1024 // number of lines in the Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
769 20:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
770 mcr p15, 0, r1, c7, c2, 5 // allocate a Dcache line
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
771 add r1, r1, #32 // increment the address to
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
772 // the next cache line
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
773 subs r0, r0, #1 // decrement the loop count
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
774 bne 20b
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
775
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
776 HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_9
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
777
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
778 // clean/drain/flush the mini Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
779 ldr r2, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
780 // the memory map above SDRAM
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
781 mov r0, #64 // number of lines in the mini Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
782 21:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
783 mcr p15, 0, r2, c7, c2, 5 // allocate a Dcache line
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
784 add r2, r2, #32 // increment the address to
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
785 // the next cache line
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
786 subs r0, r0, #1 // decrement the loop count
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
787 bne 21b
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
788
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
789 mcr p15, 0, r0, c7, c6, 0 // flush Dcache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
790 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
791
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
792 HEX_DISPLAY r0, r1, DISPLAY_7, DISPLAY_7
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
793
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
794 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
795 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
796
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
797 // enable ECC stuff here
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
798 mcr p15, 0, r0, c7, c10, 4 //
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
799 CPWAIT r0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
800
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
801 mrc p13, 0, r0, c0, c1, 0 // BCU_WAIT --> wait until the BCU isn't busy
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
802 submi pc, pc, #0xc
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
803
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
804 checkme: // add in multi-bit error reporting */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
805 mrc p13, 0, r0, c0, c1, 0 // disable ECC
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
806 and r0, r0, #(-1-8)
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
807 mcr p13, 0, r0, c0, c1, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
808 orr r0, r0, #6 // enable single-bit correction,
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
809 mcr p13, 0, r0, c0, c1, 0 // multi-bit detection
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
810 orr r0, r0, #8 // enable ECC
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
811 mcr p13, 0, r0, c0, c1, 0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
812
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
813 mrc p13, 0, r0, c0, c1, 0 // BCU_WAIT --> wait until the BCU isn't busy
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
814 submi pc, pc, #0xc
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
815
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
816 // Enable ECC circuitry in Yavapai
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
817 ldr r1, =ECCR_ADDR
158
f2545e5de153 Merge from eCos master repository on 2001-04-24-11:22:42-BST
jlarmour
parents: 157
diff changeset
818 mov r0, #0x6 // Enable single bit ECC Correction (Reporting Enabled)
152
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
819 str r0, [r1, #0]
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
820
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
821 HEX_DISPLAY r0, r1, DISPLAY_6, DISPLAY_6
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
822
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
823 #if 1
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jlarmour
parents:
diff changeset
824 mov r0, #0x1000000
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jlarmour
parents:
diff changeset
825 1: subs r0,r0,#1
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jlarmour
parents:
diff changeset
826 bne 1b
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jlarmour
parents:
diff changeset
827 #endif
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jlarmour
parents:
diff changeset
828 // Save SDRAM size
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diff changeset
829 ldr r1, =hal_dram_size /* [see hal_intr.h] */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
830 str r8, [r1]
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parents:
diff changeset
831
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
832 // Move mmu tables into RAM so page table walks by the cpu
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
833 // don't interfere with FLASH programming.
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jlarmour
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diff changeset
834 ldr r0, =mmu_table
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diff changeset
835 mov r4, r0
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diff changeset
836 add r2, r0, #0x4800 // End of tables
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
837 mov r1, #RAM_BASE
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parents:
diff changeset
838 orr r1, r1, #0x4000 // RAM tables
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parents:
diff changeset
839 mov r5, r1
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parents:
diff changeset
840
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
841 // first, fixup physical address to second level
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diff changeset
842 // table used to map first 1MB of flash.
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jlarmour
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diff changeset
843 ldr r3, [r0], #4
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jlarmour
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diff changeset
844 sub r3, r3, r4
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diff changeset
845 add r3, r3, r5
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jlarmour
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diff changeset
846 str r3, [r1], #4
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diff changeset
847 // everything else can go as-is
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jlarmour
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diff changeset
848 1:
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jlarmour
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diff changeset
849 ldr r3, [r0], #4
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diff changeset
850 str r3, [r1], #4
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diff changeset
851 cmp r0, r2
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diff changeset
852 bne 1b
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diff changeset
853
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
854 // go back and fixup physical address to second level
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
855 // table used to map first 1MB of SDRAM.
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
856 add r1, r5, #(0xA00 * 4)
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
857 ldr r0, [r1] // entry for first 1MB of DRAM
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
858 sub r0, r0, r4
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jlarmour
parents:
diff changeset
859 add r0, r0, r5
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jlarmour
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diff changeset
860 str r0, [r1] // store it back
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diff changeset
861
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diff changeset
862 // Flush the cache
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diff changeset
863 mov r0, #DCACHE_FLUSH_AREA /* cache flush region */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
864 add r1, r0, #0x8000 /* 32KB cache */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
865 667:
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
866 mcr p15,0,r0,c7,c2,5 /* allocate a line */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
867 add r0, r0, #32 /* 32 bytes/line */
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jlarmour
parents:
diff changeset
868 teq r1, r0
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jlarmour
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diff changeset
869 bne 667b
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diff changeset
870 mcr p15,0,r0,c7,c6,0 /* invalidate data cache */
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jlarmour
parents:
diff changeset
871 /* cpuwait */
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jlarmour
parents:
diff changeset
872 mrc p15,0,r1,c2,c0,0 /* arbitrary read */
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jlarmour
parents:
diff changeset
873 mov r1,r1
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jlarmour
parents:
diff changeset
874 sub pc,pc,#4
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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diff changeset
875 mcr p15,0,r0,c7,c10,4
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jlarmour
parents:
diff changeset
876 /* cpuwait */
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jlarmour
parents:
diff changeset
877 mrc p15,0,r1,c2,c0,0 /* arbitrary read */
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jlarmour
parents:
diff changeset
878 mov r1,r1
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jlarmour
parents:
diff changeset
879 sub pc,pc,#4
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jlarmour
parents:
diff changeset
880 nop
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
881
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
882 HEX_DISPLAY r0, r1, DISPLAY_5, DISPLAY_2
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
883
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
884 // Set the TTB register to DRAM mmu_table
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
885 mov r0, r5
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parents:
diff changeset
886 mov r1, #0
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diff changeset
887 mcr p15, 0, r1, c7, c5, 0 // flush I cache
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
888 mcr p15, 0, r1, c7, c10, 4 // drain WB
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
889 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
890 mcr p15, 0, r1, c8, c7, 0 // flush TLBs
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
891 CPWAIT r0
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jlarmour
parents:
diff changeset
892
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
893 // Interrupt init
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jlarmour
parents:
diff changeset
894 mov r0, #0 // enable no sources
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jlarmour
parents:
diff changeset
895 mcr p13,0,r0,c0,c0,0 // write to INTCTL
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jlarmour
parents:
diff changeset
896 // Steer both BCU and PMU to IRQ
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
897 mcr p13,0,r0,c8,c0,0 // write to INTSTR
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
898
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
899 mov r0,#0
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jlarmour
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diff changeset
900 mcr p15,0,r0,c14,c8,0 // ibcr0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
901 mcr p15,0,r0,c14,c9,0 // ibcr1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
902 mcr p15,0,r0,c14,c4,0 // dbcon
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
903 mov r0,#0x80000000
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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parents:
diff changeset
904 mcr p14,0,r0,c10,c0,0 // dcsr
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
905
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
906 HEX_DISPLAY r0, r1, DISPLAY_0, DISPLAY_0
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
907
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
908 .endm // _platform_setup1
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
909
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
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diff changeset
910
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
911 #define PLATFORM_VECTORS _platform_vectors
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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parents:
diff changeset
912 .macro _platform_vectors
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
913 .globl _80312_EMISR
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
914 _80312_EMISR: .long 0 // Companion chip "clear-on-read" interrupt status
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
915 // register for the performance monitor unit.
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
916 .endm
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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parents:
diff changeset
917
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
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parents:
diff changeset
918 /*---------------------------------------------------------------------------*/
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
919 /* end of hal_platform_setup.h */
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jlarmour
parents:
diff changeset
920 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
f935b880e96c Merge from eCos master repository on 2001-02-14-01:27:14-GMT
jlarmour
parents:
diff changeset
921